{$IFDEF OGC_INTERFACE}

{$ifdef _LANGUAGE_ASSEMBLY}
(* Condition Register Bit Fields  *)

const
  cr0 = 0;
  cr1 = 1;
  cr2 = 2;
  cr3 = 3;
  cr4 = 4;
  cr5 = 5;
  cr6 = 6;
  cr7 = 7;

  (* General Purpose Registers (GPRs)  *)
  r0 = 0;
  r1 = 1;
  sp = 1;
  r2 = 2;
  toc = 2;
  r3 = 3;
  r4 = 4;
  r5 = 5;
  r6 = 6;
  r7 = 7;
  r8 = 8;
  r9 = 9;
  r10 = 10;
  r11 = 11;
  r12 = 12;
  r13 = 13;
  r14 = 14;
  r15 = 15;
  r16 = 16;
  r17 = 17;
  r18 = 18;
  r19 = 19;
  r20 = 20;
  r21 = 21;
  r22 = 22;
  r23 = 23;
  r24 = 24;
  r25 = 25;
  r26 = 26;
  r27 = 27;
  r28 = 28;
  r29 = 29;
  r30 = 30;
  r31 = 31;

  (* Floating Point Registers (FPRs)  *)
  fr0 = 0;
  fr1 = 1;
  fr2 = 2;
  fr3 = 3;
  fr4 = 4;
  fr5 = 5;
  fr6 = 6;
  fr7 = 7;
  fr8 = 8;
  fr9 = 9;
  fr10 = 10;
  fr11 = 11;
  fr12 = 12;
  fr13 = 13;
  fr14 = 14;
  fr15 = 15;
  fr16 = 16;
  fr17 = 17;
  fr18 = 18;
  fr19 = 19;
  fr20 = 20;
  fr21 = 21;
  fr22 = 22;
  fr23 = 23;
  fr24 = 24;
  fr25 = 25;
  fr26 = 26;
  fr27 = 27;
  fr28 = 28;
  fr29 = 29;
  fr30 = 30;
  fr31 = 31;
  vr0 = 0;
  vr1 = 1;
  vr2 = 2;
  vr3 = 3;
  vr4 = 4;
  vr5 = 5;
  vr6 = 6;
  vr7 = 7;
  vr8 = 8;
  vr9 = 9;
  vr10 = 10;
  vr11 = 11;
  vr12 = 12;
  vr13 = 13;
  vr14 = 14;
  vr15 = 15;
  vr16 = 16;
  vr17 = 17;
  vr18 = 18;
  vr19 = 19;
  vr20 = 20;
  vr21 = 21;
  vr22 = 22;
  vr23 = 23;
  vr24 = 24;
  vr25 = 25;
  vr26 = 26;
  vr27 = 27;
  vr28 = 28;
  vr29 = 29;
  vr30 = 30;
  vr31 = 31;
{$endif _LANGUAGE_ASSEMBLY}

const
  SPRG0 = 272;
  SPRG1 = 273;
  SPRG2 = 274;
  SPRG3 = 275;
  PMC1 = 953;
  PMC2 = 954;
  PMC3 = 957;
  PMC4 = 958;
  MMCR0 = 952;
  MMCR1 = 956;
  LINK_REGISTER_CALLEE_UPDATE_ROOM = 4;
  EXCEPTION_NUMBER = 8;
  SRR0_OFFSET = 12;
  SRR1_OFFSET = 16;
  GPR0_OFFSET = 20;
  GPR1_OFFSET = 24;
  GPR2_OFFSET = 28;
  GPR3_OFFSET = 32;
  GPR4_OFFSET = 36;
  GPR5_OFFSET = 40;
  GPR6_OFFSET = 44;
  GPR7_OFFSET = 48;
  GPR8_OFFSET = 52;
  GPR9_OFFSET = 56;
  GPR10_OFFSET = 60;
  GPR11_OFFSET = 64;
  GPR12_OFFSET = 68;
  GPR13_OFFSET = 72;
  GPR14_OFFSET = 76;
  GPR15_OFFSET = 80;
  GPR16_OFFSET = 84;
  GPR17_OFFSET = 88;
  GPR18_OFFSET = 92;
  GPR19_OFFSET = 96;
  GPR20_OFFSET = 100;
  GPR21_OFFSET = 104;
  GPR22_OFFSET = 108;
  GPR23_OFFSET = 112;
  GPR24_OFFSET = 116;
  GPR25_OFFSET = 120;
  GPR26_OFFSET = 124;
  GPR27_OFFSET = 128;
  GPR28_OFFSET = 132;
  GPR29_OFFSET = 136;
  GPR30_OFFSET = 140;
  GPR31_OFFSET = 144;
  GQR0_OFFSET = 148;
  GQR1_OFFSET = 152;
  GQR2_OFFSET = 156;
  GQR3_OFFSET = 160;
  GQR4_OFFSET = 164;
  GQR5_OFFSET = 168;
  GQR6_OFFSET = 172;
  GQR7_OFFSET = 176;
  CR_OFFSET = 180;
  LR_OFFSET = 184;
  CTR_OFFSET = 188;
  XER_OFFSET = 192;
  MSR_OFFSET = 196;
  DAR_OFFSET = 200;
  STATE_OFFSET = 204;
  MODE_OFFSET = 206;

  FPR0_OFFSET = 208;
  FPR1_OFFSET = 216;
  FPR2_OFFSET = 224;
  FPR3_OFFSET = 232;
  FPR4_OFFSET = 240;
  FPR5_OFFSET = 248;
  FPR6_OFFSET = 256;
  FPR7_OFFSET = 264;
  FPR8_OFFSET = 272;
  FPR9_OFFSET = 280;
  FPR10_OFFSET = 288;
  FPR11_OFFSET = 296;
  FPR12_OFFSET = 304;
  FPR13_OFFSET = 312;
  FPR14_OFFSET = 320;
  FPR15_OFFSET = 328;
  FPR16_OFFSET = 336;
  FPR17_OFFSET = 344;
  FPR18_OFFSET = 352;
  FPR19_OFFSET = 360;
  FPR20_OFFSET = 368;
  FPR21_OFFSET = 376;
  FPR22_OFFSET = 384;
  FPR23_OFFSET = 392;
  FPR24_OFFSET = 400;
  FPR25_OFFSET = 408;
  FPR26_OFFSET = 416;
  FPR27_OFFSET = 424;
  FPR28_OFFSET = 432;
  FPR29_OFFSET = 440;
  FPR30_OFFSET = 448;
  FPR31_OFFSET = 456;
  FPSCR_OFFSET = 464;
  PSR0_OFFSET = 472;
  PSR1_OFFSET = 480;
  PSR2_OFFSET = 488;
  PSR3_OFFSET = 496;
  PSR4_OFFSET = 504;
  PSR5_OFFSET = 512;
  PSR6_OFFSET = 520;
  PSR7_OFFSET = 528;
  PSR8_OFFSET = 536;
  PSR9_OFFSET = 544;
  PSR10_OFFSET = 552;
  PSR11_OFFSET = 560;
  PSR12_OFFSET = 568;
  PSR13_OFFSET = 576;
  PSR14_OFFSET = 584;
  PSR15_OFFSET = 592;
  PSR16_OFFSET = 600;
  PSR17_OFFSET = 608;
  PSR18_OFFSET = 616;
  PSR19_OFFSET = 624;
  PSR20_OFFSET = 632;
  PSR21_OFFSET = 640;
  PSR22_OFFSET = 648;
  PSR23_OFFSET = 656;
  PSR24_OFFSET = 664;
  PSR25_OFFSET = 672;
  PSR26_OFFSET = 680;
  PSR27_OFFSET = 688;
  PSR28_OFFSET = 696;
  PSR29_OFFSET = 704;
  PSR30_OFFSET = 712;
  PSR31_OFFSET = 720;
  (*
   * maintain the EABI requested 8 bytes aligment
   * As SVR4 ABI requires 16, make it 16 (as some
   * exception may need more registers to be processed...)
   *)

  EXCEPTION_FRAME_END = 728;
  IBAT0U = 528;
  IBAT0L = 529;
  IBAT1U = 530;
  IBAT1L = 531;
  IBAT2U = 532;
  IBAT2L = 533;
  IBAT3U = 534;
  IBAT3L = 535;
  IBAT4U = 560;
  IBAT4L = 561;
  IBAT5U = 562;
  IBAT5L = 563;
  IBAT6U = 564;
  IBAT6L = 565;
  IBAT7U = 566;
  IBAT7L = 567;
  DBAT0U = 536;
  DBAT0L = 537;
  DBAT1U = 538;
  DBAT1L = 539;
  DBAT2U = 540;
  DBAT2L = 541;
  DBAT3U = 542;
  DBAT3L = 543;
  DBAT4U = 568;
  DBAT4L = 569;
  DBAT5U = 570;
  DBAT5L = 571;
  DBAT6U = 572;
  DBAT6L = 573;
  DBAT7U = 574;
  DBAT7L = 575;
  HID0 = 1008;
  HID1 = 1009;
  HID2 = 920;
  HID4 = 1011;
  GQR0 = 912;
  GQR1 = 913;
  GQR2 = 914;
  GQR3 = 915;
  GQR4 = 916;
  GQR5 = 917;
  GQR6 = 918;
  GQR7 = 919;
  L2CR = 1017;
  WPAR = 921;
  DMAU = 922;
  DMAL = 923;
  MSR_RI = $00000002;
  MSR_DR = $00000010;
  MSR_IR = $00000020;
  MSR_IP = $00000040;
  MSR_SE = $00000400;
  MSR_ME = $00001000;
  MSR_FP = $00002000;
  MSR_POW = $00004000;
  MSR_EE = $00008000;
  PPC_ALIGNMENT = 8;
  PPC_CACHE_ALIGNMENT = 32;
{$ENDIF OGC_INTERFACE}