XTENSA_abs:         "Absolute value"
XTENSA_add:         "Add two registers"
XTENSA_addi:        "Add signed constant to register"
XTENSA_addmi:       "Add a register and a shifted 8-bit immediate"
XTENSA_addx2:       "Add register to register shifted by 1"
XTENSA_addx4:       "Add register to register shifted by 2"
XTENSA_addx8:       "Add register to register shifted by 3"
XTENSA_and:         "Bitwise logical AND"
XTENSA_ball:        "Branch if all of masked bits set"
XTENSA_bany:        "Branch if any of masked bits set"
XTENSA_bbc:         "Branch if bit clear"
XTENSA_bbs:         "Branch if bit set"
XTENSA_bbci:        "Branch if bit clear immediate"
XTENSA_bbsi:        "Branch if bit set immediate"
XTENSA_beq:         "Branch if equal"
XTENSA_beqi:        "Branch if equal immediate"
XTENSA_beqz:        "Branch if equal to zero"
XTENSA_bge:         "Branch if greater than or equal"
XTENSA_bgei:        "Branch if one register is greater than or equal to an encoded constant"
XTENSA_bgeu:        "Branch if greater than or equal unsigned"
XTENSA_bgeui:       "Branch if greater than or equal unsigned immediate"
XTENSA_bgez:        "Branch if greater than or equal to zero"
XTENSA_blt:         "Branch if less than"
XTENSA_blti:        "Branch if less than immediate"
XTENSA_bltu:        "Branch if less than Unsigned"
XTENSA_bltui:       "Branch if less than unsigned immediate"
XTENSA_bltz:        "Branch if less than zero"
XTENSA_bnall:       "Branch if not all of masked bits set"
XTENSA_bnone:       "Branch if none of masked bits set (All Clear)"
XTENSA_bne:         "Branch if not equal"
XTENSA_bnei:        "Branch if not equal immediate"
XTENSA_bnez:        "Branch if not equal to zero"
XTENSA_break:       "Breakpoint"
XTENSA_call0:       "Call subroutine, PC-relative"
XTENSA_call4:       "Call subroutine, PC-relative, rotate window by 4"
XTENSA_call8:       "Call subroutine, PC-relative, rotate window by 8"
XTENSA_call12:      "Call subroutine, PC-relative, rotate window by 12"
XTENSA_callx0:      "Call subroutine register specified location"
XTENSA_callx4:      "Call Register, Rotate Window by 4"
XTENSA_callx8:      "Call Register, Rotate Window by 8"
XTENSA_callx12:     "Call Register, Rotate Window by 12"
XTENSA_dsync:       "Load/store synchronize"
XTENSA_entry:       "Subroutine entry"
XTENSA_esync:       "Register value synchronize"
XTENSA_excw:        "Exception Wait"
XTENSA_extui:       "Extract field specified by immediates from a register"
XTENSA_extw:        "Wait for any possible external ordering requirement"
XTENSA_isync:       "Instruction fetch synchronize"
XTENSA_j:           "Jump to PC plus offset"
XTENSA_jx:          "Jump to register specified location"
XTENSA_loop:        "Loop"
XTENSA_loopgtz:     "Loop if Greater Than Zero"
XTENSA_loopnez:     "Loop if Not-Equal Zero"
XTENSA_lsi:         "Load single-precision immediate"
XTENSA_lsx:         "Load single-precision indexed"
XTENSA_l8ui:        "Load zero extended byte"
XTENSA_l16si:       "16-bit signed load (8-bit shifted offset)"
XTENSA_l16ui:       "16-bit unsigned load (8-bit shifted offset)"
XTENSA_l32i:        "32-bit load (8-bit shifted offset)"
XTENSA_l32r:        "32-bit load PC-relative (16-bit negative word offset)"
XTENSA_max:         "Maximum Value Signed"
XTENSA_maxu:        "Maximum Value Unsigned"
XTENSA_memw:        "Wait for any possible memory ordering requirement"
XTENSA_min:         "Minimum Value Signed"
XTENSA_minu:        "Minimum Value Unsigned"
XTENSA_mov:         "Move a 32-bit register to a register"
XTENSA_moveqz:      "Conditional move if zero"
XTENSA_movgez:      "Conditional move if greater than or equal to zero"
XTENSA_movi:        "Move a 12-bit immediate to a register"
XTENSA_movltz:      "Conditional move if less than zero"
XTENSA_movnez:      "Conditional move if non-zero"
XTENSA_mul16s:      "Signed 16-bit multiplication"
XTENSA_mul16u:      "Unsigned 16-bit multiplication"
XTENSA_mull:        "Multiply low"
XTENSA_neg:         "Negate"
XTENSA_nsa:         "Normalization shift amount signed"
XTENSA_nsau:        "Normalization shift amount unsigned"
XTENSA_nop:         "No operation"
XTENSA_or:          "Bitwise logical OR"
XTENSA_ret:         "Return"
XTENSA_retw:        "Windowed Return"
XTENSA_rfe:         "Returns from the KernelExceptionVector exception"
XTENSA_rfi:         "Return from high-priority interrupt"
XTENSA_rsil:        "Read and set interrupt level"
XTENSA_rsr:         "Read Special Register"
XTENSA_rsync:       "Wait for dispatch related changes to resolve"
XTENSA_s8i:         "8-bit store (8-bit offset)"
XTENSA_s16i:        "16-bit store (8-bit shifted offset)"
XTENSA_s32i:        "Store 32-bit quantity"
XTENSA_s32ri:       "Store 32-bit release"
XTENSA_sext:        "Sign Extend"
XTENSA_sll:         "Shift left logical"
XTENSA_slli:        "Shift left logical by SAR/immediate"
XTENSA_sra:         "Shift right arithmetic"
XTENSA_srai:        "Shift right arithmetic immediate by 0..31 bit positions"
XTENSA_src:         "Shift right combined"
XTENSA_srl:         "Shift right logical"
XTENSA_srli:        "Shift right logical immediate by 0..15 bit positions"
XTENSA_ssa8b:       "Set shift amount register (SAR) for big-endian byte align"
XTENSA_ssa8l:       "Set shift amount register (SAR) for little-endian byte align"
XTENSA_ssai:        "Set shift amount register (SAR) immediate"
XTENSA_ssl:         "Set shift amount register (SAR) for shift left logica"
XTENSA_ssr:         "Set shift amount register (SAR) for shift right logical"
XTENSA_sub:         "Subtract two registers"
XTENSA_subx2:       "Subtract register from register shifted by 1"
XTENSA_subx4:       "Subtract register from register shifted by 2"
XTENSA_subx8:       "Subtract register from register shifted by 3"
XTENSA_waiti:       "Wait for interrupt"
XTENSA_wdtlb:       "Write data TLB"
XTENSA_witlb:       "Write instruction TLB"
XTENSA_wsr:         "Write Special Register"
XTENSA_xor:         "Bitwise logical exclusive OR"
XTENSA_xsr:         "Exchange Special Register"

XTENSA_ill:         "Illegal instruction executed"

// macro
XTENSA_andi:        "Bitwise logical AND with immediate"
XTENSA_ori:         "Bitwise logical OR with immediate"
//XTENSA_bbci_l:      "Branch if Bit Clear Immediate LE"
//XTENSA_bbsi_l:      "Branch if Bit Set Immediate LE"
//XTENSA_j_l:         "Unconditional Jump Long"
//XTENSA_mov:         "Move                                   - Macro for \"or\""
//XTENSA_moveqz_d:    "Move Double if Equal to Zero           - Macro for \"moveqz.s\""
//XTENSA_movf_d:      "Move Double if False                   - Macro for \"movf.s\""
//XTENSA_movgez_d:    "Move Double if Greater Than or Equal to Zero - Macro for \"movgez.s\""
//XTENSA_movltz_d:    "Move Double if Less Than Zero          - Macro for \"movltz.s\""
//XTENSA_movnez_d:    "Move Double if Not Equal to Zero       - Macro for \"movnez.s\""
//XTENSA_movt_d:      "Move Double if True                    - Macro for \"movt.s\""

  // other
//XTENSA_const16:     "CONST16-Shift In 16-bit Constant"
XTENSA_rur:         "Read User Register"
XTENSA_wur:         "Write User Register"

  // core
XTENSA_fsync:       "Fetch Synchronize"
XTENSA_rer:         "Read External Register"
XTENSA_s32nb:       "Store 32-bit Non-Buffered"
XTENSA_salt:        "Set AR if Less Than"
XTENSA_saltu:       "Set AR if Less Than Unsigned"
XTENSA_wer:         "Write External Register"

  // block prefetch
XTENSA_dhi_b:       "Block Data Cache Hit Invalidate"
XTENSA_dhwb_b:      "Block Data Cache Hit Writeback"
XTENSA_dhwbi_b:     "Block Data Cache Hit Writeback Inv"
XTENSA_dpfm_b:      "Block Data Cache Prefetch and Modify"
XTENSA_dpfm_bf:     "Block Data Cache Prefetch/Modify First"
XTENSA_dpfr_b:      "Block Data Cache Prefetch for Read"
XTENSA_dpfr_bf:     "Block Data Cache Prefetch for Read First"
XTENSA_dpfw_b:      "Block Data Cache Prefetch for Write"
XTENSA_dpfw_bf:     "Block Data Cache Prefetch for Write First"

  // boolean
XTENSA_all4:        "All 4 Booleans True"
XTENSA_all8:        "All 8 Booleans True"
XTENSA_andb:        "Boolean And"
XTENSA_andbc:       "Boolean And with Complement"
XTENSA_any4:        "Any 4 Booleans True"
XTENSA_any8:        "Any 8 Booleans True"
XTENSA_bf:          "Branch if False"
XTENSA_bt:          "Branch if True"
XTENSA_movf:        "Move if False"
XTENSA_movt:        "Move if True"
XTENSA_orb:         "Boolean Or"
XTENSA_orbc:        "Boolean Or with Complement"
XTENSA_xorb:        "Boolean Exclusive Or"

  // conditional
XTENSA_s32c1i:      "Store 32-bit Compare Conditional"

  // data cache
XTENSA_dci:         "Data Cache Coherent Hit Invalidate"
XTENSA_dcwb:        "Data Cache Coherent Hit Writeback"
XTENSA_dcwbi:       "Data Cache Coherent Hit WB Invalidate"
XTENSA_dhi:         "Data Cache Hit Invalidate"
XTENSA_dhu:         "Data Cache Hit Unlock"
XTENSA_dhwb:        "Data Cache Hit Writeback"
XTENSA_dhwbi:       "Data Cache Hit Writeback Invalidate"
XTENSA_dii:         "Data Cache Index Invalidate"
XTENSA_diu:         "Data Cache Index Unlock"
XTENSA_diwb:        "Data Cache Index Write Back"
XTENSA_diwbi:       "Data Cache Index Write Back Invalidate"
XTENSA_diwbui_p:    "Data Cache Empty"
XTENSA_dpfl:        "Data Cache Prefetch and Lock"
XTENSA_dpfr:        "Data Cache Prefetch for Read"
XTENSA_dpfro:       "Data Cache Prefetch for Read Once"
XTENSA_dpfw:        "Data Cache Prefetch for Write"
XTENSA_dpfwo:       "Data Cache Prefetch for Write Once"
XTENSA_ldct:        "Load Data Cache Tag"
XTENSA_ldcw:        "Load Data Cache Word"
XTENSA_sdct:        "Store Data Cache Tag"
XTENSA_sdcw:        "Store Data Cache Word"

  // debug
XTENSA_lddr32_p:    "Load to DDR Register"
XTENSA_rfdd:        "Return from Debug and Dispatch"
XTENSA_rfdo:        "Return from Debug Operation"
XTENSA_sddr32_p:    "Store from DDR Register"

  // deposit bits option
XTENSA_depbits:     "Deposit Bits"

  // exception
XTENSA_rfde:        "Return from Double Exception"
XTENSA_rfue:        "Return from User-Mode Exception"
XTENSA_syscall:     "System Call"

  // exclusive
XTENSA_clrex:       "Clear Exclusive"
XTENSA_getex:       "Get Exclusive Result"
XTENSA_l32ex:       "Load 32-bit Exclusive"
XTENSA_s32ex:       "Store 32-bit Exclusive"

  // floating point
XTENSA_abs_d:       "Absolute Value Double"
XTENSA_abs_s:       "Absolute Value Single"
XTENSA_add_d:       "Add Double"
XTENSA_add_s:       "Add Single"
XTENSA_addexp_d:    "Add Exponent Double"
XTENSA_addexp_s:    "Add Exponent Single"
XTENSA_addexpm_d:   "Add Exponent from Mantissa Double"
XTENSA_addexpm_s:   "Add Exponent from Mantissa Single"
XTENSA_ceil_d:      "Ceiling Double to Fixed"
XTENSA_ceil_s:      "Ceiling Single to Fixed"
XTENSA_const_d:     "Constant Double"
XTENSA_const_s:     "Constant Single"
XTENSA_cvtd_s:      "Convert Single to Double"
XTENSA_cvts_d:      "Convert Double to Single"
XTENSA_div0_d:      "Divide Begin Double"
XTENSA_div0_s:      "Divide Begin Single"
XTENSA_divn_d:      "Divide Final Double"
XTENSA_divn_s:      "Divide Final Single"
XTENSA_float_d:     "Convert Fixed to Double"
XTENSA_float_s:     "Convert Fixed to Single"
XTENSA_floor_d:     "Floor Double to Fixed"
XTENSA_floor_s:     "Floor Single to Fixed"
XTENSA_ldi:         "Load Double Immediate"
XTENSA_ldip:        "Load Double Immediate Post-Increment"
XTENSA_ldx:         "Load Double Indexed"
XTENSA_ldxp:        "Load Double Indexed Post-Increment"
XTENSA_lsip:        "Load Single Immediate Post-Increment - newer  version of lsiu"
XTENSA_lsiu:        "Load Single Immediate with Update - fp2000 version of lsip"
XTENSA_lsxp:        "Load Single Indexed Post-Increment - newer  version of lsxu"
XTENSA_lsxu:        "Load Single Indexed with Update - fp2000 version of lsxp"
XTENSA_madd_d:      "Multiply and Add Double"
XTENSA_madd_s:      "Multiply and Add Single"
XTENSA_maddn_d:     "Multiply and Add Double Round Nearest"
XTENSA_maddn_s:     "Multiply and Add Single Round Nearest"
XTENSA_mkdadj_d:    "Make Divide Adjust Double"
XTENSA_mkdadj_s:    "Make Divide Adjust Single"
XTENSA_mksadj_d:    "Make Square Root Adjust Double"
XTENSA_mksadj_s:    "Make Square Root Adjust Single"
XTENSA_mov_d:       "Move Double"
XTENSA_mov_s:       "Move Single"
XTENSA_moveqz_s:    "Move Single if Equal to Zero"
XTENSA_movf_s:      "Move Single if False"
XTENSA_movgez_s:    "Move Single if Greater Than or Equal to Zero"
XTENSA_movltz_s:    "Move Single if Less Than Zero"
XTENSA_movnez_s:    "Move Single if Not Equal to Zero"
XTENSA_movt_s:      "Move Single if True"
XTENSA_msub_d:      "Multiply and Subtract Double"
XTENSA_msub_s:      "Multiply and Subtract Single"
XTENSA_mul_d:       "Multiply Double"
XTENSA_mul_s:       "Multiply Single"
XTENSA_neg_d:       "Negate Double"
XTENSA_neg_s:       "Negate Single"
XTENSA_nexp01_d:    "Narrow Exponent Range Double"
XTENSA_nexp01_s:    "Narrow Exponent Range Single"
XTENSA_oeq_d:       "Compare Double Equal"
XTENSA_oeq_s:       "Compare Single Equal"
XTENSA_ole_d:       "Compare Double Ordered and Less Than or Equal"
XTENSA_ole_s:       "Compare Single Ordered and Less Than or Equal"
XTENSA_olt_d:       "Compare Double Ordered and Less Than"
XTENSA_olt_s:       "Compare Single Ordered and Less Than"
XTENSA_recip0_d:    "Reciprocal Begin Double"
XTENSA_recip0_s:    "Reciprocal Begin Single"
XTENSA_rfr:         "Move FR to AR"
XTENSA_rfrd:        "Move FR to AR Upper"
XTENSA_round_d:     "Round Double to Fixed"
XTENSA_round_s:     "Round Single to Fixed"
XTENSA_rsqrt0_d:    "Reciprocal Sqrt Begin Double"
XTENSA_rsqrt0_s:    "Reciprocal Sqrt Begin Single"
XTENSA_sdi:         "Store Double Immediate"
XTENSA_sdip:        "Store Double Immediate Post-Increment"
XTENSA_sdx:         "Store Double Indexed"
XTENSA_sdxp:        "Store Double Indexed Post-Increment"
XTENSA_sqrt0_d:     "Sqrt Begin Double"
XTENSA_sqrt0_s:     "Sqrt Begin Single"
XTENSA_ssi:         "Store Single Immediate"
XTENSA_ssip:        "Store Single Immediate Post-Increment - newer  version of ssiu"
XTENSA_ssiu:        "Store Single Immediate with Update - fp2000 version of ssip"
XTENSA_ssx:         "Store Single Indexed"
XTENSA_ssxp:        "Store Single Indexed Post-Increment - newer  version of ssxu"
XTENSA_ssxu:        "Store Single Indexed with Update - fp2000 version of ssxp"
XTENSA_sub_d:       "Subtract Double"
XTENSA_sub_s:       "Subtract Single"
XTENSA_trunc_d:     "Truncate Double to Fixed"
XTENSA_trunc_s:     "Truncate Single to Fixed"
XTENSA_ueq_d:       "Compare Double Unordered or Equal"
XTENSA_ueq_s:       "Compare Single Unordered or Equal"
XTENSA_ufloat_d:    "Convert Unsigned Fixed to Double"
XTENSA_ufloat_s:    "Convert Unsigned Fixed to Single"
XTENSA_ule_d:       "Compare Double Unord or Less Than or Equal"
XTENSA_ule_s:       "Compare Single Unord or Less Than or Equal"
XTENSA_ult_d:       "Compare Double Unordered or Less Than"
XTENSA_ult_s:       "Compare Single Unordered or Less Than"
XTENSA_un_d:        "Compare Double Unordered"
XTENSA_un_s:        "Compare Single Unordered"
XTENSA_utrunc_d:    "Truncate Double to Fixed Unsigned"
XTENSA_utrunc_s:    "Truncate Single to Fixed Unsigned"
XTENSA_wfr:         "Move AR to FR"
XTENSA_wfrd:        "Move AR to FR Double"

  // instruction cache
XTENSA_ihi:         "Instruction Cache Hit Invalidate"
XTENSA_ihu:         "Instruction Cache Hit Unlock"
XTENSA_iii:         "Instruction Cache Index Invalidate"
XTENSA_iiu:         "Instruction Cache Index Unlock"
XTENSA_ipf:         "Instruction Cache Prefetch"
XTENSA_ipfl:        "Instruction Cache Prefetch and Lock"
XTENSA_lict:        "Load Instruction Cache Tag"
XTENSA_licw:        "Load Instruction Cache Word"
XTENSA_sict:        "Store Instruction Cache Tag"
XTENSA_sicw:        "Store Instruction Cache Word"

  // int32
XTENSA_mulsh:       "Multiply Signed High"
XTENSA_muluh:       "Multiply Unsigned High"
XTENSA_quos:        "Quotient Signed"
XTENSA_quou:        "Quotient Unsigned"
XTENSA_rems:        "Remainder Signed"
XTENSA_remu:        "Remainder Unsigned"

  // mac16
XTENSA_lddec:       "Load with Autodecrement"
XTENSA_ldinc:       "Load with Autoincrement"
XTENSA_mul_aa:      "Signed Multiply"
XTENSA_mul_ad:      "Signed Multiply"
XTENSA_mul_da:      "Signed Multiply"
XTENSA_mul_dd:      "Signed Multiply"
XTENSA_mula_aa:     "Signed Multiply/Accumulate"
XTENSA_mula_ad:     "Signed Multiply/Accumulate"
XTENSA_mula_da:     "Signed Multiply/Accumulate"
XTENSA_mula_da_lddec:"Signed Multiply/Accumulate, Ld/Autodec"
XTENSA_mula_da_ldinc:"Signed Multiply/Accumulate, Ld/Autoinc"
XTENSA_mula_dd:      "Signed Multiply/Accumulate"
XTENSA_mula_dd_lddec:"Signed Multiply/Accumulate, Ld/Autodec"
XTENSA_mula_dd_ldinc:"Signed Multiply/Accumulate, Ld/Autoinc"
XTENSA_muls_aa:     "Signed Multiply/Subtract"
XTENSA_muls_ad:     "Signed Multiply/Subtract"
XTENSA_muls_da:     "Signed Multiply/Subtract"
XTENSA_muls_dd:     "Signed Multiply/Subtract"
XTENSA_umul_aa:     "Unsigned Multiply"

  // memory ecc
XTENSA_rfme:        "Return from Memory Error"

  // misc
XTENSA_clamps:      "Signed Clamp"

  // multiprocessor
XTENSA_l32ai:       "Load 32-bit Aquire"

  // region
XTENSA_idtlb:       "Invalidate Data TLB Entry"
XTENSA_iitlb:       "Invalidate Instruction TLB Entry"
XTENSA_pdtlb:       "Probe Data TLB"
XTENSA_pitlb:       "Probe Intruction TLB"
XTENSA_pptlb:       "Probe Protection TLB"
XTENSA_rdtlb0:      "Read Data TLB Entry Virtual"
XTENSA_rdtlb1:      "Read Data TLB Entry Translation"
XTENSA_ritlb0:      "Read Instruction TLB Entry Virtual"
XTENSA_ritlb1:      "Read Instruction TLB Entry Translation"
XTENSA_rptlb0:      "Read Protection TLB Entry Address"
XTENSA_rptlb1:      "Read Protection TLB Entry Info"
XTENSA_wptlb:       "Write Protection TLB Entry"

  // sim
XTENSA_simcall:     "Simulator Call"

  // windowed
XTENSA_l32e:        "Load 32-bit for Window Exceptions"
XTENSA_movsp:       "Move to Stack Pointer"
XTENSA_rfwo:        "Return from Window Overflow"
XTENSA_rfwu:        "Return from Window Underflow"
XTENSA_rotw:        "Rotate Window"
XTENSA_s32e:        "Store 32-bit for Window Exceptions"

  // reserved - these are undocumented in the main docs
  // but exist in some GNU binutils implementations.
  // they might be custom to some specific implementation of xtensa
  // but as long as they dont conflict with anything else we can include support for them
XTENSA_clrb_expstate: "?"
XTENSA_hwwdtlba:      "?"
XTENSA_hwwitlba:      "?"
XTENSA_ldpte:         "?"
XTENSA_read_impwire:  "?"
XTENSA_setb_expstate: "?"
XTENSA_wrmsk_expstate:"?"

  // These seem to be part of the AE (Audio Extension?) instruction set.
  // Looking at output of "AE" objdump bruteforce there are about 120 AE instructions.
  // I didn't find public docs on the AE instructions so won't try to guess them all.
XTENSA_ae2_rur:       "Read User Register (AE2 version)"
XTENSA_ae2_wur:       "Write User Register (AE2 version)"
XTENSA_ae_rur:        "Read User Register (AE version)"
XTENSA_ae_wur:        "Write User Register (AE version)"

  // These seem to be part of the DSP instruction set.
  // Looking at output of DSP objdump bruteforce there are about 180 DSP instructions.
  // I didn't find public docs on the DSP instructions so won't try to guess them all.
//XTENSA_lac_il:        "?"
//XTENSA_sac2x32:       "?"
//XTENSA_sac32_r:       "?"