RISCV_null:    "Unknown Operation"
RISCV_unk:     "Unsupported instruction"
  // Set 32 bits
  // I(nteger) extension
RISCV_lui:     "Load Upper Immediate"
RISCV_auipc:   "Add Upper Immediate to pc"
RISCV_jal:     "Jump and link"
RISCV_jalr:    "Jump register rs1 & write pc +2 in rs1"
RISCV_beq:     "Branch on equal"
RISCV_bne:     "Branch not equal"
RISCV_blt:     "Branch less than"
RISCV_bge:     "Branch greater or equal"
RISCV_bltu:    "Branch less than unsigned"
RISCV_bgeu:    "Branch greater or equal unsigned"
RISCV_lb:      "Load byte"
RISCV_lh:      "Load halfword"
RISCV_lw:      "Load word"
RISCV_lbu:     "Load byte unsigned"
RISCV_lhu:     "Load halfword unsigned"
RISCV_sb:      "Store byte"
RISCV_sh:      "Store halfword"
RISCV_sw:      "Store word"
RISCV_addi:    "Add immediate"
RISCV_slti:    "Set less than immediate"
RISCV_sltiu:   "Set less than immediate unsigned"
RISCV_xori:    "Xor immediate"
RISCV_ori:     "Or immediate"
RISCV_andi:    "And Immediate"
RISCV_slli:    "Shift left logical immediate"
RISCV_srli:    "Shift right logical immediate"
RISCV_srai:    "Shift right arithmetical immediate"
RISCV_add:     "Add integer"
RISCV_sub:     "Substract integer"
RISCV_sll:     "Shift left logical"
RISCV_slt:     "Set Less Than"
RISCV_sltu:    "Set Less Than unsigned"
RISCV_xor:     "eXclusive Or"
RISCV_srl:     "Shift right logical"
RISCV_sra:     "Shift right arithmetical"
RISCV_or:      "Or"
RISCV_and:     "And"
RISCV_fence:   "Fence"
RISCV_ecall:   "Ecall"
RISCV_ebreak:  "Ebreak"
RISCV_uret:    "User lvl return"
RISCV_sret:    "Supervisor lvl return"
RISCV_mret:    "Machine lvl return"
RISCV_wfi:     "Wait for interrupt"
RISCV_sfence:  "Supervisor fence"
RISCV_hfenceb: "Hypervisor fence b"
RISCV_hfenceg: "Hypervisor fence g"
  // Set 64 bits
  // Integer extension
RISCV_lwu:     "Load word unsigned"
RISCV_ld:      "Load double"
RISCV_sd:      "Store double"
RISCV_addiw:   "Add immediate word"
RISCV_slliw:   "Shift left logical immediate word"
RISCV_srliw:   "Shift right logical immediate word"
RISCV_sraiw:   "Shift right arithmetical immediate word"
RISCV_addw:    "Add integer word"
RISCV_subw:    "Substract integer word"
RISCV_sllw:    "Shift left logical word"
RISCV_sltw:    "Set Less Than word"
RISCV_srlw:    "Shift right logical word"
RISCV_sraw:    "Shift right arithmetical word"
  // Zifencei Standard extension
RISCV_fencei:  "Fence immediate"
  // Zicsr Standard extension
RISCV_csrrw:   "Atomic Read Write CSR"
RISCV_csrrs:   "Atomic Read and Set bit CSR"
RISCV_csrrc:   "Atomic Read and clear bit CSR"
RISCV_csrrwi:  "Atomic Read Write CSR immediate"
RISCV_csrrsi:  "Atomic Read and Set bit CSR immediate"
RISCV_csrrci:  "Atomic Read and clear bit CSR immediate"
  // M(ultiplication and divison for integer) extension
RISCV_mul:     "Multiplication"
RISCV_mulh:    "Multiplication half (signed signed)"
RISCV_mulhsu:  "Multiplication half (signed unsigned)"
RISCV_mulhu:   "Multiplication half (unsigned unsigned)"
RISCV_div:     "Division"
RISCV_divu:    "Division unsigned"
RISCV_rem:     "Remainder of div"
RISCV_remu:    "Remainder of div unsigned"
  // 64b M(ultiplication and divison for integer) extension
RISCV_mulw:    "Multiplication word"
RISCV_divw:    "Division word"
RISCV_divuw:   "Division unsigned word"
RISCV_remw:    "Remainder of div word"
RISCV_remuw:   "Remainder of div unsigned word"
  // A(tomic) operation standtard extension
RISCV_lr:      "Load reserved"
RISCV_sc:      "Store conditional"
RISCV_amoswap: "Atomic memory operation swap"
RISCV_amoadd:  "Atomic memory operation add"
RISCV_amoxor:  "Atomic memory operation xop"
RISCV_amoand:  "Atomic memory operation and"
RISCV_amoor:   "Atomic memory operation or"
RISCV_amomin:  "Atomic memory operation min"
RISCV_amomax:  "Atomic memory operation max"
RISCV_amominu: "Atomic memory operation min unsigned"
RISCV_amomaxu: "Atomic memory operation max unsigned"
  // Zacas extension
RISCV_amocas:  "Atomic compare and swap"
  // simple precision F(loat) instruction extension
RISCV_flw:     "Load word (32b)"
RISCV_fsw:     "Store word (32b)"
RISCV_fmadd:   "Multiply then add"
RISCV_fmsub:   "Multiply then substract"
RISCV_fnmsub:  "Multiply then negate then substract"
RISCV_fnmadd:  "Multiply then negate then add"
RISCV_fadd:    "Float addition"
RISCV_fsub:    "Float substraction"
RISCV_fmul:    "Float multiplication"
RISCV_fdiv:    "Float division"
RISCV_fsqrt:   "Float square root"
RISCV_fsgnj:   "Float sign injection"
RISCV_fsgnjn:  "Float sign injection negate"
RISCV_fsgnjx:  "Float sign injection xor between operands"
RISCV_fmin:    "Float minimum"
RISCV_fmax:    "Float maximum"
RISCV_fcvtf2f: "F2F conversion"
RISCV_fcvtf2i: "F2I conversion"
RISCV_fcvti2f: "I2F conversion"
RISCV_fmv:     "Mv"
RISCV_feq:     "Float equal"
RISCV_flt:     "Float less than"
RISCV_fle:     "Float less or equal than"
RISCV_fclass:  "Classify the float"
  // 64b simple precision F(loat) instruction extension
  // D(ouble) precision float instruction extension
RISCV_fld:     "Load double (64b)"
RISCV_fsd:     "Store double (64b)"
  // 64b D(ouble) precision float instruction
  // Q(uadruple) precision float instruction extension
RISCV_flq:     "Load quadruple (128b)"
RISCV_fsq:     "Store quadruple (128b)"
  // 64b Q(uadruple) precision float extension
  // pseudo insn
RISCV_nop:        "No operation"
RISCV_li:         "Load Immediate"
RISCV_mv:         "Copy register"
RISCV_not:        "One's complement"
RISCV_neg:        "Two's complement"
RISCV_negw:       "Two's complement word"
RISCV_sext:       "Sign extend word"
RISCV_seqz:       "Set if = zero"
RISCV_snez:       "Set if != zero"
RISCV_sltz:       "Set if < zero"
RISCV_sgtz:       "Set if > zero"
RISCV_fabs:       "Float absolute value"
RISCV_fneg:       "Float negate"
RISCV_beqz:       "Branch == 0"
RISCV_bnez:       "Branch != 0"
RISCV_blez:       "Branch <= 0"
RISCV_bgez:       "Branch >= 0"
RISCV_bltz:       "Branch < 0"
RISCV_bgtz:       "Branch > 0"
RISCV_j:          "Jump"
RISCV_jr:         "Jump register"
RISCV_ret:        "Return"
RISCV_rdinstret:  "Read instructions-retired counter"
RISCV_rdcycle:    "Read cycle counter"
RISCV_rdtime:     "Read real-time clock"
RISCV_rdinstreth: "Read instructions-retired counter Upper 32 bits"
RISCV_rdcycleh:   "Read cycle counter Upper 32 bits"
RISCV_rdtimeh:    "Read real-time clock Upper 32 bits"
RISCV_csrr:       "Read CSR"
RISCV_csrw:       "Write CSR"
RISCV_csrs:       "Set bit CSR"
RISCV_csrc:       "Clear bit"
RISCV_csrwi:      "Write CSR immediate"
RISCV_csrsi:      "Set bit CSR immediate"
RISCV_csrci:      "Clear bit CSR immediate"
RISCV_frcsr:      "Read FP control/status register"
RISCV_fscsr:      "Write/Swap FP control/status register"
RISCV_frrm:       "Read FP rounding mode"
RISCV_fsrm:       "Write/Swap FP rounding mode"
RISCV_frflags:    "Read FP exception flags"
RISCV_fsflags:    "Write/Swap FP exception flags"
  // Macro
RISCV_la:         "Load Address macro"
RISCV_call:       "Call macro"
RISCV_tail:       "Tail macro"
RISCV_jump:       "Jump macro"
  // Vector extension
RISCV_vsetvl:     "Set vector length rd = new vl, rs1 = AVL, rs2 = new vtype value"
RISCV_vsetvli:    "Set vector length vtype immediate"
RISCV_vsetivli:   "Set vector length avl immediate and vtype immediate"
RISCV_vl:         "Vector load"
RISCV_vs:         "Vector store"
  // Vector extention op I(nteger)
RISCV_vadd:         "Vector add"
RISCV_vsub:         "Vector sub"
RISCV_vrsub:        "Vector reverse substract"
RISCV_vminu:        "Vector unsigned minimum"
RISCV_vmin:         "Vector signed minimum"
RISCV_vmaxu:        "Vector unsigned maximum"
RISCV_vmax:         "Vector signed maximum"
RISCV_vand:         "Vector bitwise logical and"
RISCV_vor:          "Vector bitwise logical or"
RISCV_vxor:         "Vector bitwise logical xor"
RISCV_vrgather:     "Vector register gather"
RISCV_vslideup:     "Vector slide up"
RISCV_vrgatherei16: "Vector register gather"
RISCV_vslidedown:   "Vector slide down"
RISCV_vadc:         "Vector produce sum with carry"
RISCV_vmadc:        "Vector produce carry out in mask register format"
RISCV_vsbc:         "Vector produce difference with borrow"
RISCV_vmsbc:        "Vector produce borrow out in mask register format"
RISCV_vmerge:       "Vector integer merge"
RISCV_vmv:          "Vector integer move"
RISCV_vmseq:        "Vector set if equal"
RISCV_vmsne:        "Vector set if not equal"
RISCV_vmsltu:       "Vector set if less than, unsigned"
RISCV_vmslt:        "Vector set if less than, signed"
RISCV_vmsleu:       "Vector set if less than or equal, unsigned"
RISCV_vmsle:        "Vector set if less than or equal, signed"
RISCV_vmsgtu:       "Vector set if greater than, unsigned"
RISCV_vmsgt:        "Vector set if greater than, signed"
RISCV_vsaddu:       "Vector saturating adds of unsigned integers"
RISCV_vsadd:        "Vector saturating adds of signed integers"
RISCV_vssubu:       "Vector saturating subtract of unsigned integers"
RISCV_vssub:        "Vector saturating subtract of signed integers"
RISCV_vsll:         "Vector bit shift left logical"
RISCV_vsmul:        "Vector signed saturating and rounding fractional multiply"
RISCV_vmvr:         "Vector whole register move <nbr> reg"
RISCV_vsrl:         "Vector bit shift right logical"
RISCV_vsra:         "Vector bit shift right arithmetic"
RISCV_vssrl:        "Vector scaling shift right logical"
RISCV_vssra:        "Vector scaling shift right arithmetic"
RISCV_vnsrl:        "Vector narrowing shift right logical, SEW = (2*SEW) >> SEW"
RISCV_vnsra:        "Vector narrowing shift right arithmetic, SEW = (2*SEW) >> SEW"
RISCV_vnclipu:      "Vector narrowing unsigned clip"
RISCV_vnclip:       "Vector narrowing signed clip"
RISCV_vwredsumu:    "Vector unsigned sum reduction into double-width accumulator"
RISCV_vwredsum:     "Vector signed sum reduction into double-width accumulator"
  // Vector extention op M(ultiplication and divison for integer)
RISCV_vredsum:      "Vector single-width reduction sum"
RISCV_vredand:      "Vector single-width reduction and"
RISCV_vredor:       "Vector single-width reduction or"
RISCV_vredxor:      "Vector single-width reduction xor"
RISCV_vredminu:     "Vector single-width reduction min unsigned"
RISCV_vredmin:      "Vector single-width reduction min"
RISCV_vredmaxu:     "Vector single-width reduction max unsigned"
RISCV_vredmax:      "Vector single-width reduction max"
RISCV_vaaddu:       "Vector averaging adds of unsigned integers"
RISCV_vaadd:        "Vector averaging adds of signed integers"
RISCV_vasubu:       "Vector averaging subtract of unsigned integers"
RISCV_vasub:        "Vector averaging subtract of signed integers"
RISCV_vslide1up:    "Vector integer slide one element up"
RISCV_vslide1down:  "Vector integer slide one element down"
RISCV_vcpop:        "Vector count population in mask"
RISCV_vfirst:       "Vector find-first-set mask bit"
RISCV_vmvi:         "Vector integer scalar move"
RISCV_vzext:        "Vector zero extend"
RISCV_vsext:        "Vector sign extend"
RISCV_vmsbf:        "Vector Vector set-before-first mask bit"
RISCV_vmsof:        "Vector Vector set-only-first mask bit"
RISCV_vmsif:        "Vector Vector set-including-first mask bit"
RISCV_viota:        "Vector Vector iota"
RISCV_vid:          "Vector Vector element index"
RISCV_vcompress:    "Vector compress"
RISCV_vmandn:       "Vector mask-register not(vs2.mask[i] and vs1.mask[i])"
RISCV_vmand:        "Vector mask-register (vs2.mask[i] and vs1.mask[i])"
RISCV_vmor:         "Vector mask-register (vs2.mask[i] or vs1.mask[i])"
RISCV_vmxor:        "Vector mask-register (vs2.mask[i] xor vs1.mask[i])"
RISCV_vmorn:        "Vector mask-register not(vs2.mask[i] or vs1.mask[i])"
RISCV_vmnand:       "Vector mask-register not(vs2.mask[i] and vs1.mask[i])"
RISCV_vmnor:        "Vector mask-register not(vs2.mask[i] or vs1.mask[i])"
RISCV_vmxnor:       "Vector mask-register not(vs2.mask[i] xor vs1.mask[i])"
RISCV_vdivu:        "Vector unsigned divide"
RISCV_vdiv:         "Vector signed divide"
RISCV_vremu:        "Vector unsigned remainder"
RISCV_vrem:         "Vector signed remainder"
RISCV_vmulhu:       "Vector unsigned multiply, returning high bits of product"
RISCV_vmul:         "Vector signed multiply, returning low bits of product"
RISCV_vmulhsu:      "Vector signed-unsigned multiply, returning high bits of product"
RISCV_vmulh:        "Vector signed multiply, returning high bits of product"
RISCV_vmadd:        "Vector integer multiply-add, overwrite multiplicand"
RISCV_vnmsub:       "Vector integer multiply-sub, overwrite multiplicand"
RISCV_vmacc:        "Vector integer multiply-add, overwrite addend"
RISCV_vnmsac:       "Vector integer multiply-sub, overwrite minuend"
RISCV_vwaddu:       "Vector widening unsigned integer add , 2*SEW = SEW +/- SEW"
RISCV_vwadd:        "Vector widening signed integer add , 2*SEW = SEW +/- SEW"
RISCV_vwsubu:       "Vector widening unsigned integer substract , 2*SEW = SEW +/- SEW"
RISCV_vwsub:        "Vector widening signed integer substract , 2*SEW = SEW +/- SEW"
RISCV_vwadduw:      "Vector widening unsigned integer add , 2*SEW = 2*SEW +/- SEW"
RISCV_vwaddw:       "Vector widening signed integer add , 2*SEW = 2*SEW +/- SEW"
RISCV_vwsubuw:      "Vector widening unsigned integer substract , 2*SEW = 2*SEW +/- SEW"
RISCV_vwsubw:       "Vector widening signed integer substract , 2*SEW = 2*SEW +/- SEW"
RISCV_vwmulu:       "Vector widening unsigned-integer multiply"
RISCV_vwmulsu:      "Vector widening signed(vs2)-unsigned integer multiply"
RISCV_vwmul:        "Vector widening signed-integer multiply"
RISCV_vwmaccu:      "Vector widening unsigned-integer multiply-add, overwrite addend"
RISCV_vwmacc:       "Vector widening signed-integer multiply-add, overwrite addend"
RISCV_vwmaccus:     "Vector widening unsigned-signed-integer multiply-add, overwrite addend"
RISCV_vwmaccsu:     "Vector widening signed-unsigned-integer multiply-add, overwrite addend"
  // Vector extention op F(loat)
RISCV_vfadd:        "Vector floating-point add"
RISCV_vfredusum:    "Vector fp simple-width reductions unordered sum"
RISCV_vfsub:        "Vector floating-point subtract"
RISCV_vfredosum:    "Vector fp simple-width reductions ordered sum"
RISCV_vfmin:        "Vector floating-point minimum"
RISCV_vfredmin:     "Vector fp simple-width reductions minimum value"
RISCV_vfmax:        "Vector floating-point maximum"
RISCV_vfredmax:     "Vector fp simple-width reductions maximum value"
RISCV_vfsgnj:       "Vector sign injection"
RISCV_vfsgnjn:      "Vector sign injection negated"
RISCV_vfsgnjx:      "Vector sign injection xor"
RISCV_vfslide1up:   "Vector fp slide one element up"
RISCV_vfslide1down: "Vector fp slide one element down"
RISCV_vfmov:        "Vector floating-point scalar move"
RISCV_vfcvt:        "Vector convert float to integer / integer to float"
RISCV_vfwcvt:       "Vector convert single width float/integer to double-width integer/float"
RISCV_vfncvt:       "Vector convert double-width float/integer to single width float/integer"
RISCV_vfsqrt:       "Vector floating-point square root"
RISCV_vfrsqrt7:     "Vector floating-point reciprocal square-root estimate to 7 bits"
RISCV_vfrec7:       "Vector floating-point reciprocal estimate to 7 bits"
RISCV_vfclass:      "Vector classification of float"
RISCV_vfmerge:      "Vector floating-point merge"
RISCV_vfmv:         "Vector floating-point move"
RISCV_vmfeq:        "Vector fp compare equal"
RISCV_vmfle:        "Vector fp compare less than or equal"
RISCV_vmflt:        "Vector fp compare less than"
RISCV_vmfne:        "Vector fp compare not equal"
RISCV_vmfgt:        "Vector fp compare greater than"
RISCV_vmfge:        "Vector fp compare greater than or equal"
RISCV_vfdiv:        "Vector floating-point divide"
RISCV_vfrdiv:       "Vector floating-point reverse divide"
RISCV_vfmul:        "Vector floating-point multiply"
RISCV_vfrsub:       "Vector floating-point reverse subtract"
RISCV_vfmadd:       "Vector fp multiply-add, overwrites multiplicand"
RISCV_vfnmadd:      "Vector fp negate-(multiply-add), overwrites multiplicand"
RISCV_vfmsub:       "Vector fp multiply-sub, overwrites multiplicand"
RISCV_vfnmsub:      "Vector fp negate-(multiply-sub), overwrites multiplicand"
RISCV_vfmacc:       "Vector fp multiply-accumulate, overwrites addend"
RISCV_vfnmacc:      "Vector fp negate-(multiply-accumulate), overwrites subtrahend"
RISCV_vfmsac:       "Vector fp multiply-subtract-accumulator, overwrites subtrahend"
RISCV_vfnmsac:      "Vector fp negate-(multiply-subtract-accumulator), overwrites minuend"
RISCV_vfwadd:       "Vector widening fp add 2*SEW = SEW +/- SEW"
RISCV_vfwredusum:   "Vector fp widened reduction unordered sum"
RISCV_vfwsub:       "Vector widening fp substract 2*SEW = SEW +/- SEW"
RISCV_vfwredosum:   "Vector fp widened reduction ordered sum"
RISCV_vfwaddw:      "Vector widening fp add 2*SEW = 2*SEW +/- SEW"
RISCV_vfwsubw:      "Vector widening fp substract 2*SEW = 2*SEW +/- SEW"
RISCV_vfwmul:       "Vector widening floating-point multiply"
RISCV_vfwmacc:      "Vector fp widening multiply-accumulate, overwrites addend"
RISCV_vfwnmacc:     "Vector fp widening negate-(multiply-accumulate), overwrites addend"
RISCV_vfwmsac:      "Vector fp widening multiply-subtract-accumulator, overwrites addend"
RISCV_vfwnmsac:     "Vector fp widening negate-(multiply-subtract-accumulator), overwrites addend"
  // Pseudo vector instruction
RISCV_vneg:         "Vector negate"
RISCV_vwcvt:        "Vector double width signed"
RISCV_vwcvtu:       "Vector double width unsigned"
RISCV_vnot:         "Vector not"
RISCV_vncvt:        "Vector half width"
RISCV_vfneg:        "Vector floating point negate"
RISCV_vfabs:        "Vector floating point absolute"
RISCV_vmmv:         "Vector copy mask register"
RISCV_vmclr:        "Vector clear mask register"
RISCV_vmset:        "Vector set mask register"
RISCV_vmnot:        "Vector invert bits"
RISCV_andn:         "And with inverted operand rs2"
RISCV_bclr:         "Single-bit clear (register)"
RISCV_bclri:        "Single-bit clear (immediate)"
RISCV_bext:         "Single-bit extract (register)"
RISCV_bexti:        "Single-bit extract (immediate)"
RISCV_binv:         "Single-bit invert (register)"
RISCV_binvi:        "Single-bit invert (immediate)"
RISCV_bset:         "Single-bit set (register)"
RISCV_bseti:        "Single-bit set (immediate)"
RISCV_clmul:        "Carry-less multiply (low-part)"
RISCV_clmulh:       "Carry-less multiply (high-part)"
RISCV_clmulr:       "Carry-less multiply (reversed)"
RISCV_clz:          "Count leading zero bits"
RISCV_clzw:         "Count leading zero bits in word"
RISCV_cpop:         "Count set bits"
RISCV_cpopw:        "Count set bits in word"
RISCV_ctz:          "Count trailing zeros"
RISCV_ctzw:         "Count trainling zeros ni word"
RISCV_max:          "Maximum signed"
RISCV_maxu:         "Maximum unsigned"
RISCV_min:          "Minimum signed"
RISCV_minu:         "Minimum unsigned"
RISCV_orc:          "Bitwise OR-Combine"
RISCV_orn:          "Or with inverted operand rs2"
RISCV_rev8:         "Byte-reverse register"
RISCV_rol:          "Rotate left (Register)"
RISCV_rolw:         "Rotate Left Word (Register)"
RISCV_ror:          "Rotate right"
RISCV_rori:         "Rotate right immediate"
RISCV_roriw:        "Rotate Right Word by Immediate"
RISCV_rorw:         "Rotate Right Word (Register)"
RISCV_sh1add:       "Shift left by 1 and add"
RISCV_sh2add:       "Shift left by 2 and add"
RISCV_sh3add:       "Shift left by 3 and add"
RISCV_xnor:         "Exclusive nor"
RISCV_zext:         "Zero-extend halfword"
  // H(alf) precision float instruction extension
RISCV_flh:          "Load floating point half-precision (16 bits)"
RISCV_fsh:          "Store floating point half-precision (16 bits)"
  // Hypervisor virtual-machine instructions
RISCV_hl:           "Load hypervisor mode"
RISCV_hs:           "Store hypervisor mode"
  // Svinval Fine-Grained Address-Translation Cache Invalidation
RISCV_sinval:       "invalidates address-translation cache"
RISCV_sfencefg:     "fine grained supervisor fence"
RISCV_hinval:       "invalidates address-translation cache in hypervisor mode"
  // Pause hint
RISCV_pause:        "Pause"
  // Cache management operation
RISCV_cbo:          "cache base operation"
RISCV_prefetch:     "prefetch address hint"
  // Legacy instructions
RISCV_sfencevm:     "Supervisor memory-management fence (spec 1.9.1, 2016)"
  // Cryptography extension
RISCV_aes:          "AES encryption decryption"
RISCV_aes64im:      "inverse MixColumns step of the AES Block Cipher"
RISCV_aes64ks1i:    "KeySchedule operation for the AES Block cipher involving the SBox operation"
RISCV_aes64ks2:     "KeySchedule operation for the AES Block cipher"
RISCV_brev8:        "Reverse the bits in each byte of a source register"
RISCV_pack:         "Pack the low halves of rs1 and rs2 into rd"
RISCV_packh:        "Pack the low bytes of rs1 and rs2 into rd"
RISCV_packw:        "Pack the low bytes of rs1 and rs2 into rd"
RISCV_sha256:       "transformation for SHA2-256 hash function"
RISCV_sha512:       "transformation for SHA2-512 hash function"
RISCV_sm3:          "transformation for SM3 hash function"
RISCV_sm4:          "Acceleration operations for the SM4 block cipher"
RISCV_unzip:        "Place odd and even bits of the source word into upper/lower halves of the destination"
RISCV_xperm4:       "Nibble-wise lookup of indicies into a vector"
RISCV_xperm8:       "Byte-wise lookup of indicies into a vector in registers"
RISCV_zip:          "Place upper/lower halves of the source register into odd/even bits of the destination respectivley"
  // Zwars extension
RISCV_wrsnto:       "Wait on reservation with no timeout"
RISCV_wrssto:       "Wait on reservation with short timeout"
  // T-head extension
RISCV_thdcachecall:    "Clean all D-cache"
RISCV_thdcacheciall:   "Clean & invalidate all D-cache"
RISCV_thdcacheiall:    "Invalidate all D-cache"
RISCV_thdcachecpa:     "Clean D-cache at PA"
RISCV_thdcachecipa:    "Clean and invalidate D-cache at PA"
RISCV_thdcacheipa:     "Invalidate D-cache at PA"
RISCV_thdcachecva:     "Clean D-cache at VA"
RISCV_thdcacheciva:    "Clean and invalidate D-cache at VA"
RISCV_thdcacheiva:     "Invalidate D-cache at VA"
RISCV_thdcachecsw:     "Clean D-cache by set/way"
RISCV_thdcachecisw:    "Clean & invalidate D-cache by set/way"
RISCV_thdcacheisw:     "Invalidate D-cache by set/way"
RISCV_thdcachecpal1:   "Clean L1 D-cache at PA"
RISCV_thdcachecval1:   "Clean L1 D-cache at VA"
RISCV_thicacheiall:    "Invalidate all I-cache"
RISCV_thicacheialls:   "Invalidate all I-cache on all harts"
RISCV_thicacheipa:     "Invalidate I-cache at PA"
RISCV_thicacheiva:     "Invalidate I-cache at VA"
RISCV_thl2cachecall:   "Clean all L2 cache"
RISCV_thl2cacheciall:  "Clean & invalidate all L2 cache"
RISCV_thl2cacheiall:   "Invalidate all L2 cache"
RISCV_thsfencevmas:    "Invalidate TLB (page table cache) on all harts via broadcasting"
RISCV_thsync:          "Ensures that preceding instructions retire earlier and subsequent instructions retire later"
RISCV_thsyncs:         "Ensures that preceding instructions retire earlier and subsequent instructions retire later"
RISCV_thsynci:         "Ensures that preceding instructions retire earlier and subsequent instructions retire later"
RISCV_thsyncis:        "Ensures that preceding instructions retire earlier and subsequent instructions retire later"
RISCV_thaddsl:         "Add a shifted operand to a second operand"
RISCV_thsrri:          "Rotate Right (by Immediate)"
RISCV_thsrriw:         "Rotate Right Word (by Immediate)"
RISCV_thext:           "Extract and sign-extend bits"
RISCV_thextu:          "Extract and zero-extend bits"
RISCV_thff0:           "Find first '0'-bit"
RISCV_thff1:           "Find first '1'-bit"
RISCV_threv:           "Reverse the byte order"
RISCV_threvw:          "Reverse the byte order of a word operand"
RISCV_thtstnbz:        "Test for NUL bytes"
RISCV_thtst:           "Tests if a single bit is set"
RISCV_thmveqz:         "Move if equal zero"
RISCV_thmvnez:         "Move if not equal zero"
RISCV_thlbia:          "Load indexed byte"
RISCV_thlbib:          "Load indexed byte"
RISCV_thlbuia:         "Load indexed unsigned byte"
RISCV_thlbuib:         "Load indexed unsigned byte"
RISCV_thlhia:          "Load indexed half-word"
RISCV_thlhib:          "Load indexed half-word"
RISCV_thlhuia:         "Load indexed unsigned half-word"
RISCV_thlhuib:         "Load indexed unsigned half-word"
RISCV_thlwia:          "Load indexed word"
RISCV_thlwib:          "Load indexed word"
RISCV_thlwuia:         "Load indexed unsigned word"
RISCV_thlwuib:         "Load indexed unsigned word"
RISCV_thldia:          "Load indexed double-word"
RISCV_thldib:          "Load indexed double-word"
RISCV_thsbia:          "Store indexed byte"
RISCV_thsbib:          "Store indexed byte"
RISCV_thshia:          "Store indexed half-word"
RISCV_thshib:          "Store indexed half-word"
RISCV_thswia:          "Store indexed word"
RISCV_thswib:          "Store indexed word"
RISCV_thsdia:          "Store indexed double-word"
RISCV_thsdib:          "Store indexed double-word"
RISCV_thlrb:           "Load indexed byte"
RISCV_thlrbu:          "Load indexed unsigned byte"
RISCV_thlrh:           "Load indexed half-word"
RISCV_thlrhu:          "Load indexed unsigned half-word"
RISCV_thlrw:           "Load indexed word"
RISCV_thlrwu:          "Load indexed unsigned word"
RISCV_thlrd:           "Load indexed word"
RISCV_thsrb:           "Store indexed byte"
RISCV_thsrh:           "Store indexed half-word"
RISCV_thsrw:           "Store indexed word"
RISCV_thsrd:           "Store indexed double-word"
RISCV_thlurb:          "Load unsigned indexed byte"
RISCV_thlurbu:         "Load unsigned indexed unsigned byte"
RISCV_thlurh:          "Load unsigned indexed half-word"
RISCV_thlurhu:         "Load unsigned indexed unsigned half-word"
RISCV_thlurw:          "Load unsigned indexed word"
RISCV_thlurwu:         "Load unsigned indexed unsigned word"
RISCV_thlurd:          "Load unsigned indexed double-word"
RISCV_thsurb:          "Store unsigned indexed byte"
RISCV_thsurh:          "Store unsigned indexed half-word"
RISCV_thsurw:          "Store unsigned indexed word"
RISCV_thsurd:          "Store unsigned indexed double-word"
RISCV_thldd:           "Load two 64-bit values from memory into two GPRs"
RISCV_thlwd:           "Load two signed 32-bit values from memory into two GPRs"
RISCV_thlwud:          "Load two unsigned 32-bit values from memory into two GPRs"
RISCV_thsdd:           "Store two 64-bit values to memory from two GPRs"
RISCV_thswd:           "Store two 32-bit values to memory from two GPRs"
RISCV_thflrd:          "Load indexed double-precision floating point value"
RISCV_thflrw:          "Load indexed single-precision floating point value"
RISCV_thflurd:         "Load unsigned indexed double-precision floating point value"
RISCV_thflurw:         "Load unsigned indexed single-precision floating point value"
RISCV_thfsrd:          "Store indexed double-precision floating point value"
RISCV_thfsrw:          "Store indexed single-precision floating point value"
RISCV_thfsurd:         "Store unsigned indexed double-precision floating point value"
RISCV_thfsurw:         "Store unsigned indexed single-precision floating point value"
RISCV_thmula:          "Compute multiply-add result of double-word operands"
RISCV_thmulah:         "Compute multiply-add result of half-word operands"
RISCV_thmulaw:         "Compute multiply-add result of word operands"
RISCV_thmuls:          "Compute multiply-subtract result of double-word operands"
RISCV_thmulsh:         "Compute multiply-subtract result of half-word operands"
RISCV_thmulsw:         "Compute multiply-subtract result of word operands"
RISCV_thfmv:           "R/W double-precision floating-point high-bit data"
RISCV_thipush:         "Pushes register context on the interrupt stack"
RISCV_thipop:          "Pop register context from the interrupt stack"
RISCV_thandn:          "And with inverted operand rs2 (undocumented)"
RISCV_thorn:           "Or with inverted operand rs2 (undocumented)"
RISCV_thxorn:          "Exclusive nor (undocumented)"
RISCV_thpackl:         "Pack some bytes of rs1 and rs2 into rd (undocumented)"
RISCV_thpackh:         "Pack the low bytes of rs1 and rs2 into rd (undocumented)"
RISCV_thpackhl:        "Pack some bytes of rs1 and rs2 into rd (undocumented)"
RISCV_thvmaqa:         "Four signed 8-bit multiply with 32-bit add"
RISCV_thvmaqau:        "Four unsigned 8-bit multiply with 32-bit add"
RISCV_thvmaqasu:       "Four signed-unsigned 8-bit multiply with 32-bit add"
RISCV_thvmaqaus:       "Four unsigned-signed 8-bit multiply with 32-bit add"
RISCV_thvpmaqa:        "Similar to vmaqa, presumably involving packed values (undocumented)"
RISCV_thvpmaqau:       "Similar to vmaqau, presumably involving packed values (undocumented)"
RISCV_thvpmaqaus:      "Similar to vmaqaus, presumably involving packed values (undocumented)"
RISCV_thvpmaqasu:      "Similar to vmaqasu, presumably involving packed values (undocumented)"
RISCV_thvpnclip:       "Similar to vnclip, presumably involving packed values (undocumented)"
RISCV_thvpnclipu:      "Similar to vnclipu, presumably involving packed values (undocumented)"
RISCV_thvpwadd:        "Similar to vadd, presumably involving packed values (undocumented)"
RISCV_thvpwaddu:       "Similar to vaddu, presumably involving packed values (undocumented)"