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|
Version:
9.0~240807-1.fc42 ▾
|
SYS =
{
"IC IALLUIS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"IC IALLU" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"DC IVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"DC ISW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"DC IGVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"DC IGSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"DC IGDVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"DC IGDSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "110" } ],
"AT S1E1R" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"AT S1E1W" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"AT S1E0R" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"AT S1E0W" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"AT S1E1RP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"AT S1E1WP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "001" } ],
"AT S1E1A" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"DC CSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"DC CGSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"DC CGDSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "110" } ],
"DC CISW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "010" } ],
"DC CIGSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "100" } ],
"DC CIGDSW" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "110" } ],
"TLBI VMALLE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBI ASIDE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"TLBI VAAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"TLBIP VAAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"TLBI VALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBI VAALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"TLBIP VAALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVAAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RVAAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"TLBI RVALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RVAALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"TLBI VMALLE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBI ASIDE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"TLBI VAAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"TLBIP VAAE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"TLBI VALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBI VAALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"TLBIP VAALE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVAAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RVAAE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"TLBI RVALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RVAALE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVAAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RVAAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"TLBI RVALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RVAALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"TLBI VMALLE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBI ASIDE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"TLBI VAAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"TLBIP VAAE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"TLBI VALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBI VAALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"TLBIP VAALE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"TLBI VMALLE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBI ASIDE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"TLBI VAAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"TLBIP VAAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"TLBI VALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBI VAALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"TLBIP VAALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVAAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RVAAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"TLBI RVALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RVAALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"TLBI VMALLE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBI ASIDE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"TLBI VAAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"TLBIP VAAE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"TLBI VALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBI VAALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"TLBIP VAALE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVAAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RVAAE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"TLBI RVALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RVAALE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVAAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RVAAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"TLBI RVALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RVAALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"TLBI VMALLE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBI ASIDE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"TLBI VAAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"TLBIP VAAE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"TLBI VALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBI VAALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"TLBIP VAALE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"BRB IALL" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"BRB INJ" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"CFP RCTX" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"DVP RCTX" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"CPP RCTX" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"DC ZVA" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"DC GVA" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"DC GZVA" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"IC IVAU" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"DC CVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"DC CGVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"DC CGDVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "101" } ],
"DC CVAU" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"DC CVAP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"DC CGVAP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"DC CGDVAP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"DC CVADP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "001" } ],
"DC CGVADP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"DC CGDVADP" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"DC CIVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"DC CIGVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"DC CIGDVAC" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "101" } ],
"AT S1E2R" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"AT S1E2W" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"AT S12E1R" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "100" } ],
"AT S12E1W" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "101" } ],
"AT S12E0R" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "110" } ],
"AT S12E0W" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "111" } ],
"AT S1E2A" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"DC CIPAE" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"DC CIGDPAE" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "111" } ],
"TLBI IPAS2E1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TLBIP IPAS2E1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TLBI RIPAS2E1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TLBIP RIPAS2E1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TLBI IPAS2LE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"TLBIP IPAS2LE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"TLBI RIPAS2LE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TLBIP RIPAS2LE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TLBI ALLE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBI ALLE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBI VMALLS12E1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"TLBI RVAE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBI VMALLWS2E1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"TLBI RVALE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBI ALLE1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE2IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBI VMALLS12E1IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "110" } ],
"TLBI IPAS2E1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"TLBIP IPAS2E1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"TLBI IPAS2E1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"TLBIP IPAS2E1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"TLBI RIPAS2E1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"TLBIP RIPAS2E1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"TLBI RIPAS2E1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RIPAS2E1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"TLBI IPAS2LE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"TLBIP IPAS2LE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"TLBI IPAS2LE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"TLBIP IPAS2LE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"TLBI RIPAS2LE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"TLBIP RIPAS2LE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"TLBI RIPAS2LE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RIPAS2LE1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBI VMALLWS2E1OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"TLBI RVALE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE2OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBI VMALLWS2E1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"TLBI RVALE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBI ALLE1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE2" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBI VMALLS12E1" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "110" } ],
"TLBI IPAS2E1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TLBIP IPAS2E1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TLBI RIPAS2E1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TLBIP RIPAS2E1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TLBI IPAS2LE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"TLBIP IPAS2LE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"TLBI RIPAS2LE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TLBIP RIPAS2LE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TLBI ALLE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBI ALLE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBI VMALLS12E1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"TLBI RVAE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBI VMALLWS2E1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"TLBI RVALE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBI ALLE1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE2ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBI VMALLS12E1ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "110" } ],
"TLBI IPAS2E1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"TLBIP IPAS2E1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"TLBI IPAS2E1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"TLBIP IPAS2E1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"TLBI RIPAS2E1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"TLBIP RIPAS2E1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"TLBI RIPAS2E1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"TLBIP RIPAS2E1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"TLBI IPAS2LE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"TLBIP IPAS2LE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"TLBI IPAS2LE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"TLBIP IPAS2LE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"TLBI RIPAS2LE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"TLBIP RIPAS2LE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"TLBI RIPAS2LE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"TLBIP RIPAS2LE1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBI VMALLWS2E1OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"TLBI RVALE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE2OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBI VMALLWS2E1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"TLBI RVALE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBI ALLE1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE2NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBI VMALLS12E1NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "110" } ],
"AT S1E3R" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"AT S1E3W" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"AT S1E3A" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"DC CIPAPA" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"DC CIGDPAPA" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBI PAALLOS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVALE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBI VALE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE3IS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBI RPAOS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"TLBI RPALOS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"TLBI RVAE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVALE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE3OS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVALE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBI PAALL" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"TLBI VALE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE3" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TLBI VALE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVALE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TLBI VALE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE3ISNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVALE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE3OSNXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"TLBI RVAE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBIP RVAE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"TLBI RVALE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBIP RVALE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"TLBI ALLE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"TLBI VAE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBIP VAE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"TLBI VALE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TLBIP VALE3NXS" : [ { "mask" : "11", "value" : "01" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"TTBR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TTBR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"PAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"RCWSMASK_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"RCWMASK_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TTBR0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TTBR1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"VTTBR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TTBR0_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TTBR1_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"S3_<op1>_C<Cn>_C<Cm>_<op2>": [ { "mask" : "11", "value" : "11" }, { "mask" : "000", "value" : "000" }, { "mask" : "1011", "value" : "1011" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "000", "value" : "000" } ]
}
MRSMSR =
{
"UAOIMM" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"PANIMM" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"SPSELIMM" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"SSBSIMM" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"DITIMM" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"DAIFSET" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"DAIFCLR" : [ { "mask" : "11", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"OSDTRRX_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"MDCCINT_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"MDSCR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"OSDTRTX_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"MDSELR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"MDSTEPOP_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"DBGWFAR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"OSECCR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"MDRAR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"OSLAR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"OSLSR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"OSDLR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"DBGPRCR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"DBGCLAIMSET_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "110" } ],
"DBGCLAIMCLR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "110" } ],
"DBGAUTHSTATUS_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "110" } ],
"SPMACCESSR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"SPMIIDR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"SPMDEVARCH_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"SPMDEVAFF_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "110" } ],
"SPMCFGR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "111" } ],
"SPMINTENSET_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"SPMINTENCLR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "010" } ],
"PMCCNTSVR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"PMICNTSVR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"TRCTRACEIDR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TRCVICTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TRCIDR8" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TRCIMSPEC0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"TRCPRGCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"TRCQCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"TRCVIIECTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"TRCIDR9" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"TRCITEEDCR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TRCVISSCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"TRCIDR10" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"TRCSTATR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TRCVIPCSSCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"TRCIDR11" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "110" } ],
"TRCCONFIGR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR12" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"TRCIDR13" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "110" } ],
"TRCAUXCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"TRCSEQRSTEVR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"TRCSEQSTR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"TRCEVENTCTL0R" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "111" } ],
"TRCEVENTCTL1R" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "111" } ],
"TRCRSR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR2" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "111" } ],
"TRCSTALLCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR3" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"TRCTSCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR4" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "111" } ],
"TRCSYNCPR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR5" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "111" } ],
"TRCCCCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR6" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "111" } ],
"TRCBBCTLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"TRCIDR7" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "111" } ],
"TRCOSLSR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"TRCCIDCCTLR0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TRCCIDCCTLR1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"TRCVMIDCCTLR0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"TRCVMIDCCTLR1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"TRCDEVID" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"TRCCLAIMSET" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "110" } ],
"TRCCLAIMCLR" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "110" } ],
"TRCAUTHSTATUS" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "110" } ],
"TRCDEVARCH" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "110" } ],
"BRBCR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"BRBFCR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"BRBTS_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"BRBINFINJ_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"BRBSRCINJ_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"BRBTGTINJ_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"BRBIDR0_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"TEECR32_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TEEHBR32_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"MDCCSR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"DBGDTR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"DBGDTRRX_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"DBGDTRTX_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"SPMCR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"SPMCNTENSET_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"SPMCNTENCLR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"SPMOVSCLR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"SPMZR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"SPMSELR_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"SPMOVSSET_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"DBGVCR32_EL2" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"BRBCR_EL2" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"SPMACCESSR_EL2" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"BRBCR_EL12" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"SPMACCESSR_EL12" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"SPMACCESSR_EL3" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"SPMROOTCR_EL3" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "111" } ],
"SPMSCR_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "111" } ],
"MIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"MPIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"REVIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"ID_PFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"ID_PFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"ID_DFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"ID_AFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"ID_MMFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"ID_MMFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"ID_MMFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"ID_MMFR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"ID_ISAR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"ID_ISAR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"ID_ISAR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"ID_ISAR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"ID_ISAR4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"ID_ISAR5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"ID_MMFR4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"ID_ISAR6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"MVFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"MVFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"MVFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"ID_AA32RES3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"ID_PFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"ID_DFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"ID_MMFR5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "110" } ],
"ID_AA32RES7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"ID_AA64PFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"ID_AA64PFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"ID_AA64PFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"ID_AA64PFR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"ID_AA64ZFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"ID_AA64SMFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"ID_AA64ZFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"ID_AA64FPFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"ID_AA64DFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"ID_AA64DFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"ID_AA64DFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"ID_AA64DFR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"ID_AA64AFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "100" } ],
"ID_AA64AFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"ID_AA64AFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "110" } ],
"ID_AA64AFR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "111" } ],
"ID_AA64ISAR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"ID_AA64ISAR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"ID_AA64ISAR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"ID_AA64ISAR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"ID_AA64ISAR4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"ID_AA64ISAR5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"ID_AA64ISAR6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "110" } ],
"ID_AA64ISAR7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"ID_AA64MMFR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"ID_AA64MMFR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"ID_AA64MMFR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"ID_AA64MMFR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"ID_AA64MMFR4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"ID_AA64MMFR5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"ID_AA64MMFR6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "110" } ],
"ID_AA64MMFR7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"SCTLR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ACTLR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"CPACR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"SCTLR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"RGSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"GCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"ZCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"TRFCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TRCITECR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"SMPRI_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"SMCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"TTBR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TTBR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TCR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"APIAKeyLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"APIAKeyHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"APIBKeyLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"APIBKeyHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"APDAKeyLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"APDAKeyHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"APDBKeyLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"APDBKeyHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"APGAKeyLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"APGAKeyHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"GCSCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"GCSPR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"GCSCRE0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"SPSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ELR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"SP_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"SPSel" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"CurrentEL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"PAN" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"UAO" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"ALLINT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"PM" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"ICC_PMR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"AFSR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"AFSR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"ESR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"ERRIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"ERRSELR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"ERXGSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"ERXFR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"ERXCTLR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"ERXSTATUS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"ERXADDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"ERXPFGF_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"ERXPFGCTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"ERXPFGCDN_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"ERXMISC0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"ERXMISC1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"ERXMISC2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"ERXMISC3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"TFSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"TFSRE0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"FAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"PFAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"PAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"PMSCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"PMSNEVFR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "001" } ],
"PMSICR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"PMSIRR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "011" } ],
"PMSFCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "100" } ],
"PMSEVFR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"PMSLATFR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "110" } ],
"PMSIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "111" } ],
"PMBLIMITR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"PMBPTR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"PMBSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"PMSDSFR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"PMBIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "111" } ],
"TRBLIMITR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"TRBPTR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"TRBBASER_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "010" } ],
"TRBSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"TRBMAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "100" } ],
"TRBMPAM_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"TRBTRG_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "110" } ],
"TRBIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"PMSSCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"PMINTENSET_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"PMINTENCLR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "010" } ],
"PMUACR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "100" } ],
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"PMIAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "111" } ],
"MAIR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"MAIR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"PIRE0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"PIR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"POR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"S2POR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"AMAIR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"AMAIR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"LORSA_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"LOREA_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"LORN_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"LORC_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"MPAMIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"LORID_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"MPAM1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"MPAM0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"MPAMSM_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"VBAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"RVBAR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"RMR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"ISR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"DISR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"ICC_IAR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"ICC_EOIR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"ICC_HPPIR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"ICC_BPR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"ICC_NMIAR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"ICC_DIR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"ICC_RPR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"ICC_SGI1R_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"ICC_ASGI1R_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "110" } ],
"ICC_SGI0R_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"ICC_IAR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"ICC_EOIR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"ICC_HPPIR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"ICC_BPR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"ICC_CTLR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"ICC_SRE_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"ICC_IGRPEN0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "110" } ],
"ICC_IGRPEN1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "111" } ],
"CONTEXTIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"RCWSMASK_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"TPIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"ACCDATA_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"RCWMASK_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"SCXTNUM_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"CNTKCTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"HID0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"EHID0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"HID25" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"HID26_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"HID27_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"HID28" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"HID29" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"HID1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"EHID1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"EHID20_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"HID21_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"HID22" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"HID23" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"HID2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"EHID2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"HID3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"EHID3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"HID4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"EHID4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"HID5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"EHID5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"HID6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"HID7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"EHID7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"HID8_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"HID9_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"EHID9_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "001" } ],
"HID10_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"EHID10_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"BLOCK_CMAINT_CFG" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"HID11_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"EHID11_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"HID18_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "010" } ],
"EHID18_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"HID12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"HID15" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"HID19" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"BIU_TLIMIT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"HID13_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"HID14_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"HID16_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "010" } ],
"LLC_WRR2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "011" } ],
"HID17_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "101" } ],
"HID24" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "110" } ],
"CCSIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"CLIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"CCSIDR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"GMID_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"SMIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"AIDR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"PMCR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"APPL_CONTEXTPTR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"LD_LATPROF_CTL_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTL01_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"PM_MEMFLT_CTL23_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"REDIR_ACNTV_CTL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"LCL_ACNTVCTSS_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"PMCR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_CTR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTL23_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"PM_MEMFLT_CTL45_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"ACNTRDIR_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"ACNTKCTL_NOREDIR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"PMCR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTL45_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTHP_CVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"LCL_CNTVCT_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"ACNTP_CVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"PMCR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_INF_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTL67_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTHP_TVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"LCL_CNTPCTSS_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"ACNTP_TVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "110" } ],
"PMCR4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MEMFLT_CTL01_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTHP_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"LCL_CNTVCTSS_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"ACNTP_CTL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"PMESR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_CMD_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MEMFLT_CTL23_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTHV_CVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "100" } ],
"ACNTV_CVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "110" } ],
"PMESR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"PMCR1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MEMFLT_CTL45_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTHV_TVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"CNTKCTL_NOREDIR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"ACNTV_TVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "110" } ],
"OPMAT0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"PMCR1_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MEMFLT_CTL67_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTHV_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"CNTP_CVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"ACNTV_CTL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "110" } ],
"OPMAT1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"PMCR1_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTFRQ_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "100" } ],
"CNTP_TVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "101" } ],
"LCL_CNTPCT_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "110" } ],
"OPMSK0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_CTL_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "011" } ],
"ACNTVOFF_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "100" } ],
"CNTP_CTL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"CNTV_CTL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "110" } ],
"OPMSK1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"LD_LATPROF_INF_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"AON_CPU_MSTALL_CTR2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTP_CVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"CNTV_CVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "101" } ],
"LCL_ACNTPCT_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "110" } ],
"PMCR_AFFINITY_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"AON_CPU_MSTALL_CTR3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTP_TVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "100" } ],
"CNTV_TVAL_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"VMSA_HV_LOCK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "110" } ],
"PMSWCTRL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"PMCR5_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"AON_CPU_MSTALL_CTR4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"PMCompare0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"PMCompare1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"VMSA_NV_LOCK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "110" } ],
"PMSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"AON_CPU_MSTALL_CTR5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTP_CTL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"PMCompare5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"PMCompare6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "110" } ],
"PMCompare7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "111" } ],
"PMCR_BVRNG4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"PM_PMI_PC" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"AON_CPU_MSTALL_CTR6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTV_CVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "100" } ],
"LCL_ACNTVCT_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "101" } ],
"PMCR_BVRNG5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"AON_CPU_MSTALL_CTR7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "011" } ],
"REDIR_ACNTV_TVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "100" } ],
"LCL_ACNTPCTSS_NOREDIR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "101" } ],
"CSSELR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"PMC0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"UPMCFILTER0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"UPMCFILTER1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"UPMCFILTER2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"UPMCFILTER3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"UPMCFILTER4" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"UPMCFILTER5" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"UPMCFILTER6" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"PMC1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"UPMCFILTER7" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"PMC2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"PMC3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"PMC4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"PMC5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"PMC6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"PMC7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"PMC8_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"PMC9_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"PMTRHLD6" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"PMTRHLD4" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"PMTRHLD2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"PMMMAP" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "010" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"CTR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"DCZID_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"RNDR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"RNDRRS" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"GCSPR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"NZCV" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"DAIF" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"SVCR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"DIT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"SSBS" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"TCO" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"FPCR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"FPSR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"FPMR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"DSPSR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"DLR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"PMICNTR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"PMICFILTR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"PMCR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"PMCNTENSET_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"PMCNTENCLR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"PMOVSCLR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"PMSWINC_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"PMSELR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"PMCEID0_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "110" } ],
"PMCEID1_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "111" } ],
"PMCCNTR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"PMXEVTYPER_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "001" } ],
"PMXEVCNTR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "010" } ],
"PMZR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"PMUSERENR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"PMOVSSET_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"POR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"TPIDR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TPIDRRO_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"TPIDR2_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"SCXTNUM_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"AMCR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"AMCFGR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"AMCGCR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"AMUSERENR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"AMCNTENCLR0_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"AMCNTENSET0_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"AMCG1IDR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"AMCNTENCLR1_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"AMCNTENSET1_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"CNTFRQ_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"CNTPCT_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"CNTVCT_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"CNTPCTSS_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"CNTVCTSS_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"CNTP_TVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"CNTP_CTL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"CNTP_CVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"CNTV_TVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"CNTV_CTL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"CNTV_CVAL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"PMCCFILTR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "111" } ],
"LSU_ERR_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"AFLATCTL1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"AFLATVALBIN0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"AFLATINFLO_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"LSU_ERR_CTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"AFLATCTL2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"AFLATVALBIN1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"AFLATINFHI_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"E_LSU_ERR_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"AFLATCTL3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"AFLATVALBIN2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"AFLATCTL4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"AFLATVALBIN3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"LLC_FILL_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"AFLATCTL5_LO_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"AFLATVALBIN4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"AFLATCTL5_HI_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"LLC_FILL_DAT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"AFLATVALBIN5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"AFLATVALBIN6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"L2_CRAMCONFIG" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"AFLATVALBIN7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"L2C_ERR_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"L2E_ERR_STS" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"CMAINT_BCAST_LIST_1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"CMAINT_BCAST_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"L2C_ERR_ADR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"L2E_ERR_ADR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "001" } ],
"LLC_ERR_INJ" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"L2C_ERR_INF_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"L2E_ERR_INF" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"UUSERTAG_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"KUSERTAG_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"HUSERTAG_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"LLC_TRACE_CTL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"LLC_TRACE_CTL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"LLC_UP_REQ_VC" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"LLC_UP_REQ_VC_THRESH" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "001" } ],
"LLC_UP_REQ_VC_2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "010" } ],
"LLC_UP_REQ_VC_THRESH_2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"LLC_DRAM_HASH0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"LLC_DRAM_HASH1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"LLC_DRAM_HASH2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "110" } ],
"LLC_DRAM_HASH3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "111" } ],
"LLC_TRACE_CTL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"LLC_HASH0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"LLC_HASH1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "001" } ],
"LLC_HASH2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "010" } ],
"LLC_HASH3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "011" } ],
"LLC_WRR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "100" } ],
"VPIDR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"VMPIDR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"SCTLR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ACTLR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"SCTLR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"HCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"MDCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"CPTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"HSTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"HFGRTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"HFGWTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"HFGITR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"HACR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"ZCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"TRFCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"HCRX_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"TRCITECR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"SMPRIMAP_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"SMCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"SDER32_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"TTBR0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TTBR1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TCR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"VTTBR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"VTCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"VNCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"HDBSSBR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"HDBSSPROD_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"HACDBSBR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"HACDBSCONS_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"GCSCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"GCSPR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"VSTTBR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"VSTCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"DACR32_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"HDFGRTR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"HDFGWTR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"HFGRTR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"HFGWTR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"HDFGRTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"HDFGWTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"HAFGRTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"HFGITR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"SPSR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ELR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"SP_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"SPSR_irq" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"SPSR_abt" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"SPSR_und" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"SPSR_fiq" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"IFSR32_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"AFSR0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"AFSR1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"ESR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"VSESR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"FPEXC32_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"TFSR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"FAR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"HPFAR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"PFAR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"PMSCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"MAIR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"MAIR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"PIRE0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"PIR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"POR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"S2PIR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"AMAIR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"AMAIR2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"MPAMHCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"MPAMVPMV_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"MPAM2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"MPAMVPM0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"MPAMVPM1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"MPAMVPM2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"MPAMVPM3_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"MPAMVPM4_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"MPAMVPM5_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"MPAMVPM6_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "110" } ],
"MPAMVPM7_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"MECID_P0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"MECID_A0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"MECID_P1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"MECID_A1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"MECIDR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "111" } ],
"VMECID_P_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"VMECID_A_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "001" } ],
"VBAR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"RVBAR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"RMR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"VDISR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"ICC_SRE_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"ICH_HCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"ICH_VTR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"ICH_MISR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "010" } ],
"ICH_EISR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"ICH_ELRSR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"ICH_VMCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"CONTEXTIDR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TPIDR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"SCXTNUM_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"CNTVOFF_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"CNTPOFF_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"CNTHCTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"CNTHP_TVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"CNTHP_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"CNTHP_CVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"CNTHV_TVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"CNTHV_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"CNTHV_CVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"CNTHVS_TVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"CNTHVS_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"CNTHVS_CVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"CNTHPS_TVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"CNTHPS_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"CNTHPS_CVAL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"FED_ERR_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"FED_ERR_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"E_FED_ERR_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"APCTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"SPR_LOCKDOWN_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"IMPL_MSR_RO_CTRL0_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"KERNKEYLO_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"KERNKEYHI_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"VMSA_LOCK_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"AMX_STATE_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"AMX_CONFIG_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"VMSA_LOCK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"CTRR_B_UPR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"CTRR_B_LWR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"APRR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"APRR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"CTRR_LOCK_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"CTRR_A_LWR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"CTRR_A_UPR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"CTRR_CTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"VMSA_LOCK_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"APRR_JIT_MASK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "111" } ],
"AMX_STATE_C0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"AMX_STATE_C1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"AMX_STATE_C2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"AMX_STATE_C3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"AMX_STATUS_C0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"AMX_STATUS_C1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"AMX_STATUS_C2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "110" } ],
"AMX_STATUS_C3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "111" } ],
"AMX_NUMCTXT_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"ACNTP_CVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"REDIR_ACNTP_TVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"ACNTP_CTL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"ACNTV_CVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"ACNTV_TVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"AMX_CONFIG_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "110" } ],
"AMX_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "111" } ],
"CORE_INDEX" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"SPRR_PPERM_EL20" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"SPRR_UPERM_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"AMX_PRIORITY_C0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "110" } ],
"AMX_PRIORITY_C1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "111" } ],
"AMX_PRIORITY_C2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"AMX_PRIORITY_C3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"CTRR_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"CTRR_LOCK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"CTRR_A_LWR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"CTRR_A_UPR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"CTRR_B_LWR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "110" } ],
"CTRR_B_UPR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"SPRR_UMPRR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"SPRR_UPERM_SH1_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"SPRR_UPERM_SH2_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"SPRR_UPERM_SH3_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"SPRR_HUPERM_SH04_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"SPRR_HUPERM_SH05_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"SPRR_HUPERM_SH06_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "110" } ],
"SPRR_HUPERM_SH07_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"SPRR_UMPRR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"SPRR_UPERM_SH1_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"SPRR_UPERM_SH2_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"SPRR_UPERM_SH3_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"SPRR_VUPERM_SH04_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "100" } ],
"SPRR_VUPERM_SH05_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "101" } ],
"SPRR_VUPERM_SH06_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "110" } ],
"SPRR_VUPERM_SH07_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "111" } ],
"CTRR_A_LWR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"CTRR_A_UPR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "001" } ],
"CTRR_B_LWR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"CTRR_B_UPR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "011" } ],
"CTRR_CTL_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "100" } ],
"CTRR_LOCK_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"REDIR_ACNTKCTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "110" } ],
"ACNTKCTL_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "111" } ],
"PREDAKEYLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"PREDAKEYHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"PREDBKEYLo_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"PREDBKEYHi_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"SIQ_CFG_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"ACNTPCT_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "101" } ],
"ACNTVCT_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "110" } ],
"AVNCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "111" } ],
"CTRR_A_LWR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"CTRR_A_UPR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"ACC_CTRR_B_LWR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "010" } ],
"ACC_CTRR_B_UPR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"CTRR_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "100" } ],
"CTRR_LOCK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"REDIR_LCL_ACNTPCT_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "110" } ],
"REDIR_LCL_ACNTVCT_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"ACFG_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"AHCR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"APL_INTSTATUS_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"APL_INTSTATUS_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"IMPL_MSR_LOCK_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"REDIR_ACNTHCTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "110" } ],
"IMPL_MSR_LOCK_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "111" } ],
"JAPIAKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"JAPIAKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "001" } ],
"JAPIBKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "010" } ],
"JAPIBKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"JAPIAKeyLo_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"JAPIAKeyHi_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"JAPIBKeyLo_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "110" } ],
"JAPIBKeyHi_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "111" } ],
"JAPIAKeyLo_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"JAPIAKeyHi_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"JAPIBKeyLo_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "010" } ],
"JAPIBKeyHi_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"ACNTRDIR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "101" } ],
"ACNTRDIR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "110" } ],
"JRANGE_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"JRANGE_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "001" } ],
"JRANGE_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "010" } ],
"JCTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "011" } ],
"JCTL_EL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "100" } ],
"JCTL_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "101" } ],
"JCTL_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "110" } ],
"AMDSCR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "111" } ],
"SCTLR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ACTLR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"CPACR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"SCTLR2_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"ZCR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"TRFCR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TRCITECR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"SMCR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"TTBR0_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TTBR1_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"TCR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TCR2_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"GCSCR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"GCSPR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "001" } ],
"SPSR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ELR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"AFSR0_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"AFSR1_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"ESR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"TFSR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"FAR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"PFAR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"PMSCR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"MAIR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"MAIR2_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"PIRE0_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"PIR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"POR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"AMAIR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"AMAIR2_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"MPAM1_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"VBAR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"CONTEXTIDR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"SCXTNUM_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"CNTKCTL_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"CNTP_TVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"CNTP_CTL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"CNTP_CVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"CNTV_TVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"CNTV_CTL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"CNTV_CVAL_EL02" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"IPI_RR_LOCAL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"IPI_RR_GLOBAL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"AF_ERR_CFG0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"AP_ERR_CFG0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"AF_ERR_SRC_IDS" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"DPC_ERR_STS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"DPC_ERR_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"TRACE_CORE_CFG" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"IPI_SR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"VM_TMR_LR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"VM_TMR_FIQ_ENA_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"KTRACE_MESSAGE" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"TRACE_CORE_CFG_EXT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"WatchDogDiag0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "110" } ],
"WatchDogDiag1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "111" } ],
"DBG_WRAP_GLB" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"TRACE_STREAM_BASE" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"TRACE_STREAM_FILL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"TRACE_STREAM_BASE1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"TRACE_STREAM_FILL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"TRACE_STREAM_IRQ" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"AWL_SCRATCH_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"TRACE_AUX_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "000" } ],
"IPI_CR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"UTRIG_EVENT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"TRACE_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"TRACE_DAT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"ACC_CFG_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"PBLK_STS" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"CYC_OVRD_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"PBLK_EXE_ST" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"ACC_OVRD_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "000" } ],
"ACC_EBLK_OVRD_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "001" } ],
"CPM_PWRDN_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"PRE_LLCFLUSH_TMR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"PRE_TD_TMR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"ACC_SLP_WAKE_UP_TMR" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"PBLK_PSW_DLY" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "000" } ],
"CPU_STS" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"HIST_TRIG" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"ARRAY_INDEX" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"IL1_DATA0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"IL1_DATA1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"DL1_DATA0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"DL1_DATA1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"MMUDATA0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"MMUDATA1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"LLC_DATA0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"LLC_DATA1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "101" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"SCTLR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"ACTLR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"SCTLR2_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"SCR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"SDER32_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"CPTR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"FGWTE3_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"ZCR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"SMCR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "110" } ],
"MDCR_EL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
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"SPRR_PPERM_SH2_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"SPRR_PPERM_SH3_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"SPRR_PPERM_SH04_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"SPRR_PPERM_SH05_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"SPRR_PPERM_SH06_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "110" } ],
"SPRR_PPERM_SH07_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "111" } ],
"APIAKeyLo_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "000" } ],
"APIAKeyHi_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "001" } ],
"APIBKeyLo_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"APIBKeyHi_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"APDAKeyLo_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"APDAKeyHi_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"APDBKeyLo_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "110" } ],
"APDBKeyHi_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "111" } ],
"GXF_STATUS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "000" } ],
"GXF_ENTRY_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "001" } ],
"GXF_PABENTRY_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"ASPSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"ADSPSR_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "100" } ],
"PMCR1_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "101" } ],
"ASPSR_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "110" } ],
"PMCR1_GL21" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "111" } ],
"VBAR_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"SPSR_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "011" } ],
"ASPSR_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "100" } ],
"ESR_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"ELR_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "110" } ],
"FAR_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "111" } ],
"SP_GL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "000" } ],
"TPIDR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "001" } ],
"VBAR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"SPSR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"ASPSR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"ESR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "101" } ],
"ELR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "110" } ],
"FAR_GL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "111" } ],
"SP_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "000" } ],
"TPIDR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "001" } ],
"VBAR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "010" } ],
"SPSR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"ASPSR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "100" } ],
"ESR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"ELR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "110" } ],
"FAR_GL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "111" } ],
"GXF_ENTRY_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "000" } ],
"GXF_PABENTRY_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "001" } ],
"APCTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"APSTS_EL2_MAYBE" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"APSTS_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"KERNKEYLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "101" } ],
"KERNKEYHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "110" } ],
"ASPSR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "111" } ],
"APIAKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "000" } ],
"APIAKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "001" } ],
"APIBKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "010" } ],
"APIBKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"APDAKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"APDAKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "101" } ],
"APDBKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "110" } ],
"APDBKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "111" } ],
"APGAKeyLo_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "000" } ],
"APGAKeyHi_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "001" } ],
"SPRR_CONFIG_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "010" } ],
"SPRR_AMRANGE_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"VMKEYLO_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "100" } ],
"VMKEYHI_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "101" } ],
"ACTLR_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "110" } ],
"APSTS_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "111" } ],
"APCTL_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "000" } ],
"GXF_CONFIG_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "001" } ],
"GXF_ENTRY_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "010" } ],
"GXF_PABENTRY_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "011" } ],
"SPRR_CONFIG_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "100" } ],
"SPRR_AMRANGE_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "101" } ],
"MMU_SESR_CTL_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "110" } ],
"SPRR_PPERM_EL12" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "110" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "111" } ],
"CNTPS_TVAL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"CNTPS_CTL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"CNTPS_CVAL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"PWRDNSAVE0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"NRG_ACC_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"AON_CNT0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"UPMCR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"UPMC8_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"PWRDNSAVE1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "000" } ],
"CORE_NRG_ACC_DAT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "001" } ],
"AON_CNT_CTL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "011" } ],
"UPMESR0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "100" } ],
"UPMC9_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "111", "value" : "101" } ],
"ACC_PWR_DN_SAVE" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"CPM_NRG_ACC_DAT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "001" } ],
"AON_CNT1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"UPMSWCTRL_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "100" } ],
"UPMC10_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "111", "value" : "101" } ],
"CORE_SRM_NRG_ACC_DAT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "001" } ],
"AON_CNT_CTL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "011" } ],
"UPMECM0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "100" } ],
"UPMC11_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "000" } ],
"CPM_SRM_NRG_ACC_DAT" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "001" } ],
"AON_CNT2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"UPMECM1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "100" } ],
"UPMC12_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"CPU_CNT_CTL" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "000" } ],
"AON_CNT_CTL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "011" } ],
"UPMPCM_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "100" } ],
"UPMC13_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0101" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"UPMSR_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "100" } ],
"UPMC14_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0110" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT_CTL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL3" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "011" } ],
"UPMC0_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "100" } ],
"UPMC15_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "0111" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT4" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT4" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "011" } ],
"UPMC1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "100" } ],
"UPMECM2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT_CTL4" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL4" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "011" } ],
"UPMC2_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "100" } ],
"UPMECM3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT5" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT5" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "011" } ],
"UPMC3_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "100" } ],
"UPMCR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1010" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT_CTL5" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL5" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "011" } ],
"UPMC4_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "100" } ],
"UPMESR1_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1011" }, { "mask" : "111", "value" : "101" } ],
"AON_CNT6" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT6" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "011" } ],
"UPMC5_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "111", "value" : "100" } ],
"AON_CNT_CTL6" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL6" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "011" } ],
"UPMC6_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "111", "value" : "100" } ],
"AON_CNT7" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT7" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "011" } ],
"UPMC7_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "111", "value" : "100" } ],
"AON_CNT_CTL7" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "010" } ],
"CPU_CNT_CTL7" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "1111", "value" : "1111" }, { "mask" : "111", "value" : "011" } ],
"SPMCGCR<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "110", "value" : "000" } ],
"TRCSEQEVR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1100", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"TRCCNTRLDVR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1100", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"TRCCNTCTLR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1100", "value" : "0100" }, { "mask" : "111", "value" : "101" } ],
"TRCEXTINSELR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1100", "value" : "1000" }, { "mask" : "111", "value" : "100" } ],
"TRCCNTVR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1100", "value" : "1000" }, { "mask" : "111", "value" : "101" } ],
"ICC_AP0R<m>_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "100", "value" : "100" } ],
"ICC_AP1R<m>_EL1" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "100", "value" : "000" } ],
"ICH_AP0R<m>_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "100", "value" : "000" } ],
"ICH_AP1R<m>_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1111", "value" : "1001" }, { "mask" : "100", "value" : "000" } ],
"TRCIMSPEC<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "1000", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"TRCSSCCR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1000", "value" : "0000" }, { "mask" : "111", "value" : "010" } ],
"TRCSSPCICR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1000", "value" : "0000" }, { "mask" : "111", "value" : "011" } ],
"TRCSSCSR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "1000", "value" : "1000" }, { "mask" : "111", "value" : "010" } ],
"TRCCIDCVR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "0001", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"TRCVMIDCVR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0011" }, { "mask" : "0001", "value" : "0000" }, { "mask" : "111", "value" : "001" } ],
"DBGBVR<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "111", "value" : "100" } ],
"DBGBCR<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "111", "value" : "101" } ],
"DBGWVR<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "111", "value" : "110" } ],
"DBGWCR<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "0000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "111", "value" : "111" } ],
"TRCACVR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "0001", "value" : "0000" }, { "mask" : "110", "value" : "000" } ],
"TRCACATR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0010" }, { "mask" : "0001", "value" : "0000" }, { "mask" : "110", "value" : "010" } ],
"SPMEVCNTR<m>_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1110", "value" : "0000" }, { "mask" : "000", "value" : "000" } ],
"SPMEVTYPER<m>_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1110", "value" : "0010" }, { "mask" : "000", "value" : "000" } ],
"SPMEVFILTR<m>_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1110", "value" : "0100" }, { "mask" : "000", "value" : "000" } ],
"SPMEVFILT2R<m>_EL0" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1110", "value" : "0110" }, { "mask" : "000", "value" : "000" } ],
"AMEVCNTR0<m>_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1110", "value" : "0100" }, { "mask" : "000", "value" : "000" } ],
"AMEVTYPER0<m>_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1110", "value" : "0110" }, { "mask" : "000", "value" : "000" } ],
"AMEVCNTR1<m>_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1110", "value" : "1100" }, { "mask" : "000", "value" : "000" } ],
"AMEVTYPER1<m>_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1110", "value" : "1110" }, { "mask" : "000", "value" : "000" } ],
"ICH_LR<m>_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1100" }, { "mask" : "1110", "value" : "1100" }, { "mask" : "000", "value" : "000" } ],
"AMEVCNTVOFF0<m>_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1110", "value" : "1000" }, { "mask" : "000", "value" : "000" } ],
"AMEVCNTVOFF1<m>_EL2" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "100" }, { "mask" : "1111", "value" : "1101" }, { "mask" : "1110", "value" : "1010" }, { "mask" : "000", "value" : "000" } ],
"PMEVCNTSVR<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "000" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1100", "value" : "1000" }, { "mask" : "000", "value" : "000" } ],
"TRCRSCTLR<m>" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "0001" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "110", "value" : "000" } ],
"BRBINF<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "011", "value" : "000" } ],
"BRBSRC<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "011", "value" : "001" } ],
"BRBTGT<m>_EL1" : [ { "mask" : "11", "value" : "10" }, { "mask" : "111", "value" : "001" }, { "mask" : "1111", "value" : "1000" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "011", "value" : "010" } ],
"PMEVCNTR<m>_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1100", "value" : "1000" }, { "mask" : "000", "value" : "000" } ],
"PMEVTYPER<m>_EL0" : [ { "mask" : "11", "value" : "11" }, { "mask" : "111", "value" : "011" }, { "mask" : "1111", "value" : "1110" }, { "mask" : "1100", "value" : "1100" }, { "mask" : "000", "value" : "000" } ],
"ALLINT" : [ { "mask" : "00", "value" : "00" }, { "mask" : "111", "value" : "001" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "1110", "value" : "0000" }, { "mask" : "111", "value" : "000" } ],
"PM" : [ { "mask" : "00", "value" : "00" }, { "mask" : "111", "value" : "001" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "1110", "value" : "0010" }, { "mask" : "111", "value" : "000" } ],
"SVCRSM" : [ { "mask" : "00", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "1110", "value" : "0010" }, { "mask" : "111", "value" : "011" } ],
"SVCRZA" : [ { "mask" : "00", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "1110", "value" : "0100" }, { "mask" : "111", "value" : "011" } ],
"SVCRSMZA" : [ { "mask" : "00", "value" : "00" }, { "mask" : "111", "value" : "011" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "1110", "value" : "0110" }, { "mask" : "111", "value" : "011" } ],
"S3_<op1>_C<Cn>_C<Cm>_<op2>": [ { "mask" : "11", "value" : "11" }, { "mask" : "000", "value" : "000" }, { "mask" : "1011", "value" : "1011" }, { "mask" : "0000", "value" : "0000" }, { "mask" : "000", "value" : "000" } ]
}
MSR_IMM =
{
"SSBS" : 25,
"DAIFSet" : 30,
"DAIFClr" : 31,
"TCO" : 28,
"DIT" : 26,
"SPSel" : 5,
"PAN" : 4,
"UAO" : 3
}
HINTS =
{
"FGWTE3_EL3" : "Provides controls for traps of MSR and MSRR writes to specified EL3 system\nregisters.",
"CGVADP" : "Clean Allocation tags by address to Point of Deep Persistence.\nIf the memory system does not identify a Point of Deep Persistence, then\nthis instruction behaves as a DC CGVAP.",
"PMBPTR_EL1" : "Defines the current write pointer for the profiling buffer.",
"RIPAS2E1IS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 2 only translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 2 only translation table entry, from any level of the translation\ntable walk, if TTL is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"NZCV" : "Allows access to the condition flags.",
"RVAE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange, and one of the following applies:\nThe entry is from a level of lookup above the final level and matches the\nspecified ASID.\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:",
"CCSIDR_EL1" : "Provides information about the architecture of the currently selected cache.",
"S12E1W" : "Performs stage 1 and 2 address translation, with permissions as if writing\nto the given virtual address from EL1, or from EL2 if the Effective value\nof HCR_EL2.{E2H, TGE} is {1, 1}, using the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"MIDR_EL1" : "Provides identification information for the PE, including an implementer\ncode for the device and a device ID number.",
"ERRIDR_EL1" : "Defines the highest numbered index of the error records that can be accessed\nthrough the Error Record System registers.",
"ID_AA64AFR1_EL1" : "Reserved for future expansion of information about the implementation defined\nfeatures of the PE in AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"RIPAS2E1OS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom any level of the translation table walk, if TTL is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SDER32_EL3" : "Allows access to the AArch32 register SDER from AArch64 state only. Its\nvalue has no effect on execution in AArch64 state.",
"CNTHPS_CTL_EL2" : "Control register for the Secure EL2 physical timer.",
"CNTHVS_TVAL_EL2" : "Holds the timer value for the Secure EL2 virtual timer.",
"DLR_EL0" : "In Debug state, holds the address to restart from.",
"DACR32_EL2" : "Allows access to the AArch32 DACR register from AArch64 state only. Its\nvalue has no effect on execution in AArch64 state.",
"HDFGWTR_EL2" : "Provides controls for traps of MSR and MCR writes of debug, trace, PMU,\nand Statistical Profiling System registers.",
"CNTPCT_EL0" : "Reads of CNTPCT_EL0 return the 64-bit physical count value minus a physical\noffset.",
"HDFGRTR2_EL2" : "Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and\nStatistical Profiling System registers.",
"ID_MMFR5_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch32 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"MDCR_EL3" : "Provides EL3 configuration options for self-hosted debug and the Performance\nMonitors Extension.",
"RCTX" : "Cache Prefetch Prediction Restriction by Context applies to all Cache Allocation\nResources that predict cache allocations based on information gathered\nwithin the target execution context or contexts.\nThe actions of code in the target execution context or contexts appearing\nin program order before the instruction cannot exploitatively control cache\nprefetch predictions occurring after the instruction is complete and synchronized.\nThis instruction applies to all:\nThis instruction is guaranteed to be complete following a DSB that covers\nboth read and write behavior on the same PE as executed the original restriction\ninstruction, and a subsequent context synchronization event is required\nto ensure that the effect of the completion of the instructions is synchronized\nto the current execution.\nThis instruction does not require the invalidation of Cache Allocation Resources\nso long as the behavior described for completion of this instruction is\nmet by the implementation.\nOn some implementations the instruction is likely to take a significant\nnumber of cycles to execute. This instruction is expected to be used very\nrarely, such as on the roll-over of an ASID or VMID, but should not be\nused on every context switch.",
"GCSPR_EL1" : "Contains the Guarded Control Stack Pointer at EL1.",
"RVAALE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the leaf level of the translation\ntable walk, indicated by the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom the leaf level of the translation table walk, if TTL is 0b00.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"RVAALE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the leaf level of the translation\ntable walk, indicated by the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom the leaf level of the translation table walk, if TTL is 0b00.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ID_MMFR4_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch32 state.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"ZCR_EL2" : "This register controls aspects of SVE visible at Exception levels EL2, EL1,\nand EL0.",
"PMIAR_EL1" : "Captures the address of the instruction generating a PMU exception.",
"ISR_EL1" : "Shows the pending status of IRQ and FIQ interrupts and SError exceptions.\nWhen FEAT_NMI is implemented, also shows whether a pending IRQ or FIQ interrupt\nhas Superpriority.",
"TRCCCCTLR" : "Set the threshold value for cycle counting.",
"PMBSR_EL1" : "Provides syndrome information to software when the buffer is disabled because\nthe management interrupt has been raised.",
"VALE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry.\nA 64-bit stage 1 translation table entry, if TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA, and one of the following\napplies:\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SPMDEVAFF_EL1" : "For additional information, see the CoreSight Architecture Specification.\nFor a System PMU that has affinity with a single PE or a group of PEs, SPMDEVAFF_EL1\nis a copy of MPIDR_EL1 or part of MPIDR_EL1:\nFor example, if the group of PEs is a subset of the PEs at affinity level\n1 then all of the following are true:\nDepending on the implementation defined nature of the system, it might be\npossible that SPMDEVAFF_EL1 is read before system firmware has configured\nthe System PMU and/or the PE or group of PEs that the System PMU has affinity\nwith. When this is the case, SPMDEVAFF_EL1 reads-as-zero.",
"ERXMISC1_EL1" : "Accesses ERR<n>MISC1 for the error record <n> selected by ERRSELR_EL1.SEL.",
"TRCCLAIMSET" : "In conjunction with TRCCLAIMCLR, provides Claim Tag bits that can be separately\nset and cleared to indicate whether functionality is in use by a debug\nagent.\nFor additional information, see the CoreSight Architecture Specification.",
"CurrentEL" : "Holds the current Exception level.",
"PFAR_EL2" : "Records the faulting physical address for a synchronous External abort,\nor SError exception taken to EL2.",
"GCSPOPCX" : "Loads an exception return record from the location indicated by the current\nGuarded Control Stack Pointer register, compares the values loaded with\nthe current ELR_ELx, SPSR_ELx, and LR, and increments the current Guarded\nControl Stack Pointer register by the size of a Guarded Control Stack exception\nreturn record.",
"RVBAR_EL2" : "If EL2 is the highest Exception level implemented, contains the implementation\ndefined address that execution starts from after reset when executing in\nAArch64 state.",
"VAE3OS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk.\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk, if TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL3 translation\nregime.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"IPAS2E1IS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from any level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom any level of the translation table walk, if TTL[3:2] is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMXEVCNTR_EL0" : "Reads or writes the value of the selected event counter, PMEVCNTR<n>_EL0.\nPMSELR_EL0.SEL determines which event counter is selected.",
"BRBSRCINJ_EL1" : "The source address of a Branch record for injection.",
"ID_AA64MMFR4_EL1" : "Provides additional information about implemented memory model and memory\nmanagement support in AArch64.",
"PMSCR_EL2" : "Provides EL2 controls for Statistical Profiling.",
"ALLE3OS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nThe entry would be required to translate an address using the EL3 translation\nregime.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"RCWMASK_EL1" : "Contains the mask used by RCW instructions.",
"S1E1RP" : "Performs a stage 1 address translation, where the value of PSTATE.PAN determines\nif a read from a location will generate a Permission fault for a privileged\naccess, using the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"VALE3" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL3 translation\nregime.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"BRBTGTINJ_EL1" : "The target address of a Branch record for injection.",
"MAIR2_EL2" : "Provides the memory attribute encodings corresponding to the possible AttrIndx\nvalues in a VMSAv8-64 or VMSAv9-128 translation table entry for stage 1\ntranslations at EL1.",
"TRCIDR5" : "Returns the tracing capabilities of the trace unit.",
"ID_PFR1_EL1" : "Gives information about the AArch32 programmers' model.\nMust be interpreted with ID_PFR0_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"VMALLS12E1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 or stage 2 translation table entry, from any level\nof the translation table walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to the PE that executes this System instruction.\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"CIGDPAE" : "Clean and invalidate of data and allocation tags by PA to PoE.",
"GCR_EL1" : "Tag Control Register.",
"ERXADDR_EL1" : "Accesses ERR<n>ADDR for the error record <n> selected by ERRSELR_EL1.SEL.",
"SPMINTENCLR_EL1" : "Disables the generation of interrupt requests on overflows from event counters\nin System PMU <s>.",
"SPMINTENSET_EL1" : "Enables the generation of interrupt requests on overflows from event counters\nin System PMU <s>.",
"ICC_HPPIR1_EL1" : "Indicates the highest priority pending Group 1 interrupt on the CPU interface.",
"MPAMVPM4_EL2" : "MPAMVPM4_EL2 provides mappings from virtual PARTIDs 16 - 19 to physical\nPARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2\nregisters. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs.\nIf MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register,\nMPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"SCTLR_EL1" : "Provides top level control of the system, including its memory system, at\nEL1 and EL0.",
"S1E0R" : "Performs stage 1 address translation from EL0, with permissions as if reading\nfrom the given virtual address from EL0, using the following translation\nregime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"MVFR2_EL1" : "Describes the features provided by the AArch32 Advanced SIMD and Floating-point\nimplementation.\nMust be interpreted with MVFR0_EL1 and MVFR1_EL1.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"PMECR_EL1" : "Provides EL1 configuration options for the Performance Monitors.",
"SPSR_EL1" : "Holds the saved process state when an exception is taken to EL1.",
"VMECID_A_EL2" : "Alternate MECID for EL1&0 stage 2 translation regime.",
"ELR_EL2" : "When taking an exception to EL2, holds the address to return to.",
"APDBKeyLo_EL1" : "Holds bits[63:0] of key B used for authentication of data pointer values.\nThe term APDBKey_EL1 is used to describe the concatenation of APDBKeyHi_EL1:\nAPDBKeyLo_EL1.",
"CONTEXTIDR_EL1" : "Identifies the current Process Identifier.\nThe value of the whole of this register is called the Context ID and is\nused by:\nThe significance of this register is for debug and trace use only.",
"ALLE3IS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nThe entry would be required to translate an address using the EL3 translation\nregime.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VAAE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk.\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk, if TTL is 0b00.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SSBS" : "Allows access to the Speculative Store Bypass Safe bit.",
"PMINTENCLR_EL1" : "Allows software to disable the generation of interrupt requests or, when\nFEAT_EBEP is implemented, PMU exceptions on overflows from the following\ncounters:\nReading from this register shows which overflow interrupt requests or PMU\nexceptions are enabled.",
"HFGRTR2_EL2" : "Provides controls for traps of MRRS, MRS and MRC reads of System registers.",
"PMCCNTSVR_EL1" : "Captures the PMU Cycle counter, PMCCNTR_EL0.",
"FAR_EL1" : "Holds the faulting Virtual Address for all synchronous Instruction Abort\nexceptions, Data Abort exceptions, PC alignment fault exceptions and Watchpoint\nexceptions that are taken to EL1.",
"HACDBSBR_EL2" : "Control register for HACDBS structure.",
"GCSPUSHM" : "Decrements the current Guarded Control Stack Pointer register by the size\nof a Guarded Control Stack procedure return record and stores an entry\nto the Guarded Control Stack.",
"TCR_EL2" : "The control register for stage 1 of the EL2, or EL2&0, translation regime:",
"ALLE2" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation only applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TRBBASER_EL1" : "Defines the base address for the trace buffer.",
"RVAE2" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any VA in the range determined by\nthe formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]\nusing the EL2 or EL2&0 translation regime, as determined by the Effective\nvalue of HCR_EL2.E2H, for the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from any level\nof the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is from a level of the translation table walk above the final\nlevel and matches the specified ASID.\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VMALLE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VAE2IS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry.\nA 64-bit stage 1 translation table entry, if TTL[3:2] is 0b00.\nThe entry would be required to translate the specified VA using the EL2\nor EL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H,\nfor the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from any level\nof the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is from a level of the translation table walk above the final\nlevel and matches the specified ASID.\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"CNTPS_CTL_EL1" : "Control register for the secure physical timer, usually accessible at EL3\nbut configurably accessible at EL1 in Secure state.",
"VAE2" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry.\nA 64-bit stage 1 translation table entry, if TTL[3:2] is 0b00.\nThe entry would be required to translate the specified VA using the EL2\nor EL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H,\nfor the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from any level\nof the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is from a level of the translation table walk above the final\nlevel and matches the specified ASID.\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ID_AA64AFR0_EL1" : "Provides information about the implementation defined features of the PE\nin AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"TRCPRGCTLR" : "Enables the trace unit.",
"VAE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA, and one of the following\napplies:\nThe entry is from a level of lookup above the final level and matches the\nspecified ASID.\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TRCIDR2" : "Returns the tracing capabilities of the trace unit.",
"ERXMISC0_EL1" : "Accesses ERR<n>MISC0 for the error record <n> selected by ERRSELR_EL1.SEL.",
"VALE2OS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL2 or\nEL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H,\nfor the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from the final\nlevel of the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"CNTV_CVAL_EL0" : "Holds the compare value for the virtual timer.",
"MECIDR_EL2" : "MEC identification register.",
"FPCR" : "Controls floating-point behavior.",
"AIDR_EL1" : "Provides implementation defined identification information.\nThe value of this register must be interpreted in conjunction with the value\nof MIDR_EL1.",
"CVAU" : "Clean data cache by address to Point of Unification.",
"TRCVICTLR" : "Controls instruction trace filtering.",
"CNTVCT_EL0" : "Reads of CNTVCT_EL0 return the 64-bit physical count value minus a virtual\noffset.",
"TRCCIDCCTLR0" : "Contains Context identifier mask values for the TRCCIDCVR<n> registers,\nfor n = 0 to 3.",
"SCR_EL3" : "Defines the configuration of the current Security state. It specifies:",
"PMCCFILTR_EL0" : "Determines the modes in which the Cycle Counter, PMCCNTR_EL0, increments.",
"TTBR0_EL3" : "Holds the base address of the translation table for the initial lookup for\nstage 1 of an address translation in the EL3 translation regime, and other\ninformation for this translation regime.",
"ICV_BPR0_EL1" : "Defines the point at which the priority value fields split into two parts,\nthe group priority field and the subpriority field. The group priority\nfield determines virtual Group 0 interrupt preemption.",
"ICC_SRE_EL1" : "Controls whether the System register interface or the memory-mapped interface\nto the GIC CPU interface is used for EL1.",
"MAIR2_EL3" : "Provides the memory attribute encodings corresponding to the possible AttrIndx\nvalues in a VMSAv8-64 or VMSAv9-128 translation table entry for stage 1\ntranslations at EL1.",
"TRCITECR_EL1" : "Provides EL1 controls for Trace Instrumentation.",
"TRCDEVID" : "Provides discovery information for the component.\nFor additional information, see the CoreSight Architecture Specification.",
"IPAS2E1OS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 2 only translation table entry, from any level of the translation\ntable walk.\nA 64-bit stage 2 only translation table entry, from any level of the translation\ntable walk, if TTL[3:2] is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ICH_HCR_EL2" : "Controls the environment for VMs.",
"IGSW" : "Invalidate Allocation Tags in data cache by set/way.",
"ELR_EL1" : "When taking an exception to EL1, holds the address to return to.",
"CIGDVAC" : "Clean and Invalidate data and Allocation Tags in data cache by address to\nPoint of Coherency.",
"TCR_EL3" : "The control register for stage 1 of the EL3 translation regime.",
"AFSR0_EL1" : "Provides additional implementation defined fault status information for\nexceptions taken to EL1.",
"ID_ISAR1_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR0_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1,\nand ID_ISAR5_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"TCR2_EL1" : "The control register for stage 1 of the EL1&0 translation regime.",
"VMALLS12E1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 or stage 2 translation table entry, from any level\nof the translation table walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFrom Armv8.4, when a TLB maintenance instruction is generated to the Secure\nEL1&0 translation regime and is defined to pass a VMID argument, or would\nbe defined to pass a VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"" : "",
"TRCIT" : "Generates an instrumentation packet in the trace.",
"VAALE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom the final level of the translation table walk, if TTL[3:2] is 0b00.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"IGDVAC" : "Invalidate data and Allocation Tags in data cache by address to Point of\nCoherency.",
"APIAKeyHi_EL1" : "Holds bits[127:64] of key A used for authentication of instruction pointer\nvalues.\nThe term APIAKey_EL1 is used to describe the concatenation of APIAKeyHi_EL1:\nAPIAKeyLo_EL1.",
"TRCAUXCTLR" : "The function of this register is implementation defined.",
"TRCEVENTCTL0R" : "Controls the generation of ETEEvents.",
"VAALE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from the final level of the translation\ntable walk.\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk, if TTL[3:2] is 0b00.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFrom Armv8.4, when a TLB maintenance instruction is generated to the Secure\nEL1&0 translation regime and is defined to pass a VMID argument, or would\nbe defined to pass a VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SCXTNUM_EL1" : "Provides a number that can be used to separate out different context numbers\nwith the EL1 exception level, for the purpose of protecting against side-channels\nusing branch prediction and similar resources.",
"VAE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry.\nA 64-bit stage 1 translation table entry, if TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA, and one of the following\napplies:\nThe entry is from a level of lookup above the final level and matches the\nspecified ASID.\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFrom Armv8.4, when a TLB maintenance instruction is generated to the Secure\nEL1&0 translation regime and is defined to pass a VMID argument, or would\nbe defined to pass a VMID argument if SCR_EL3.EEL2==1, then:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"RVALE2OS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any VA in the range determined by\nthe formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]\nusing the EL2 or EL2&0 translation regime, as determined by the Effective\nvalue of HCR_EL2.E2H, for the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from the final\nlevel of the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"DAIF" : "Allows access to the interrupt mask bits.",
"VALE3IS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following\nA 128-bit stage 1 translation table entry, from the final level of the translation\ntable walk.\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk, if TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL3 translation\nregime.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TRCVISSCTLR" : "Use this to select, or read, the Single Address Comparators for the ViewInst\nstart/stop function.",
"PMINTENSET_EL1" : "Allows software to enable the generation of interrupt requests or, when\nFEAT_EBEP is implemented, PMU exceptions on overflows from the following\ncounters:\nReading from this register shows which overflow interrupt requests or PMU\nexceptions are enabled.",
"TFSRE0_EL1" : "Holds accumulated Tag Check Faults occurring in EL0 that are not taken precisely.",
"ICV_EOIR1_EL1" : "A PE writes to this register to inform the CPU interface that it has completed\nthe processing of the specified virtual Group 1 interrupt.",
"POR_EL2" : "Stage 1 Permission Overlay Register for privileged access of the EL2 or\nEL2&0 translation regime.",
"GCSCR_EL2" : "Controls the Guarded Control Stack at EL2.",
"APIBKeyLo_EL1" : "Holds bits[63:0] of key B used for authentication of instruction pointer\nvalues.\nThe term APIBKey_EL1 is used to describe the concatenation of APIBKeyHi_EL1:\nAPIBKeyLo_EL1.",
"SCXTNUM_EL0" : "Provides a number that can be used to separate out different context numbers\nwith the EL0 exception level, for the purpose of protecting against side-channels\nusing branch prediction and similar resources.",
"TPIDR_EL1" : "Provides a location where software executing at EL1 can store thread identifying\ninformation, for OS management purposes.\nThe PE makes no use of this register.",
"CNTHPS_CVAL_EL2" : "Holds the compare value for the Secure EL2 physical timer.",
"SVCR" : "Controls Streaming SVE mode and SME behavior.",
"ASIDE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 translation table entry.\nThe entry would be used for the specified ASID, and either:\nIs from a level of lookup above the final level.\nIs a non-global entry from the final level of lookup.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate an address using the EL1&0 translation\nregime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"RVALE2" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, if TTL is 0b00.\nThe entry would be used to translate any VA in the range determined by\nthe formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]\nusing the EL2 or EL2&0 translation regime, as determined by the Effective\nvalue of HCR_EL2.E2H, for the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from the final\nlevel of the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"HFGITR2_EL2" : "Provides instruction trap controls.",
"VAAE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom any level of the translation table walk, if TTL[3:2] is 0b00.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFrom Armv8.4, when a TLB maintenance instruction is generated to the Secure\nEL1&0 translation regime and is defined to pass a VMID argument, or would\nbe defined to pass a VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"AMAIR_EL1" : "Provides implementation defined memory attributes for the memory regions\nspecified by MAIR_EL1.",
"LORC_EL1" : "Enables and disables LORegions, and selects the current LORegion descriptor.",
"MPAM2_EL2" : "Holds information to generate MPAM labels for memory requests when executing\nat EL2.",
"PMSFCR_EL1" : "Controls sample filtering. The filter is the logical AND of the FL, FT and\nFE bits. For example, if FE == 1 and FT == 1 only samples including the\nselected operation types and the selected events will be recorded",
"IALLUIS" : "Invalidate all instruction caches in the Inner Shareable domain of the PE\nexecuting the instruction to the Point of Unification.",
"RVALE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange, and one of the following applies:\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VAE2OS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry.\nA 64-bit stage 1 translation table entry, if TTL[3:2] is 0b00.\nThe entry would be required to translate the specified VA using the EL2\nor EL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H,\nfor the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from any level\nof the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is from a level of the translation table walk above the final\nlevel and matches the specified ASID.\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"IALLU" : "Invalidate all instruction caches of the PE executing the instruction to\nthe Point of Unification.",
"S1E0W" : "Performs stage 1 address translation from EL0, with permissions as if writing\nto the given virtual address from EL0, using the following translation\nregime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"RVAE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange, and one of the following applies:\nThe entry is from a level of lookup above the final level and matches the\nspecified ASID.\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:",
"SPSR_EL3" : "Holds the saved process state when an exception is taken to EL3.",
"S1E2A" : "Performs stage 1 address translation as defined for EL2, while ignoring\npermissions checks from the given virtual address.\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"RVAAE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom any level of the translation table walk, if TTL is 0b00.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TTBR1_EL1" : "Holds the base address of the translation table for the initial lookup for\nstage 1 of the translation of an address from the higher VA range in the\nEL1&0 stage 1 translation regime, and other information for this translation\nregime.",
"PAALLOS" : "Invalidates cached copies of GPT entries from TLBs. Details:\nThe invalidation applies to TLB entries containing GPT information that\nrelates to a physical address.\nThe invalidation applies to all TLB entries containing GPT information.\nThe invalidation affects all TLBs in the Outer Shareable domain.\nThe full set of TLB maintenance instructions that invalidate cached GPT\nentries is: TLBI PAALL, TLBI PAALLOS, TLBI RPALOS, and TLBI RPAOS.\nThese instructions have the same ordering, observability, and completion\nbehavior as all other TLBI instructions.",
"PMCR_EL0" : "Provides details of the Performance Monitors implementation, including the\nnumber of counters implemented, and configures and controls the counters.",
"ACTLR_EL1" : "Provides implementation defined configuration and control options for execution\nat EL1 and EL0.\nArm recommends the contents of this register have no effect on the PE when\nthe Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, and instead the configuration\nand control fields are provided by the ACTLR_EL2 register. This avoids\nthe need for software to manage the contents of these register when switching\nbetween a Guest OS and a Host OS.",
"HPFAR_EL2" : "Holds the faulting IPA for some aborts on a stage 2 translation taken to\nEL2.",
"CGDVAC" : "Clean data and Allocation Tags in data cache by address to Point of Coherency.",
"MDRAR_EL1" : "Defines the base physical address of a 4KB-aligned memory-mapped debug component,\nusually a ROM table that locates and describes the memory-mapped debug\ncomponents in the system. Armv8 deprecates any use of this register.",
"SPMACCESSR_EL3" : "Controls access to System PMUs from EL2, EL1 and EL0.",
"S12E0R" : "Performs stage 1 and 2 address translations from EL0, with permissions as\nif reading from the given virtual address from EL0, using the following\ntranslation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"ERXPFGCDN_EL1" : "Accesses ERR<n>PFGCDN for the error record <n> selected by ERRSELR_EL1.SEL.",
"ERXGSR_EL1" : "Shows the status for the records in a group of error records.\nAccesses ERRGSR for the group of error records <n> selected by ERRSELR_EL1.SEL[15:6].",
"ID_MMFR1_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch32 state.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"HDFGRTR_EL2" : "Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and\nStatistical Profiling System registers.",
"BRBFCR_EL1" : "Functional controls for the Branch Record Buffer.",
"CNTFRQ_EL0" : "This register is provided so that software can discover the frequency of\nthe system counter. It must be programmed with this value as part of system\ninitialization. The value of the register is not interpreted by hardware.",
"ERXPFGF_EL1" : "Accesses ERR<n>PFGF for the error record <n> selected by ERRSELR_EL1.SEL.",
"VTTBR_EL2" : "Holds the base address of the translation table for the initial lookup for\nstage 2 of an address translation in the EL1&0 translation regime, and\nother information for this translation regime.",
"CNTP_TVAL_EL0" : "Holds the timer value for the EL1 physical timer.",
"PMBLIMITR_EL1" : "Defines the upper limit for the profiling buffer, and enables the profiling\nbuffer",
"ZCR_EL1" : "This register controls aspects of SVE visible at Exception levels EL1 and\nEL0.",
"PMSCR_EL1" : "Provides EL1 controls for Statistical Profiling.",
"VMALLWS2E1OS" : "Invalidates stage 2 write permissions from cached copies of translation\ntable entries from TLBs that meet all the following requirements:\nThe entry would be used for stage 2 translation. This applies if the TLB\nentry holds information from stage 2 translation only, or combined information\nfrom stage 1 and stage 2 translation.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SPMACCESSR_EL1" : "Controls access to System PMUs from EL0.",
"ICC_SGI1R_EL1" : "Generates Group 1 SGIs for the current Security state.",
"ID_AA64FPFR0_EL1" : "Provides information about the FP8 formats and instructions implemented\nin AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"TRCIDR3" : "Returns the base architecture of the trace unit.",
"ICV_RPR_EL1" : "Indicates the Running priority of the virtual CPU interface.",
"IPAS2E1" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 2 only translation table entry, from any level of the translation\ntable walk.\nA 64-bit stage 2 only translation table entry, from any level of the translation\ntable walk, if TTL[3:2] is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to the PE that executes this System instruction.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SMPRI_EL1" : "Configures the streaming execution priority for instructions executed on\na shared Streaming Mode Compute Unit (SMCU) when the PE is in Streaming\nSVE mode at any Exception level.",
"IPAS2LE1IS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from the final level of the\ntranslation table walk.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom the final level of the translation table walk, if TTL[3:2] is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TRCIDR7" : "Returns the tracing capabilities of the trace unit.",
"ID_AA64ISAR2_EL1" : "Provides information about the features and instructions implemented in\nAArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"ID_AA64MMFR0_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"SPMZR_EL0" : "Zero the set of System PMU event counters specified by the mask written\nto SPMZR_EL0.",
"ICC_CTLR_EL3" : "Controls aspects of the behavior of the GIC CPU interface and provides information\nabout the features implemented.",
"PMSDSFR_EL1" : "Controls sample filtering by Data Source.",
"TRCQCTLR" : "Controls when Q elements are enabled.",
"GCSCRE0_EL1" : "Controls the Guarded Control Stack at EL0.",
"S1E1WP" : "Performs a stage 1 address translation, where the value of PSTATE.PAN determines\nif a write to a location will generate a Permission fault for a privileged\naccess, using the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"RVAE3IS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange using the EL3 translation regime.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"DBGPRCR_EL1" : "Controls behavior of the PE on powerdown request.",
"SPSR_und" : "Holds the saved process state when an exception is taken to Undefined mode.",
"ICV_IAR0_EL1" : "The PE reads this register to obtain the INTID of the signaled virtual Group\n0 interrupt. This read acts as an acknowledge for the interrupt.",
"APGAKeyHi_EL1" : "Holds bits[127:64] of key used for generic pointer authentication code.\nThe term APGAKey_EL1 is used to describe the concatenation of APGAKeyHi_EL1:\nAPGAKeyLo_EL1.",
"CGVAC" : "Clean Allocation Tags in data cache by address to Point of Coherency.",
"ICV_DIR_EL1" : "When interrupt priority drop is separated from interrupt deactivation, a\nwrite to this register deactivates the specified virtual interrupt.",
"S2PIR_EL2" : "Stage 2 Permission Indirection Register for EL1&0 translation regime.",
"RIPAS2LE1IS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 2 only translation table entry, from the leaf level of the\ntranslation table walk, indicated by the TTL hint.\nIf FEAT_D128 is implemented, a 64-bit stage 2 only translation table entry,\nfrom the leaf level of the translation table walk, if TTL is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VMALLE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"CLIDR_EL1" : "Identifies the type of cache, or caches, that are implemented at each level\nand can be managed using the architected cache maintenance instructions\nthat operate by set/way, up to a maximum of seven levels. Also identifies\nthe Level of Coherence (LoC) and Level of Unification (LoU) for the cache\nhierarchy.",
"ALLE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 or stage 2 translation table entry, from any level\nof the translation table walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to entries with any VMID.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ICV_PMR_EL1" : "Provides a virtual interrupt priority filter. Only virtual interrupts with\na higher priority than the value in this register are signaled to the PE.",
"VALE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA, and one of the following\napplies:\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFrom Armv8.4, when a TLB maintenance instruction is generated to the Secure\nEL1&0 translation regime and is defined to pass a VMID argument, or would\nbe defined to pass a VMID argument if SCR_EL3.EEL2==1, then:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ID_ISAR3_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR4_EL1,\nand ID_ISAR5_EL1. \nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"CPTR_EL3" : "Controls trapping to EL3 of accesses to CPACR, CPACR_EL1, HCPTR, CPTR_EL2,\ntrace, Activity Monitor, SME, Streaming SVE, SVE, and Advanced SIMD\nand floating-point functionality.",
"MDSTEPOP_EL1" : "Used to execute instructions while Software Step is in active-not-pending\nstate.",
"FPEXC32_EL2" : "Allows access to the AArch32 register FPEXC from AArch64 state only. Its\nvalue has no effect on execution in AArch64 state.",
"RVAALE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the leaf level of the translation\ntable walk, indicated by the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom the leaf level of the translation table walk, if TTL is 0b00.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMCNTENCLR_EL0" : "Allows software to disable the following counters:\nReading from this register shows which counters are enabled.",
"IVAU" : "Invalidate instruction cache by address to Point of Unification.",
"PMSICR_EL1" : "Software must write zero to PMSICR_EL1 before enabling sample profiling\nfor a sampling session. Software must then treat PMSICR_EL1 as an opaque,\n64-bit, read/write register used for context switches only.",
"ICC_PMR_EL1" : "Provides an interrupt priority filter. Only interrupts with a higher priority\nthan the value in this register are signaled to the PE.\nWrites to this register must be high performance and must ensure that no\ninterrupt of lower priority than the written value occurs after the write,\nwithout requiring an ISB or an exception boundary.",
"ICV_HPPIR1_EL1" : "Indicates the highest priority pending virtual Group 1 interrupt on the\nvirtual CPU interface.",
"TRCOSLSR" : "Returns the status of the Trace OS Lock.",
"IPAS2LE1OS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from the final level of the\ntranslation table walk.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom the final level of the translation table walk, if TTL[3:2] is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ICC_RPR_EL1" : "Indicates the Running priority of the CPU interface.",
"TRCEVENTCTL1R" : "Controls the behavior of the ETEEvents that TRCEVENTCTL0R selects.",
"MPAMVPM7_EL2" : "MPAMVPM7_EL2 provides mappings from virtual PARTIDs 28 - 31 to physical\nPARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2\nregisters. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs.\nIf MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register,\nMPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"HDBSSPROD_EL2" : "Allows producer to update write index for HDBSS.",
"SPMDEVARCH_EL1" : "Provides discovery information for System PMU <s>.",
"ID_AA64DFR1_EL1" : "Provides top level information about the debug system in AArch64.",
"TRCIDR6" : "Returns the tracing capabilities of the trace unit.",
"ESR_EL1" : "Holds syndrome information for an exception taken to EL1.",
"ICC_EOIR0_EL1" : "A PE writes to this register to inform the CPU interface that it has completed\nthe processing of the specified Group 0 interrupt.",
"RMR_EL1" : "When this register is implemented:",
"VAE3IS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk.\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk, if TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL3 translation\nregime.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VAAE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk.\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk, if TTL[3:2] is 0b00.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ICC_IGRPEN1_EL3" : "Controls whether Group 1 interrupts are enabled or not.",
"TRCIMSPEC0" : "TRCIMSPEC0 shows the presence of any implementation defined features, and\nprovides an interface to enable the features that are provided.",
"TRCIDR11" : "Returns the tracing capabilities of the trace unit.",
"RVAE2IS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, if TTL is 0b00.\nThe entry would be used to translate any VA in the range determined by\nthe formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]\nusing the EL2 or EL2&0 translation regime, as determined by the Effective\nvalue of HCR_EL2.E2H, for the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from any level\nof the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is from a level of the translation table walk above the final\nlevel and matches the specified ASID.\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VBAR_EL1" : "Holds the vector base address for any exception that is taken to EL1.",
"ALLE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 or stage 2 translation table entry, from any level\nof the translation table walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to entries with any VMID.\nThe invalidation only applies to the PE that executes this System instruction.\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"AFSR0_EL3" : "Provides additional implementation defined fault status information for\nexceptions taken to EL3.",
"AFSR0_EL2" : "Provides additional implementation defined fault status information for\nexceptions taken to EL2.",
"TRCDEVARCH" : "Provides discovery information for the component.\nFor additional information, see the CoreSight Architecture Specification.",
"OSDLR_EL1" : "Used to control the OS Double Lock.",
"ICV_EOIR0_EL1" : "A PE writes to this register to inform the CPU interface that it has completed\nthe processing of the specified virtual Group 0 interrupt.",
"HFGWTR_EL2" : "Provides controls for traps of MSRR, MSR and MCR writes of System registers.",
"CNTHCTL_EL2" : "Controls the generation of an event stream from the physical counter, and\naccess from EL1 to the physical counter and the EL1 physical timer.",
"LORSA_EL1" : "Indicates whether the current LORegion descriptor selected by LORC_EL1.DS\nis enabled, and holds the physical address of the start of the LORegion.",
"POR_EL0" : "Stage 1 Permission Overlay Register for unprivileged access of EL1&0 or\nEL2&0 translation regime.",
"VALE2" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL2 or\nEL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H,\nfor the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from the final\nlevel of the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VBAR_EL3" : "Holds the vector base address for any exception that is taken to EL3.",
"TPIDR_EL0" : "Provides a location where software executing at EL0 can store thread identifying\ninformation, for OS management purposes.\nThe PE makes no use of this register.",
"TRCIDR13" : "Returns the tracing capabilities of the trace unit.",
"ESR_EL3" : "Holds syndrome information for an exception taken to EL3.",
"ICH_ELRSR_EL2" : "These registers can be used to locate a usable List register when the hypervisor\nis delivering an interrupt to a VM.",
"PFAR_EL1" : "Records the faulting physical address for a synchronous External abort,\nor SError exception taken to EL1.",
"RVAE2OS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any VA in the range determined by\nthe formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]\nusing the EL2 or EL2&0 translation regime, as determined by the Effective\nvalue of HCR_EL2.E2H, for the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from any level\nof the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is from a level of the translation table walk above the final\nlevel and matches the specified ASID.\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMICNTR_EL0" : "If event counting is not prohibited and the instruction counter is enabled,\nthe counter increments for each architecturally-executed instruction, according\nto the configuration specified by PMICFILTR_EL0.",
"AMCG1IDR_EL0" : "Defines which auxiliary counters are implemented, and which of them have\na corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.",
"TTBR1_EL2" : "When the Effective value of HCR_EL2.E2H is 1, holds the base address of\nthe translation table for the initial lookup for stage 1 of the translation\nof an address from the higher VA range in the EL2&0 translation regime,\nand other information for this translation regime.\nWhen the Effective value of HCR_EL2.E2H is not 1, the contents of this register\nare ignored by the PE, except for a direct read or write of the register.",
"ID_AFR0_EL1" : "Provides information about the implementation defined features of the PE\nin AArch32 state.\nMust be interpreted with the Main ID Register, MIDR_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"VALE3OS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL3 translation\nregime.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMOVSSET_EL0" : "Allows software to set the unsigned overflow flags for the following counters\nto 1:\nReading from this register shows the current unsigned overflow flag values.",
"ICV_IAR1_EL1" : "The PE reads this register to obtain the INTID of the signaled virtual Group\n1 interrupt. This read acts as an acknowledge for the interrupt.",
"ACTLR_EL3" : "Provides implementation defined configuration and control options for EL3.",
"CNTPCTSS_EL0" : "Holds the self-synchronized view of the 64-bit physical count value.",
"CIPAE" : "Data or unified Cache line Clean and Invalidate by PA to PoE.",
"GZVA" : "Zero data and write a value to the Allocation Tags of a naturally aligned\nblock of N bytes, where the size of N is identified in DCZID_EL0. The\nAllocation Tag used is determined by the input address.",
"MDSELR_EL1" : "Selects the current breakpoints or watchpoints accessed by System register\ninstructions.",
"ICC_IAR0_EL1" : "The PE reads this register to obtain the INTID of the signaled Group 0 interrupt.\nThis read acts as an acknowledge for the interrupt.",
"MAIR_EL1" : "Provides the memory attribute encodings corresponding to the possible AttrIndx\nvalues in a Long-descriptor format translation table entry for stage 1\ntranslations at EL1.",
"APIAKeyLo_EL1" : "Holds bits[63:0] of key A used for authentication of instruction pointer\nvalues.\nThe term APIAKey_EL1 is used to describe the concatenation of APIAKeyHi_EL1:\nAPIAKeyLo_EL1.",
"RVALE3IS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following\nA 128-bit stage 1 translation table entry, from the final level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk, if TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange using the EL3 translation regime.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PIR_EL1" : "Stage 1 Permission Indirection Register for privileged access of the EL1&0\ntranslation regime.",
"PMMIR_EL1" : "Describes Performance Monitors parameters specific to the implementation\nto software.",
"TRCVMIDCCTLR0" : "Virtual Context Identifier Comparator mask values for the TRCVMIDCVR<n>\nregisters, where n=0-3.",
"TCR2_EL2" : "The control register for stage 1 of the EL2&0 translation regime.",
"BRBCR_EL2" : "Controls the Branch Record Buffer.",
"AMUSERENR_EL0" : "Global user enable register for the activity monitors. Enables or disables\nEL0 access to the activity monitors. AMUSERENR_EL0 is applicable to both\nthe architected and the auxiliary counter groups.",
"VSESR_EL3" : "Provides the syndrome value reported to software when the Effective value\nof SCR_EL3.DSE is 1 on taking a delegated SError exception to EL2 or EL1,\nor on executing an ESB instruction at EL2 or EL1.\nWhen the delegated SError exception injected using SCR_EL3.DSE is taken\nto EL2 using AArch64, then the syndrome value is reported in ESR_EL2.\nWhen the delegated SError exception injected using SCR_EL3.DSE is taken\nto EL1 using AArch64, then the syndrome value is reported in ESR_EL1.\nWhen the delegated SError exception injected using SCR_EL3.DSE is deferred\nby an ESB instruction, then the syndrome value is written to VDISR_EL3.",
"TRCCIDCCTLR1" : "Contains Context identifier mask values for the TRCCIDCVR<n> registers,\nfor n = 4 to 7.",
"SPMSCR_EL1" : "Controls observability of Secure events by System PMU <s>, and optionally\ncontrols Secure attributes for message signaled interrupts and Non-secure\naccess to the performance monitor registers.",
"RVALE3" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange using the EL3 translation regime.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"DBGDTR_EL0" : "Transfers 64 bits of data between the PE and an external debugger. Can transfer\nboth ways using only a single register.",
"CNTVCTSS_EL0" : "Reads of CNTVCTSS_EL0 return the 64-bit physical count value minus a virtual\noffset.",
"MPAMSM_EL1" : "Holds information to generate MPAM labels for memory requests that are:\nIf an implementation uses a shared SMCU, then the MPAM labels in this register\nhave precedence over the labels in MPAM0_EL1, MPAM1_EL1, MPAM2_EL2, and\nMPAM3_EL3.\nIf an implementation includes an SMCU that is not shared with other PEs,\nthen it is implementation defined whether the MPAM labels in this register\nhave precedence over the labels in MPAM0_EL1, MPAM1_EL1, MPAM2_EL2, and\nMPAM3_EL3.\nThe MPAM labels in this register are only used if MPAM1_EL1.MPAMEN is 1.\n\nFor memory requests issued from EL0, the MPAM PARTID in this register is\nvirtual and mapped into a physical PARTID when all of the following are\ntrue:\nFor memory requests issued from EL1, the MPAM PARTID in this register is\nvirtual and mapped into a physical PARTID when all of the following are\ntrue:",
"SCXTNUM_EL3" : "Provides a number that can be used to separate out different context numbers\nwith the EL3 exception level, for the purpose of protecting against side-channels\nusing branch prediction and similar resources.",
"CVAC" : "Clean data cache by address to Point of Coherency.",
"ICH_MISR_EL2" : "Indicates which maintenance interrupts are asserted.",
"HFGITR_EL2" : "Provides instruction trap controls.",
"TRCSTATR" : "Returns the trace unit status.",
"RVALE3OS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange using the EL3 translation regime.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VSESR_EL2" : "Provides the syndrome value reported to software on taking a virtual SError\nexception to EL1, or on executing an ESB instruction at EL1.\nWhen the virtual SError exception injected using HCR_EL2.VSE is taken to\nEL1 using AArch64, then the syndrome value is reported in ESR_EL1.\nWhen the virtual SError exception injected using HCR_EL2.VSE is taken to\nEL1 using AArch32, then the syndrome value is reported in DFSR.{AET, ExT}\nand the remainder of DFSR is set as defined by VMSAv8-32. For more information,\nsee The AArch32 Virtual Memory System Architecture.\nWhen the virtual SError exception injected using HCR_EL2.VSE is deferred\nby an ESB instruction, then the syndrome value is written to VDISR_EL2.",
"CGDVADP" : "Clean Allocation Tags and data in data cache by address to Point of Deep\nPersistence.\nIf the memory system does not identify a Point of Deep Persistence, then\nthis instruction behaves as a DC CGDVAP.",
"GMID_EL1" : "Indicates the block size that is accessed by the LDGM and STGM System instructions.",
"PMCEID0_EL0" : "Defines which Common architectural events and Common microarchitectural\nevents are implemented, or counted, using PMU events in the ranges 0x0000\nto 0x001F and 0x4000 to 0x401F.\nFor more information about the Common events and the use of the PMCEID<n>_EL0\nregisters see 'The PMU event number space and common events'.",
"IFSR32_EL2" : "Allows access to the AArch32 IFSR register from AArch64 state only. Its\nvalue has no effect on execution in AArch64 state.",
"TPIDR_EL2" : "Provides a location where software executing at EL2 can store thread identifying\ninformation, for OS management purposes.\nThe PE makes no use of this register.",
"CNTHPS_TVAL_EL2" : "Holds the timer value for the Secure EL2 physical timer.",
"ID_AA64SMFR0_EL1" : "Provides information about the implemented features of the AArch64 Scalable\nMatrix Extension.\nThe fields in this register do not follow the standard ID scheme. See 'Alternative\nID scheme used for ID_AA64SMFR0_EL1'.",
"ICV_IGRPEN0_EL1" : "Controls whether virtual Group 0 interrupts are enabled or not.",
"LORID_EL1" : "Indicates the number of LORegions and LORegion descriptors supported by\nthe PE.",
"PMICFILTR_EL0" : "Configures the Instruction Counter.",
"MVFR1_EL1" : "Describes the features provided by the AArch32 Advanced SIMD and Floating-point\nimplementation.\nMust be interpreted with MVFR0_EL1 and MVFR2_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"VAALE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from the final level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom the final level of the translation table walk, if TTL[3:2] is 0b00.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ERXFR_EL1" : "Accesses ERR<n>FR for the error record <n> selected by ERRSELR_EL1.SEL.",
"MPAMVPMV_EL2" : "Valid bits for virtual PARTID mapping entries. Each bit m corresponds to\nvirtual PARTID mapping entry m in the MPAMVPM<n>_EL2 registers where n\n= m >> 2.",
"ID_ISAR0_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1,\nand ID_ISAR5_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"SPMCNTENCLR_EL0" : "Disable event counters in System PMU <s>.",
"CVAP" : "Clean data cache by address to Point of Persistence.\nIf the memory system does not identify a Point of Persistence, then this\ninstruction behaves as a DC CVAC.",
"TRCIDR0" : "Returns the tracing capabilities of the trace unit.",
"GCSPR_EL2" : "Contains the Guarded Control Stack Pointer at EL2.",
"VPIDR_EL2" : "Holds the value of the Virtualization Processor ID. This is the value returned\nby EL1 reads of MIDR_EL1.",
"GCSPR_EL3" : "Contains the Guarded Control Stack Pointer at EL3.",
"PMCEID1_EL0" : "Defines which Common architectural events and Common microarchitectural\nevents are implemented, or counted, using PMU events in the ranges 0x0020\nto 0x003F and 0x4020 to 0x403F.\nFor more information about the Common events and the use of the PMCEID<n>_EL0\nregisters see 'The PMU event number space and common events'.",
"TCO" : "When FEAT_MTE is implemented, this register allows tag checks to be disabled\nglobally.\nWhen FEAT_MTE2 is not implemented, it is CONSTRAINED UNPREDICTABLE whether\nthis register is RES0 or behaves as if FEAT_MTE2 is implemented.",
"OSLAR_EL1" : "Used to lock or unlock the OS Lock.",
"VDISR_EL2" : "Records that a virtual SError exception has been consumed by an ESB instruction\nexecuted at EL1.\nAn indirect write to VDISR_EL2 made by an ESB instruction does not require\nan explicit synchronization operation for the value written to be observed\nby a direct read of one of the following registers occurring in program\norder after the ESB instruction:",
"MECID_A0_EL2" : "Alternate MECID for EL2 and EL2&0 accesses translated by TTBR0_EL2.",
"CNTKCTL_EL1" : "When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this register\ndoes not cause any event stream from the virtual counter to be generated,\nand does not control access to the counters and timers. The access to counters\nand timers at EL0 is controlled by CNTHCTL_EL2.\nWhen FEAT_VHE is not implemented, or when the Effective value of HCR_EL2.{E2H,\nTGE} is not {1, 1}, this register controls the generation of an event stream\nfrom the virtual counter, and access from EL0 to the physical counter,\nvirtual counter, EL1 physical timers, and the virtual timer.",
"GCSPR_EL0" : "Contains the Guarded Control Stack Pointer at EL0.",
"DBGCLAIMCLR_EL1" : "Used by software to read the values of the CLAIM tag bits, and to clear\nCLAIM tag bits to 0.\nThe architecture does not define any functionality for the CLAIM tag bits.\nCLAIM tags are typically used for communication between the debugger and\ntarget software.\nUsed in conjunction with the DBGCLAIMSET_EL1 register.",
"TRCAUTHSTATUS" : "Provides information about the state of the implementation defined authentication\ninterface for debug.\nFor additional information, see the CoreSight Architecture Specification.",
"ICV_HPPIR0_EL1" : "Indicates the highest priority pending virtual Group 0 interrupt on the\nvirtual CPU interface.",
"MECID_A1_EL2" : "Alternate MECID for EL2&0 accesses translated by TTBR1_EL2.",
"VAE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA, and one of the following\napplies:\nThe entry is from a level of lookup above the final level and matches the\nspecified ASID.\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VMALLWS2E1" : "Invalidates stage 2 write permissions from cached copies of translation\ntable entries from TLBs that meet all the following requirements:\nThe entry would be used for stage 2 translation. This applies if the TLB\nentry holds information from stage 2 translation only, or combined information\nfrom stage 1 and stage 2 translation.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"DSPSR_EL0" : "Holds the saved process state for Debug state. On entering Debug state,\nPSTATE information is written to this register. On exiting Debug state,\nvalues are copied from this register to PSTATE.",
"POR_EL3" : "Stage 1 Permission Overlay Register for privileged access of the EL3 translation\nregime.",
"TRCTRACEIDR" : "Sets the trace ID for instruction trace.",
"ICV_NMIAR1_EL1" : "The PE reads this register to obtain the INTID of the signaled virtual Group\n1 interrupt. This read acts as an acknowledge for the interrupt.",
"ID_AA64MMFR2_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"ICV_BPR1_EL1" : "Defines the point at which the priority value fields split into two parts,\nthe group priority field and the subpriority field. The group priority\nfield determines virtual Group 1 interrupt preemption.",
"RVAAE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk, if TTL is 0b00.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"GPCCR_EL3" : "The control register for Granule Protection Checks.",
"SCTLR2_EL2" : "Provides top level control of the system, including its memory system, at\nEL2.\nWhen the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, these controls\nalso apply to execution at EL0.",
"CNTV_CTL_EL0" : "Control register for the virtual timer.",
"ICC_IGRPEN1_EL1" : "Controls whether Group 1 interrupts are enabled for the current Security\nstate.",
"TRBIDR_EL1" : "Describes constraints on using the Trace Buffer Unit to software, including\nwhether the Trace Buffer Unit can be programmed at the current Exception\nlevel.",
"ID_PFR0_EL1" : "Gives top-level information about the instruction sets supported by the\nPE in AArch32 state.\nMust be interpreted with ID_PFR1_EL1.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"CNTHVS_CVAL_EL2" : "Holds the compare value for the Secure EL2 virtual timer.",
"GCSPOPX" : "Loads an exception return record from the location indicated by the current\nGuarded Control Stack Pointer register, checks that the record is a Guarded\nControl Stack exception return record, and increments the current Guarded\nControl Stack Pointer register by the size of a Guarded Control Stack exception\nreturn record.",
"ZCR_EL3" : "This register controls aspects of SVE visible at all Exception levels.",
"VMALLE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFrom Armv8.4, when a TLB maintenance instruction is generated to the Secure\nEL1&0 translation regime and is defined to pass a VMID argument, or would\nbe defined to pass a VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMCCNTR_EL0" : "Holds the value of the processor Cycle Counter, CCNT, that counts processor\nclock cycles. See 'Time as measured by the Performance Monitors cycle counter'\nfor more information.\nPMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can\nincrement.",
"CSW" : "Clean data cache by set/way.",
"CIPAPA" : "Clean and Invalidate data cache by physical address to the Point of Physical\nAliasing.\nThis instruction cleans and invalidates all copies of the Location specified\nin the Xt argument, irrespective of any MECID associated with the Location.\nMemory accesses resulting from the Clean operation use the MECID associated\nwith the cache entry.",
"VSTCR_EL2" : "The control register for stage 2 of the Secure EL1&0 translation regime.",
"ID_AA64ISAR0_EL1" : "Provides information about the instructions implemented in AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"SMCR_EL1" : "This register controls aspects of Streaming SVE that are visible at Exception\nlevels EL1 and EL0.",
"SPMROOTCR_EL3" : "Controls observability of Root and Realm events by System PMU <s>.",
"MPAMVPM6_EL2" : "MPAMVPM6_EL2 provides mappings from virtual PARTIDs 24 - 27 to physical\nPARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2\nregisters. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs.\nIf MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register,\nMPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"OSECCR_EL1" : "Provides a mechanism for an operating system to access the contents of EDECCR\nthat are otherwise invisible to software, so it can save/restore the contents\nof EDECCR over powerdown on behalf of the external debugger.",
"TRCRSR" : "Use this to set, or read, the status of the resources.",
"SCXTNUM_EL2" : "Provides a number that can be used to separate out different context numbers\nwith the EL2 exception level, for the purpose of protecting against side-channels\nusing branch prediction and similar resources.",
"CTR_EL0" : "Provides information about the architecture of the caches.",
"TRBSR_EL1" : "Provides syndrome information to software for a trace buffer management\nevent.",
"CPTR_EL2" : "Controls trapping to EL2 of accesses to CPACR, CPACR_EL1, trace, Activity\nMonitor, SME, Streaming SVE, SVE, and Advanced SIMD and floating-point\nfunctionality.",
"TTBR0_EL1" : "Holds the base address of the translation table for the initial lookup for\nstage 1 of the translation of an address from the lower VA range in the\nEL1&0 translation regime, and other information for this translation regime.",
"HDBSSBR_EL2" : "Control register for HDBSS base address.",
"HSTR_EL2" : "Controls trapping to EL2 of EL1 or lower AArch32 accesses to the System\nregister in the coproc == 0b1111 encoding space, by the CRn value used\nto access the register using MCR or MRC instruction. When the register\nis accessible using an MCRR or MRRC instruction, this is the CRm value\nused to access the register.",
"SPMOVSSET_EL0" : "Sets the state of overflow bits for event counters in System PMU <s>.",
"ICC_SGI0R_EL1" : "Generates Secure Group 0 SGIs.",
"ALLE2OS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TRCCONFIGR" : "Controls the tracing options.",
"TRCIDR4" : "Returns the tracing capabilities of the trace unit.",
"SMCR_EL3" : "This register controls aspects of Streaming SVE that are visible at all\nException levels.",
"CNTP_CVAL_EL0" : "Holds the compare value for the EL1 physical timer.",
"TRFCR_EL2" : "Provides EL2 controls for Trace.",
"GCSCR_EL1" : "Controls the Guarded Control Stack at EL1.",
"ICC_IGRPEN0_EL1" : "Controls whether Group 0 interrupts are enabled or not.",
"TRCIDR12" : "Returns the tracing capabilities of the trace unit.",
"ICC_SRE_EL3" : "Controls whether the System register interface or the memory-mapped interface\nto the GIC CPU interface is used for EL3.",
"TRBMAR_EL1" : "Controls Trace Buffer Unit accesses to memory.\nIf the trace buffer pointers specify virtual addresses, the address properties\nare defined by the translation tables and this register is ignored.",
"CVADP" : "Clean data cache by address to Point of Deep Persistence.\nIf the memory system does not identify a Point of Deep Persistence, then\nthis instruction behaves as a DC CVAP.",
"CGSW" : "Clean Allocation Tags in data cache by set/way.",
"RNDRRS" : "Random Number with fresh full entropy. Returns a 64-bit random number from\nan approved Random Bit Generator, using either a Non-deterministic Random\nBit Generator or one where the Deterministic Random Bit Generator is reseeded,\nwhere possible, from an approved entropy source before the return of the\nrandom number. See 'Properties of the generated random number'.\nIf the hardware returns a genuine random number, PSTATE.NZCV is set to 0b0000.\nIf the instruction cannot return a genuine random number in a reasonable\nperiod of time, PSTATE.NZCV is set to 0b0100 and the data value returned\nis 0.\nWhen FEAT_RNG_TRAP is implemented and SCR_EL3.TRNDR is 1, reads of this\nregister are trapped to EL3.",
"MPAMVPM3_EL2" : "MPAMVPM3_EL2 provides mappings from virtual PARTIDs 12 - 15 to physical\nPARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2\nregisters. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs.\nIf MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register,\nMPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"RMR_EL2" : "When this register is implemented:",
"DIT" : "Allows access to the Data Independent Timing bit.",
"AMCNTENCLR1_EL0" : "Disable control bits for the auxiliary activity monitors event counters,\nAMEVCNTR1<n>_EL0.",
"HCR_EL2" : "Provides configuration controls for virtualization, including defining whether\nvarious operations are trapped to EL2.",
"ID_AA64DFR0_EL1" : "Provides top level information about the debug system in AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"CNTHP_CTL_EL2" : "Control register for the EL2 physical timer.",
"PMSELR_EL0" : "Selects the current event counter PMEVCNTR<n>_EL1 or the cycle counter PMCCNTR.\nUsed in conjunction with PMXEVTYPER_EL0 to determine the event that increments\na selected counter, and the modes and states in which the selected counter\nincrements.\nUsed in conjunction with PMXEVCNTR_EL0 to determine the value of a selected\ncounter.",
"TRBMPAM_EL1" : "Defines the PARTID, PMG, and MPAM_SP values used by the trace buffer unit\nin external mode.",
"ID_AA64ISAR3_EL1" : "Provides information about the features and instructions implemented in\nAArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"SPMIIDR_EL1" : "Provides discovery information for System PMU <s>.",
"BRBIDR0_EL1" : "Indicates the features of the branch buffer unit.",
"IGVAC" : "Invalidate Allocation Tags in data cache by address to Point of Coherency.",
"APDBKeyHi_EL1" : "Holds bits[127:64] of key B used for authentication of data pointer values.\nThe term APDBKey_EL1 is used to describe the concatenation of APDBKeyHi_EL1:\nAPDBKeyLo_EL1.",
"POR_EL1" : "Stage 1 Permission Overlay Register for privileged access of the EL1&0 translation\nregime.",
"ID_AA64MMFR3_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch64 state.",
"RPAOS" : "Invalidates cached copies of GPT entries from TLBs. Details:\nThe invalidation applies to TLB entries containing GPT information that\nrelates to a physical address.\nThe invalidation affects all TLBs in the Outer Shareable domain.\nInvalidates TLB entries containing GPT information from all levels of the\nGPT walk that relates to the supplied physical address.\nInvalidations are range-based, invalidating TLB entries starting from the\naddress in BaseADDR, within the range as specified by SIZE.\nThe full set of TLB maintenance instructions that invalidate cached GPT\nentries is: TLBI PAALL, TLBI PAALLOS, TLBI RPALOS, and TLBI RPAOS.\nThese instructions have the same ordering, observability, and completion\nbehavior as all other TLBI instructions.",
"PIRE0_EL2" : "Stage 1 Permission Indirection Register for unprivileged access of the EL2&0\ntranslation regime.",
"DISR_EL1" : "Records that an SError exception has been consumed by an ESB instruction.",
"SP_EL3" : "Holds the stack pointer associated with EL3. When executing at EL3, the\nvalue of SPSel.SP determines the current stack pointer:",
"VSTTBR_EL2" : "The base register for stage 2 translation tables to translate Secure IPAs\nin the Secure EL1&0 translation regime. Holds the base address of the translation\ntable for the initial lookup for stage 2 of an address translation for\na Secure IPA in the Secure EL1&0 translation regime, and other information\nfor this translation stage.",
"ICC_HPPIR0_EL1" : "Indicates the highest priority pending Group 0 interrupt on the CPU interface.",
"CSSELR_EL1" : "Selects the current Cache Size ID Register, CCSIDR_EL1, by specifying the\nrequired cache level and the cache type (either instruction or data cache).",
"VBAR_EL2" : "Holds the vector base address for any exception that is taken to EL2.",
"BRBCR_EL1" : "Controls the Branch Record Buffer.",
"TCR_EL1" : "The control register for stage 1 of the EL1&0 translation regime.",
"VAE3" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL3 translation\nregime.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"RIPAS2LE1" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from the leaf level of the\ntranslation table walk, indicated by the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom the leaf level of the translation table walk, if TTL is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation only applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"S2POR_EL1" : "Stage 2 Permission Overlay Register for EL1&0 translation regime.",
"RVAE3OS" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk, if TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange using the EL3 translation regime.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ID_DFR0_EL1" : "Provides top level information about the debug system in AArch32 state.\nMust be interpreted with the Main ID Register, MIDR_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"ERXPFGCTL_EL1" : "Accesses ERR<n>PFGCTL for the error record <n> selected by ERRSELR_EL1.SEL.",
"SP_EL0" : "Holds the stack pointer associated with EL0. At higher Exception levels,\nthis is used as the current stack pointer when the value of SPSel.SP is\n0.",
"ALLE2IS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"SCTLR_EL2" : "Provides top-level control of the system, including its memory system, at\nEL2.\nWhen the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, these controls\napply also to execution at EL0.",
"CNTPOFF_EL2" : "Holds the 64-bit physical offset. This is the offset for the AArch64 physical\ntimers and counters when Enhanced Counter Virtualization is enabled.",
"MPAMVPM0_EL2" : "MPAMVPM0_EL2 provides mappings from virtual PARTIDs 0 - 3 to physical PARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2\nregister. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs.\nIf MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register,\nMPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"MPAMHCR_EL2" : "Controls the PARTID virtualization features of MPAM. It controls the mapping\nof virtual PARTIDs into physical PARTIDs in MPAM0_EL1 when EL0_VPMEN ==\n1 and in MPAM1_EL1 when EL1_VPMEN == 1.",
"RVALE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, if TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange, and one of the following applies:\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ICV_IGRPEN1_EL1" : "Controls whether virtual Group 1 interrupts are enabled for the current\nSecurity state.",
"ICH_EISR_EL2" : "Indicates which List registers have outstanding EOI maintenance interrupts.",
"ID_ISAR5_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,\nand ID_ISAR4_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"ID_AA64PFR2_EL1" : "Provides additional information about implemented PE features in AArch64\nstate.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"S1E3W" : "Performs stage 1 address translation as defined for EL3, with permissions\nas if writing to the given virtual address.",
"HFGRTR_EL2" : "Provides controls for traps of MRRS, MRS and MRC reads of System registers.",
"MECID_P0_EL2" : "Primary MECID for EL2 and EL2&0 accesses translated by TTBR0_EL2.",
"S1E1W" : "Performs stage 1 address translation, with permissions as if writing to\nthe given virtual address from EL1, or from EL2 if the Effective value\nof HCR_EL2.{E2H, TGE} is {1, 1}, using the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"RVBAR_EL3" : "If EL3 is the highest Exception level implemented, contains the implementation\ndefined address that execution starts from after reset when executing in\nAArch64 state.",
"TRCIDR9" : "Returns the tracing capabilities of the trace unit.",
"VMALLWS2E1IS" : "Invalidates stage 2 write permissions from cached copies of translation\ntable entries from TLBs that meet all the following requirements:\nThe entry would be used for stage 2 translation. This applies if the TLB\nentry holds information from stage 2 translation only, or combined information\nfrom stage 1 and stage 2 translation.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"TRBPTR_EL1" : "Defines the current write pointer for the trace buffer.",
"VDISR_EL3" : "Records that a delegated SError exception has been consumed by an ESB instruction\nexecuted at EL2 or EL1 when the Effective value of SCR_EL3.DSE is 1.\nAn indirect write to VDISR_EL3 made by an ESB instruction does not require\nan explicit synchronization operation for the value written to be observed\nby a direct read of DISR_EL1 occurring in program order after the ESB instruction.",
"SPMCNTENSET_EL0" : "Enables event counters in System PMU <s>.",
"GCSSS2" : "Validates that the most recent entry of the Guarded Control Stack that is\ngetting switched to contains an In-progress cap entry, stores a Valid cap\nentry to the Guarded Control Stack that is getting switched from, and sets\nXt to the address of that Valid cap entry.",
"PAALL" : "Invalidates cached copies of GPT entries from TLBs. Details:\nThe invalidation applies to TLB entries containing GPT information that\nrelates to a physical address.\nThe invalidation applies to all TLB entries containing GPT information.\nThe invalidation affects only the TLBs for the PE executing the operation.\nThe full set of TLB maintenance instructions that invalidate cached GPT\nentries is: TLBI PAALL, TLBI PAALLOS, TLBI RPALOS, and TLBI RPAOS.\nThese instructions have the same ordering, observability, and completion\nbehavior as all other TLBI instructions.",
"MPAM3_EL3" : "Holds information to generate MPAM labels for memory requests when executing\nat EL3.",
"AMCNTENSET0_EL0" : "Enable control bits for the architected activity monitors event counters,\nAMEVCNTR0<n>_EL0.",
"MAIR2_EL1" : "Provides the memory attribute encodings corresponding to the possible AttrIndx\nvalues in a VMSAv8-64 or VMSAv9-128 translation table entry for stage 1\ntranslations at EL1.",
"RVBAR_EL1" : "If EL1 is the highest Exception level implemented, contains the implementation\ndefined address that execution starts from after reset when executing in\nAArch64 state.",
"OSLSR_EL1" : "Provides the status of the OS Lock.",
"VALE2IS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA using the EL2 or\nEL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H,\nfor the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from the final\nlevel of the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMXEVTYPER_EL0" : "When PMSELR_EL0.SEL selects an event counter, this accesses a PMEVTYPER<n>_EL0\nregister. When PMSELR_EL0.SEL selects the cycle counter, this accesses\nPMCCFILTR_EL0.",
"S1E2W" : "Performs stage 1 address translation as defined for EL2, with permissions\nas if writing to the given virtual address.\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"ASIDE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 translation table entry.\nThe entry would be used for the specified ASID, and either:\nIs from a level of lookup above the final level.\nIs a non-global entry from the final level of lookup.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate an address using the EL1&0 translation\nregime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"HAFGRTR_EL2" : "Provides controls for traps of MRS reads of Activity Monitors System registers.",
"CIGDPAPA" : "Clean and Invalidate data and Allocation Tags in data cache by physical\naddress to the Point of Physical Aliasing.\nThis instruction cleans and invalidates all copies of the Location specified\nin the Xt argument, irrespective of any MECID associated with the Location.\nMemory accesses resulting from the Clean operation use the MECID associated\nwith the cache entry.",
"PMSWINC_EL0" : "Increments a counter that is configured to count the Software increment\nevent, event 0x00. For more information, see 'SW_INCR'.",
"SPSR_fiq" : "Holds the saved process state when an exception is taken to FIQ mode.",
"SDER32_EL2" : "Allows access to the AArch32 register SDER from Secure EL2 and EL3 only.",
"IVAC" : "Invalidate data cache by address to Point of Coherency.\nWhen FEAT_MTE2 is implemented, this instruction might invalidate Allocation\nTags from caches. When it invalidates Allocation Tags from caches, it also\ncleans them.",
"TPIDRRO_EL0" : "Provides a location where software executing at EL1 or higher can store\nthread identifying information that is visible to software executing at\nEL0, for OS management purposes.\nThe PE makes no use of this register.",
"TFSR_EL3" : "Holds accumulated Tag Check Faults occurring in EL3 that are not taken precisely.",
"TRCCLAIMCLR" : "In conjunction with TRCCLAIMSET, provides Claim Tag bits that can be separately\nset and cleared to indicate whether functionality is in use by a debug\nagent.\nFor additional information, see the CoreSight Architecture Specification.",
"RIPAS2E1" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom any level of the translation table walk, if TTL is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"AFSR1_EL1" : "Provides additional implementation defined fault status information for\nexceptions taken to EL1.",
"CNTHV_TVAL_EL2" : "Holds the timer value for the EL2 virtual timer.",
"PMSIRR_EL1" : "Defines the interval between samples.",
"TRCIDR1" : "Returns the tracing capabilities of the trace unit.",
"PMSEVFR_EL1" : "Controls sample filtering by events. The overall filter is the logical AND\nof these filters. For example, if PMSEVFR_EL1.E[3] and PMSEVFR_EL1.E[5]\nare both set to 1, only samples that have both event 3 (Level 1 unified\nor data cache refill) and event 5 (TLB walk) set to 1 are recorded.",
"IALL" : "Invalidates all Branch records in the Branch Record Buffer.",
"RGSR_EL1" : "Random Allocation Tag Seed Register.",
"HACDBSCONS_EL2" : "Read index for HACDBS structure.",
"PIR_EL3" : "Stage 1 Permission Indirection Register for privileged access of the EL3\ntranslation regime.",
"PMZR_EL0" : "Zero the set of counters specified by the mask written to PMZR_EL0.",
"S1E1R" : "Performs stage 1 address translation, with permissions as if reading from\nthe given virtual address from EL1, or from EL2 if the Effective value\nof HCR_EL2.{E2H, TGE} is {1, 1}, using the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"RMR_EL3" : "If EL3 is implemented and this register is implemented:",
"ICH_VMCR_EL2" : "Enables the hypervisor to save and restore the virtual machine view of the\nGIC state.",
"S1E2R" : "Performs stage 1 address translation as defined for EL2, with permissions\nas if reading from the given virtual address.\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"ERXSTATUS_EL1" : "Accesses ERR<n>STATUS for the error record <n> selected by ERRSELR_EL1.SEL.",
"CGDVAP" : "Clean data and Allocation Tags in data cache by address to Point of Persistence.\nIf the memory system does not identify a Point of Persistence, then this\ninstruction behaves as a DC CGDVAC.",
"ERXCTLR_EL1" : "Accesses ERR<n>CTLR for the error record <n> selected by ERRSELR_EL1.SEL.",
"S12E0W" : "Performs stage 1 and 2 address translations from EL0, with permissions as\nif writing to the given virtual address from EL0, using the following translation\nregime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"PMSLATFR_EL1" : "Controls sample filtering by latency",
"VNCR_EL2" : "When FEAT_NV2 is implemented, holds the base address that is used to define\nthe memory location that is accessed by transformed reads and writes of\nSystem registers.",
"ICC_CTLR_EL1" : "Controls aspects of the behavior of the GIC CPU interface and provides information\nabout the features implemented.",
"INJ" : "Injects the Branch Record held in BRBINFINJ_EL1, BRBSRCINJ_EL1, and BRBTGTINJ_EL1\ninto the Branch Record Buffer.",
"IPAS2LE1" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from the final level of the\ntranslation table walk.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom the final level of the translation table walk, if TTL[3:2] is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to the PE that executes this System instruction.\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ID_AA64ISAR1_EL1" : "Provides information about the features and instructions implemented in\nAArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"CNTVOFF_EL2" : "Holds the 64-bit virtual offset. This is the offset for the AArch64 virtual\ntimers and counters.",
"CNTHV_CVAL_EL2" : "Holds the compare value for the EL2 virtual timer.",
"ELR_EL3" : "When taking an exception to EL3, holds the address to return to.",
"MPAMVPM2_EL2" : "MPAMVPM2_EL2 provides mappings from virtual PARTIDs 8 - 11 to physical PARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM0_EL2\nto MPAMVPM7_EL2 registers. VPMR_MAX can be as large as 7 (8 registers)\nor 32 virtual PARTIDs. If MPAMIDR_EL1.VPMR_MAX == 0, there is only a single\nMPAMVPM<n>_EL2 register, MPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"MPAMVPM5_EL2" : "MPAMVPM5_EL2 provides mappings from virtual PARTIDs 20 - 23 to physical\nPARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2\nregisters. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs.\nIf MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register,\nMPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"ZVA" : "Zero data cache by address. Zeroes a naturally aligned block of N bytes,\nwhere the size of N is identified in DCZID_EL0.",
"ICC_BPR1_EL1" : "Defines the point at which the priority value fields split into two parts,\nthe group priority field and the subpriority field. The group priority\nfield determines Group 1 interrupt preemption.",
"VMECID_P_EL2" : "Primary MECID for EL1&0 stage 2 translation regime.",
"AMAIR_EL3" : "Provides implementation defined memory attributes for the memory regions\nspecified by MAIR_EL3.",
"ICC_NMIAR1_EL1" : "The PE reads this register to obtain the INTID of the signaled Group 1 non-maskable\ninterrupt. This read acts as an acknowledge for the interrupt.",
"AMAIR_EL2" : "Provides implementation defined memory attributes for the memory regions\nspecified by MAIR_EL2.",
"PAR_EL1" : "Returns the output address (OA) from an Address translation instruction\nthat executed successfully, or fault information if the instruction did\nnot execute successfully.",
"ESR_EL2" : "Holds syndrome information for an exception taken to EL2.",
"CNTPS_CVAL_EL1" : "Holds the compare value for the secure physical timer, usually accessible\nat EL3 but configurably accessible at EL1 in Secure state.",
"DBGDTRTX_EL0" : "Transfers data from the PE to an external debugger. For example, it is used\nby a debug target to transfer data to the debugger. See DBGDTR_EL0 for\nadditional architectural mappings. It is a component of the Debug Communication\nChannel.",
"TRCVIPCSSCTLR" : "Use this to select, or read, which PE Comparator Inputs can control the\nViewInst start/stop function.",
"DBGDTRRX_EL0" : "Transfers data from an external debugger to the PE. For example, it is used\nby a debugger transferring commands and data to a debug target. See DBGDTR_EL0\nfor additional architectural mappings. It is a component of the Debug Communications\nChannel.",
"TTBR0_EL2" : "When the Effective value of HCR_EL2.E2H is not 1, holds the base address\nof the translation table for the initial lookup for stage 1 of an address\ntranslation in the EL2 translation regime, and other information for this\ntranslation regime.\nWhen the Effective value of HCR_EL2.E2H is 1, holds the base address of\nthe translation table for the initial lookup for stage 1 of the translation\nof an address from the lower VA range in the EL2&0 translation regime,\nand other information for this translation regime.",
"RVALE1IS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, if TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange, and one of the following applies:\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"MVFR0_EL1" : "Describes the features provided by the AArch32 Advanced SIMD and Floating-point\nimplementation.\nMust be interpreted with MVFR1_EL1 and MVFR2_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"PIRE0_EL1" : "Stage 1 Permission Indirection Register for unprivileged access of the EL1&0\ntranslation regime.",
"MAIR_EL2" : "Provides the memory attribute encodings corresponding to the possible AttrIndx\nvalues in a Long-descriptor format translation table entry for stage 1\ntranslations at EL2.",
"CNTP_CTL_EL0" : "Control register for the EL1 physical timer.",
"S1E3A" : "Performs stage 1 address translation as defined for EL3, while ignoring\npermissions checks from the given virtual address.",
"SPMACCESSR_EL2" : "Controls access to System PMUs from EL1 and EL0.",
"TRCTSCTLR" : "Controls the insertion of global timestamps in the trace stream.",
"ID_ISAR6_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,\nID_ISAR4_EL1 and ID_ISAR5_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"PMCNTENSET_EL0" : "Allows software to enable the following counters:\nReading from this register shows which counters are enabled.",
"HACR_EL2" : "Hypervisor Auxiliary Control Register\n BIT 0: TRAP_CPU_EXT\n BIT 4: TRAP_AIDR\n BIT 10: TRAP_AMX\n BIT 11: TRAP_SPRR\n BIT 13: TRAP_GXF\n BIT 14: TRAP_CTRR\n BIT 16: TRAP_IPI\n BIT 18: TRAP_s3_4_c15_c5z6_x\n BIT 19: TRAP_s3_4_c15_c0z12_5\n BIT 20: GIC_CNTV\n BIT 25: TRAP_s3_4_c15_c10_4\n BIT 48: TRAP_SERROR_INFO\n BIT 49: TRAP_EHID\n BIT 50: TRAP_HID\n BIT 51: TRAP_s3_0_c15_c12_1z2\n BIT 52: TRAP_ACC\n BIT 56: TRAP_PMUV3\n BIT 57: TRAP_PM\n BIT 58: TRAP_UPM\n BIT 59: TRAP_s3_1z7_c15_cx_3",
"CNTHP_TVAL_EL2" : "Holds the timer value for the EL2 physical timer.",
"ID_AA64PFR0_EL1" : "Provides additional information about implemented PE features in AArch64\nstate.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"BRBTS_EL1" : "Captures the Timestamp value on a BRBE freeze event.",
"SPMCR_EL0" : "Main control register for System PMU <s>.",
"TPIDR2_EL0" : "Provides a location where SME-aware software executing at EL0 can store\nthread identifying information, for context management purposes.\nThe PE makes no use of this register.",
"SP_EL1" : "Holds the stack pointer associated with EL1. When executing at EL1, the\nvalue of SPSel.SP determines the current stack pointer:",
"CIGDSW" : "Clean and Invalidate data and Allocation Tags in data cache by set/way.",
"TRCSTALLCTLR" : "Enables trace unit functionality that prevents trace unit buffer overflows.",
"APDAKeyHi_EL1" : "Holds bits[127:64] of key A used for authentication of data pointer values.\nThe term APDAKey_EL1 is used to describe the concatenation of APDAKeyHi_EL1:\nAPDAKeyLo_EL1.",
"TRCVIIECTLR" : "Use this to select, or read, the Address Range Comparators for the ViewInst\ninclude/exclude function.",
"RPALOS" : "Invalidates cached copies of GPT entries from TLBs. Details:\nThe invalidation applies to TLB entries containing GPT information that\nrelates to a physical address.\nThe invalidation affects all TLBs in the Outer Shareable domain.\nInvalidates TLB entries containing GPT information from the final level\nof the GPT walk that relates to the supplied physical address.\nInvalidations are range-based, invalidating TLB entries starting from the\naddress in BaseADDR, within the range as specified by SIZE.\nThe full set of TLB maintenance instructions that invalidate cached GPT\nentries is: TLBI PAALL, TLBI PAALLOS, TLBI RPALOS, and TLBI RPAOS.\nThese instructions have the same ordering, observability, and completion\nbehavior as all other TLBI instructions.",
"MPAM0_EL1" : "Holds information to generate MPAM labels for memory requests when executing\nat EL0. When EL2 is implemented and enabled in the current Security state,\nthe MPAM virtualization option is present, MPAMHCR_EL2.GSTAPP_PLK == 1\nand HCR_EL2.TGE == 0, MPAM1_EL1 is used instead of MPAM0_EL1 to generate\nMPAM information to label memory requests.\nIf EL2 is implemented and enabled in the current Security state, and the\nEffective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the MPAM virtualization\noption is present and MPAMHCR_EL2.EL0_VPMEN == 1, then MPAM PARTIDs in\nMPAM0_EL1 are virtual and mapped into physical PARTIDs for the current\nSecurity state.",
"ICC_IAR1_EL1" : "The PE reads this register to obtain the INTID of the signaled Group 1 interrupt.\nThis read acts as an acknowledge for the interrupt.",
"VMALLS12E1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 or stage 2 translation table entry, from any level\nof the translation table walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ID_AA64MMFR1_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch64 state.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"SPSR_EL2" : "Holds the saved process state when an exception is taken to EL2.",
"AFSR1_EL3" : "Provides additional implementation defined fault status information for\nexceptions taken to EL3.",
"ID_AA64ZFR0_EL1" : "Provides additional information about the implemented features of the AArch64\nScalable Vector Extension instruction set, when FEAT_SVE or FEAT_SME is\nimplemented.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"PMSSCR_EL1" : "Holds status information about the captured counters and provides a mechanism\nfor software to initiate a sample.",
"RIPAS2LE1OS" : "If EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 64-bit stage 2 only translation table entry, from the leaf level of the\ntranslation table walk, indicated by the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry,\nfrom the leaf level of the translation table walk, if TTL is 0b00.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe entry would be used with the current VMID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nThe invalidation is not required to apply to caching structures that combine\nstage 1 and stage 2 translation table entries.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nFor more information about the architectural requirements for this System\ninstruction, see 'Invalidation of TLB entries from stage 2 translations'.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"AMCR_EL0" : "Global control register for the activity monitors implementation. AMCR_EL0\nis applicable to both the architected and the auxiliary counter groups.",
"HFGWTR2_EL2" : "Provides controls for traps of MSRR, MSR and MCR writes of System registers.",
"GVA" : "Write a value to the Allocation Tags of a naturally aligned block of N bytes,\nwhere the size of N is identified in DCZID_EL0. The Allocation Tag used\nis determined by the input address.",
"ID_ISAR4_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,\nand ID_ISAR5_EL1.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"ACCDATA_EL1" : "Holds the lower 32 bits of the data that is stored by an ST64BV0, Single-copy\natomic 64-byte EL0 store instruction.",
"CIVAC" : "Clean and Invalidate data cache by address to Point of Coherency.",
"AMCNTENCLR0_EL0" : "Disable control bits for the architected activity monitors event counters,\nAMEVCNTR0<n>_EL0.",
"HCRX_EL2" : "Provides configuration controls for virtualization, including defining whether\nvarious operations are trapped to EL2.",
"ASIDE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 translation table entry.\nThe entry would be used for the specified ASID, and either:\nIs from a level of lookup above the final level.\nIs a non-global entry from the final level of lookup.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate an address using the EL1&0 translation\nregime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"ERXMISC2_EL1" : "Accesses ERR<n>MISC2 for the error record <n> selected by ERRSELR_EL1.SEL.",
"CPACR_EL1" : "Controls access to trace, SME, Streaming SVE, SVE, and Advanced SIMD\nand floating-point functionality.",
"SPMCFGR_EL1" : "Describes the capabilities of System PMU <s>.",
"HDFGWTR2_EL2" : "Provides controls for traps of MSR and MCR writes of debug, trace, PMU,\nand Statistical Profiling System registers.",
"TRCVMIDCCTLR1" : "Virtual Context Identifier Comparator mask values for the TRCVMIDCVR<n>\nregisters, where n=4-7.",
"RVALE2IS" : "When EL2 is implemented and enabled in the current Security state, invalidates\ncached copies of translation table entries from TLBs that meet all the\nfollowing requirements:\nThe entry is one of the following:\nA 128-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nA 64-bit stage 1 translation table entry, if TTL is 0b00.\nThe entry would be used to translate any VA in the range determined by\nthe formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]\nusing the EL2 or EL2&0 translation regime, as determined by the Effective\nvalue of HCR_EL2.E2H, for the Security state.\nIf the Effective value of HCR_EL2.E2H is not 1, the entry is from the final\nlevel of the translation table walk.\nIf the Effective value of HCR_EL2.E2H is 1, one of the following applies:\nThe entry is a global entry from the final level of the translation table\nwalk.\nThe entry is a non-global entry from the final level of the translation\ntable walk that matches the specified ASID.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Inner Shareable shareability\ndomain as the PE that executes this System instruction.\nFor 128-bit translation table entry, the range of addresses invalidated\nis UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for\nthe translation system is not aligned.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMUACR_EL1" : "Enables or disables EL0 access to specfic Performance Monitors.",
"S1E1A" : "Performs a stage 1 address translation, while ignoring the permission checks\nusing the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"AMAIR2_EL1" : "Provides implementation defined memory attributes for the memory regions\nspecified by MAIR2_EL1.",
"TPIDR_EL3" : "Provides a location where software executing at EL3 can store thread identifying\ninformation, for OS management purposes.\nThe PE makes no use of this register.",
"SPMOVSCLR_EL0" : "Clears the state of overflow bits for event counters in System PMU <s>.",
"SPSel" : "Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx.",
"ISW" : "Invalidate data cache by set/way.\nWhen FEAT_MTE2 is implemented, this instruction might invalidate Allocation\nTags from caches. When it invalidates Allocation Tags from caches, it also\ncleans them.",
"ALLE3" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is a stage 1 translation table entry, from any level of the translation\ntable walk.\nThe entry would be required to translate an address using the EL3 translation\nregime.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"BRBINFINJ_EL1" : "The information of a Branch record for injection.",
"CNTHP_CVAL_EL2" : "Holds the compare value for the EL2 physical timer.",
"ICH_VTR_EL2" : "Reports supported GIC virtualization features.",
"DBGVCR32_EL2" : "Allows access to the AArch32 register DBGVCR from AArch64 state only. Its\nvalue has no effect on execution in AArch64 state.",
"LORN_EL1" : "Holds the number of the LORegion described in the current LORegion descriptor\nselected by LORC_EL1.DS.",
"MECID_P1_EL2" : "Primary MECID for EL2&0 accesses translated by TTBR1_EL2.",
"CGDSW" : "Clean data and Allocation Tags in data cache by set/way.",
"PMUSERENR_EL0" : "Enables or disables EL0 access to the Performance Monitors.",
"VTCR_EL2" : "The control register for stage 2 of the EL1&0 translation regime.",
"RVAAE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nfrom any level of the translation table walk, if TTL is 0b00.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor the EL1&0 and EL2&0 translation regimes, the invalidation applies to\nboth global entries and non-global entries with any ASID.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"VMPIDR_EL2" : "Holds the value of the Virtualization Multiprocessor ID. This is the value\nreturned by EL1 reads of MPIDR_EL1.",
"ACTLR_EL2" : "Provides implementation defined configuration and control options for EL2.\nArm recommends the contents of this register are updated to apply to EL0\nwhen the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, gaining configuration\nand control fields from the ACTLR_EL1. This avoids the need for software\nto manage the contents of these register when switching between a Guest\nOS and a Host OS.",
"GPTBR_EL3" : "The control register for Granule Protection Table base address.",
"PAN" : "Allows access to the Privileged Access Never bit.",
"ID_MMFR0_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch32 state.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"AMCFGR_EL0" : "Global configuration register for the activity monitors.\nProvides information on supported features, the number of counter groups\nimplemented, the total number of activity monitor event counters implemented,\nand the size of the counters. AMCFGR_EL0 is applicable to both the architected\nand the auxiliary counter groups.",
"TRCSYNCPR" : "Controls how often trace protocol synchronization requests occur.",
"ICC_EOIR1_EL1" : "A PE writes to this register to inform the CPU interface that it has completed\nthe processing of the specified Group 1 interrupt.",
"CCSIDR2_EL1" : "Provides the information about the architecture of the currently selected\ncache from bits[63:32] of CCSIDR_EL1.",
"ERXMISC3_EL1" : "Accesses ERR<n>MISC3 for the error record <n> selected by ERRSELR_EL1.SEL.",
"ICC_BPR0_EL1" : "Defines the point at which the priority value fields split into two parts,\nthe group priority field and the subpriority field. The group priority\nfield determines Group 0 interrupt preemption.",
"FPSR" : "Provides floating-point system status information.",
"MAIR_EL3" : "Provides the memory attribute encodings corresponding to the possible AttrIndx\nvalues in a Long-descriptor format translation table entry for stage 1\ntranslations at EL3.",
"FPMR" : "Controls behaviors of the FP8 instructions.",
"PM" : "Allows access to the PMU exception Mask bit.",
"TRCIDR10" : "Returns the tracing capabilities of the trace unit.",
"PMICNTSVR_EL1" : "Captures the PMU Instruction counter, PMICNTR_EL0.",
"VALE1" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL[3:2] is 0b00.\nThe entry would be used to translate the specified VA, and one of the following\napplies:\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate the specified VA using the EL1&0\ntranslation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to the PE that executes this System instruction.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"CNTPS_TVAL_EL1" : "Holds the timer value for the secure physical timer, usually accessible\nat EL3 but configurably accessible at EL1 in Secure state.",
"S12E1R" : "Performs stage 1 and 2 address translation, with permissions as if reading\nfrom the given virtual address from EL1, or from EL2 if the Effective value\nof HCR_EL2.{E2H, TGE} is {1, 1}, using the following translation regime:\nWhen FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS}\nis a reserved value, this instruction is UNDEFINED at EL3.",
"CISW" : "Clean and Invalidate data cache by set/way.",
"ERRSELR_EL1" : "Selects an error record to be accessed through the Error Record System registers.",
"TRBLIMITR_EL1" : "Defines the top address for the trace buffer, and controls the trace buffer\nmodes and enable.",
"UAO" : "Allows access to the User Access Override bit.",
"CIGSW" : "Clean and Invalidate Allocation Tags in data cache by set/way.",
"AMAIR2_EL3" : "Provides implementation defined memory attributes for the memory regions\nspecified by MAIR2_EL3.",
"SMCR_EL2" : "This register controls aspects of Streaming SVE that are visible at Exception\nlevels EL2, EL1, and EL0.",
"RVAE3" : "If EL3 is implemented, invalidates cached copies of translation table entries\nfrom TLBs that meet all the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange using the EL3 translation regime.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nThe invalidation applies to the PE that executes this System instruction.\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"RNDR" : "Random Number. Returns a 64-bit random number from an approved Random Bit\nGenerator, where the Deterministic Random Bit Generator within the Random\nBit Generator is reseeded from an approved entropy source at an implementation\ndefined rate. See 'Properties of the generated random number'.\nIf the hardware returns a genuine random number, PSTATE.NZCV is set to 0b0000.\nIf the instruction cannot return a genuine random number in a reasonable\nperiod of time, PSTATE.NZCV is set to 0b0100 and the data value returned\nis 0.",
"TRCIDR8" : "Returns the maximum speculation depth of the instruction trace element stream.",
"MECID_RL_A_EL3" : "Alternate MECID for EL3 accesses to the Realm physical address space, translated\nby TTBR0_EL3.",
"TRCSEQSTR" : "Use this to set, or read, the Sequencer state.",
"CNTHV_CTL_EL2" : "Control register for the EL2 virtual timer.",
"ID_AA64DFR2_EL1" : "Provides top level information about the debug system in AArch64.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"ICC_SRE_EL2" : "Controls whether the System register interface or the memory-mapped interface\nto the GIC CPU interface is used for EL2.",
"MPIDR_EL1" : "In a multiprocessor system, provides an additional PE identification mechanism.",
"RVAE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is one of the following:\nA 64-bit stage 1 translation table entry, from any level of the translation\ntable walk up to the level indicated in the TTL hint.\nIf FEAT_D128 is implemented, a 128-bit stage 1 translation table entry,\nif TTL is 0b00.\nThe entry would be used to translate any of the VAs in the specified address\nrange, and one of the following applies:\nThe entry is from a level of lookup above the final level and matches the\nspecified ASID.\nThe entry is a global entry from the final level of lookup.\nThe entry is a non-global entry from the final level of lookup that matches\nthe specified ASID.\nThe entry is within the address range determined by the formula [BaseADDR\n<= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].\nWhen EL2 is implemented and enabled in the current Security state:\nWhen EL2 is not implemented or is disabled in the current Security state,\nthe entry would be required to translate any of the VAs in the specified\naddress range using the EL1&0 translation regime for the Security state.\nThe Security state is indicated by the value of SCR_EL3.NS if FEAT_RME\nis not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nWhen a TLB maintenance instruction is generated to the Secure EL1&0 translation\nregime and is defined to pass a VMID argument, or would be defined to pass\na VMID argument if SCR_EL3.EEL2==1, then:\nFor 64-bit translation table entry, the range of addresses invalidated is\nUNPREDICTABLE when:\nFor the 4K translation granule:\nFor the 16K translation granule:\nFor the 64K translation granule:",
"ICC_DIR_EL1" : "When interrupt priority drop is separated from interrupt deactivation, a\nwrite to this register deactivates the specified interrupt.",
"REVIDR_EL1" : "Provides implementation-specific minor revision information.",
"FAR_EL3" : "Holds the faulting Virtual Address for all synchronous Instruction Abort\nexceptions, Data Abort exceptions and PC alignment fault exceptions that\nare taken to EL3.",
"IGDSW" : "Invalidate data and Allocation Tags in data cache by set/way.",
"MDCCINT_EL1" : "Enables interrupt requests to be signaled based on the DCC status flags.",
"AMAIR2_EL2" : "Provides implementation defined memory attributes for the memory regions\nspecified by MAIR2_EL2.",
"S1E3R" : "Performs stage 1 address translation as defined for EL3, with permissions\nas if reading from the given virtual address.",
"DCZID_EL0" : "Indicates the block size that is written with byte values of 0 by the DC\nZVA (Data Cache Zero by Address) System instruction.\nIf FEAT_MTE is implemented, this register also indicates the granularity\nat which the DC GVA and DC GZVA instructions write.",
"TRFCR_EL1" : "Provides EL1 controls for Trace.",
"SCTLR_EL3" : "Provides top level control of the system, including its memory system, at\nEL3.",
"DBGCLAIMSET_EL1" : "Used by software to set the CLAIM tag bits to 1.\nThe architecture does not define any functionality for the CLAIM tag bits.\nCLAIM tags are typically used for communication between the debugger and\ntarget software.\nUsed in conjunction with the DBGCLAIMCLR_EL1 register.",
"SMIDR_EL1" : "Provides additional identification mechanisms for scheduling purposes, for\na PE that supports Streaming SVE mode.",
"TRCITEEDCR" : "Controls instrumentation trace filtering.",
"TFSR_EL2" : "Holds accumulated Tag Check Faults occurring in EL2 that are not taken precisely.",
"GCSCR_EL3" : "Controls the Guarded Control Stack at EL3.",
"APIBKeyHi_EL1" : "Holds bits[127:64] of key B used for authentication of instruction pointer\nvalues.\nThe term APIBKey_EL1 is used to describe the concatenation of APIBKeyHi_EL1:\nAPIBKeyLo_EL1.",
"AMCGCR_EL0" : "Provides information on the number of activity monitor event counters implemented\nwithin each counter group.",
"MDCR_EL2" : "Provides EL2 configuration options for self-hosted debug and the Performance\nMonitors Extension.",
"SPSR_abt" : "Holds the saved process state when an exception is taken to Abort mode.",
"PIR_EL2" : "Stage 1 Permission Indirection Register for privileged access of the EL2\nor EL2&0 translation regime.",
"ALLE1OS" : "Invalidates cached copies of translation table entries from TLBs that meet\nall the following requirements:\nThe entry is a stage 1 or stage 2 translation table entry, from any level\nof the translation table walk.\nIf FEAT_RME is implemented, one of the following applies:\nIf FEAT_RME is not implemented, one of the following applies:\nThe invalidation applies to entries with any VMID.\nThe invalidation applies to all PEs in the same Outer Shareable shareability\ndomain as the PE that executes this System instruction.\nFor the EL1&0 translation regimes, the invalidation applies to both global\nentries and non-global entries with any ASID.\nIf FEAT_XS is implemented, the nXS variant of this System instruction is\ndefined.\nBoth variants perform the same invalidation, but the TLBI System instruction\nwithout the nXS qualifier waits for all memory accesses using in-scope\nold translation information to complete before it is considered complete.\nThe TLBI System instruction with the nXS qualifier is considered complete\nwhen the subset of these memory accesses with XS attribute set to 0 are\ncomplete.",
"PMSIDR_EL1" : "Describes the Statistical Profiling implementation to software.",
"AMCNTENSET1_EL0" : "Enable control bits for the auxiliary activity monitors event counters,\nAMEVCNTR1<n>_EL0.",
"ICC_ASGI1R_EL1" : "Generates Group 1 SGIs for the Security state that is not the current Security\nstate.",
"CNTV_TVAL_EL0" : "Holds the timer value for the EL1 virtual timer.",
"APGAKeyLo_EL1" : "Holds bits[63:0] of key used for generic pointer authentication code.\nThe term APGAKey_EL1 is used to describe the concatenation of APGAKeyHi_EL1:\nAPGAKeyLo_EL1.",
"PMOVSCLR_EL0" : "Allows software to clear the unsigned overflow flags for the following counters\nto 0:\nReading from this register shows the current unsigned overflow flag values.",
"MPAMIDR_EL1" : "Indicates the presence and maximum PARTID and PMG values supported in the\nimplementation. It also indicates whether the implementation supports MPAM\nvirtualization.",
"PMBIDR_EL1" : "Provides information to software as to whether the buffer can be programmed\nat the current Exception level.",
"PMSNEVFR_EL1" : "Controls sample filtering by events. The overall inverted filter is the\nlogical OR of these filters. For example, if PMSNEVFR_EL1.E[3] and PMSNEVFR_EL1.E[5]\nare both set to 1, samples that have either event 3 (Level 1 unified or\ndata cache refill) or event 5 (TLB walk) set to 1 are not recorded.",
"MFAR_EL3" : "Records the faulting physical address for a Granule Protection Check, synchronous\nExternal abort, or SError exception taken to EL3.",
"CONTEXTIDR_EL2" : "Identifies the current Process Identifier for EL2.\nThe value of the whole of this register is called the Context ID and is\nused by:\nThe significance of this register is for debug and trace use only.",
"ICV_CTLR_EL1" : "Controls aspects of the behavior of the GIC virtual CPU interface and provides\ninformation about the features implemented.",
"GCSSS1" : "Validates that the stack being switched to contains a Valid cap entry, stores\nan In-progress cap entry on to the stack that is getting switched to and\nsets the current Guarded Control Stack Pointer to the stack that is getting\nswitched to.",
"APDAKeyLo_EL1" : "Holds bits[63:0] of key A used for authentication of data pointer values.\nThe term APDAKey_EL1 is used to describe the concatenation of APDAKeyHi_EL1:\nAPDAKeyLo_EL1.",
"FAR_EL2" : "Holds the faulting Virtual Address for all synchronous Instruction Abort\nexceptions, Data Abort exceptions, PC alignment fault exceptions and Watchpoint\nexceptions that are taken to EL2.",
"ID_AA64PFR1_EL1" : "Provides additional information about implemented PE features in AArch64\nstate.\nFor general information about the interpretation of the ID registers, see\n'Principles of the ID scheme for fields in ID registers'.",
"SP_EL2" : "Holds the stack pointer associated with EL2. When executing at EL2, the\nvalue of SPSel. SP determines the current stack pointer:",
"CNTHVS_CTL_EL2" : "Control register for the Secure EL2 virtual timer.",
"CIGVAC" : "Clean and Invalidate Allocation Tags in data cache by address to Point of\nCoherency.",
"OSDTRRX_EL1" : "Used for save and restore of DBGDTRRX_EL0. It is a component of the Debug\nCommunications Channel.",
"SPMSELR_EL0" : "Selects the System PMU and event counter registers to access.",
"LOREA_EL1" : "Holds the physical address of the end of the LORegion described in the current\nLORegion descriptor selected by LORC_EL1.DS.",
"ID_ISAR2_EL1" : "Provides information about the instruction sets implemented by the PE in\nAArch32 state.\nMust be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1,\nand ID_ISAR5_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"MPAMVPM1_EL2" : "MPAMVPM1_EL2 provides mappings from virtual PARTIDs 4 - 7 to physical PARTIDs.\nMPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM0_EL2\nto MPAMVPM7_EL2 registers. VPMR_MAX can be as large as 7 (8 registers)\nor 32 virtual PARTIDs. If MPAMIDR_EL1.VPMR_MAX == 0, there is only a single\nMPAMVPM<n>_EL2 register, MPAMVPM0_EL2.\nVirtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for PARTIDs in\nMPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for PARTIDs in MPAM0_EL1.\nA virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only\nwhen the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.",
"TFSR_EL1" : "Holds accumulated Tag Check Faults occurring in EL1 that are not taken precisely.",
"ID_MMFR3_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch32 state.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"MDCCSR_EL0" : "Read-only register containing control status flags for the DCC.",
"DBGAUTHSTATUS_EL1" : "Provides information about the state of the implementation defined authentication\ninterface for debug.",
"MPAM1_EL1" : "Holds information to generate MPAM labels for memory requests when executing\nat EL1.\nWhen EL2 is implemented and enabled in the current Security state, the MPAM\nvirtualization option is present, MPAMHCR_EL2.GSTAPP_PLK == 1 and HCR_EL2.TGE\n== 0, MPAM1_EL1 is used instead of MPAM0_EL1 to generate MPAM labels for\nmemory requests when executing at EL0.\nMPAM1_EL1 is an alias for MPAM2_EL2 when executing at EL2 and the Effective\nvalue of HCR_EL2.E2H is 1.\nMPAM1_EL12 is an alias for MPAM1_EL1 when executing at EL2 or EL3 and the\nEffective value of HCR_EL2.E2H is 1.\nIf EL2 is implemented and enabled in the current Security state, the MPAM\nvirtualization option is present and MPAMHCR_EL2.EL1_VPMEN == 1, MPAM PARTIDs\nin MPAM1_EL1 are virtual and mapped into physical PARTIDs for the current\nSecurity state. This mapping of MPAM1_EL1 virtual PARTIDs to physical PARTIDs\nwhen EL1_VPMEN is 1 also applies when MPAM1_EL1 is used at EL0 due to MPAMHCR_EL2.GSTAPP_PLK.",
"ALLINT" : "Allows access to the all interrupt mask bit.",
"TRCITECR_EL2" : "Provides EL2 controls for Trace Instrumentation.",
"RCWSMASK_EL1" : "Contains the software mask used by RCWS instructions.",
"ID_MMFR2_EL1" : "Provides information about the implemented memory model and memory management\nsupport in AArch32 state.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"SCTLR2_EL1" : "Provides top level control of the system, including its memory system, at\nEL1 and EL0.",
"TRCBBCTLR" : "Controls the regions in the memory map where branch broadcasting is active.",
"ID_DFR1_EL1" : "Provides top level information about the debug system in AArch32.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"TRCSEQRSTEVR" : "Moves the Sequencer to state 0 when a programmed resource event occurs.",
"AFSR1_EL2" : "Provides additional implementation defined fault status information for\nexceptions taken to EL2.",
"CGVAP" : "Clean Allocation Tags in data cache by address to Point of Persistence.\nIf the memory system does not identify a Point of Persistence, then this\ninstruction behaves as a DC CGVAC.",
"TRBTRG_EL1" : "Specifies the number of bytes of trace to capture following a Detected Trigger\nbefore a Trigger Event.",
"GCSPOPM" : "Loads the 64-bit doubleword that is pointed to by the current Guarded Control\nStack Pointer, writes it to the destination register, and increments the\ncurrent Guarded Control Stack Pointer register by the size of a Guarded\nControl Stack procedure return record.",
"SPSR_irq" : "Holds the saved process state when an exception is taken to IRQ mode.",
"MDSCR_EL1" : "Main control register for the debug implementation.",
"GCSPUSHX" : "Decrements the current Guarded Control Stack Pointer register by the size\nof a Guarded Control Stack exception return record and stores a Guarded\nControl Stack exception return record to the Guarded Control Stack.",
"SMPRIMAP_EL2" : "Maps the value in SMPRI_EL1 to a streaming execution priority value for\ninstructions executed at EL1 and EL0 in the same Security states as EL2.",
"OSDTRTX_EL1" : "Used for save/restore of DBGDTRTX_EL0. It is a component of the Debug Communications\nChannel.",
"SCTLR2_EL3" : "Provides top level control of the system, including its memory system, at\nEL3.",
"ID_PFR2_EL1" : "Gives information about the AArch32 programmers' model.\nMust be interpreted with ID_PFR0_EL1 and ID_PFR1_EL1.\nFor general information about the interpretation of the ID registers see\n'Principles of the ID scheme for fields in ID registers'.",
"HID0_EL1" : "Hardware Implementation-Dependent Register 0",
"EHID0_EL1" : "Hardware Implementation-Dependent Register 0 (E-core)",
"HID1_EL1" : "Hardware Implementation-Dependent Register 1",
"EHID1_EL1" : "Hardware Implementation-Dependent Register 1 (E-core)",
"HID2_EL1" : "Hardware Implementation-Dependent Register 2",
"EHID2_EL1" : "Hardware Implementation-Dependent Register 2 (E-core)",
"HID3_EL1" : "Hardware Implementation-Dependent Register 3",
"EHID3_EL1" : "Hardware Implementation-Dependent Register 3 (E-core)",
"HID4_EL1" : "Hardware Implementation-Dependent Register 4",
"EHID4_EL1" : "Hardware Implementation-Dependent Register 4 (E-core)",
"HID5_EL1" : "Hardware Implementation-Dependent Register 5",
"EHID5_EL1" : "Hardware Implementation-Dependent Register 5 (E-core)",
"HID6_EL1" : "Hardware Implementation-Dependent Register 6",
"HID7_EL1" : "Hardware Implementation-Dependent Register 7",
"EHID7_EL1" : "Hardware Implementation-Dependent Register 7 (E-core)",
"HID8_EL1" : "Hardware Implementation-Dependent Register 8",
"HID9_EL1" : "Hardware Implementation-Dependent Register 9",
"EHID9_EL1" : "Hardware Implementation-Dependent Register 9 (E-core)",
"HID10_EL1" : "Hardware Implementation-Dependent Register 10",
"EHID10_EL1" : "Hardware Implementation-Dependent Register 10 (E-core)",
"HID11_EL1" : "Hardware Implementation-Dependent Register 11",
"EHID11_EL1" : "Hardware Implementation-Dependent Register 11 (E-core)",
"HID13_EL1" : "Hardware Implementation-Dependent Register 13",
"HID14_EL1" : "Hardware Implementation-Dependent Register 14",
"HID16_EL1" : "Hardware Implementation-Dependent Register 16",
"HID17_EL1" : "Hardware Implementation-Dependent Register 17",
"HID18_EL1" : "Hardware Implementation-Dependent Register 18",
"EHID18_EL1" : "Hardware Implementation-Dependent Register 18 (E-core)",
"EHID20_EL1" : "Hardware Implementation-Dependent Register 20 (E-core)",
"HID21_EL1" : "Hardware Implementation-Dependent Register 21",
"HID26_EL1" : "Hardware Implementation-Dependent Register 26",
"HID27_EL1" : "Hardware Implementation-Dependent Register 27",
"PMCR0_EL1" : "Performance Monitor Control Register 0\n BIT 0 : PMC0_EN\n BIT 1 : PMC1_EN\n BIT 2 : PMC2_EN\n BIT 3 : PMC3_EN\n BIT 4 : PMC4_EN\n BIT 5 : PMC5_EN\n BIT 6 : PMC6_EN\n BIT 7 : PMC7_EN\n BITS 10 - 8: IRQ_MODE\n BIT 11 : IRQ_ACTIVE\n BIT 12 : PMC0_IRQ_EN\n BIT 13 : PMC1_IRQ_EN\n BIT 14 : PMC2_IRQ_EN\n BIT 15 : PMC3_IRQ_EN\n BIT 16 : PMC4_IRQ_EN\n BIT 17 : PMC5_IRQ_EN\n BIT 18 : PMC6_IRQ_EN\n BIT 19 : PMC7_IRQ_EN\n BIT 20 : DIS_CNT_PMI\n BIT 22 : WAIT_ERET\n BIT 23 : CNT_GLOBAL_L2C\n BIT 30 : USER_EN\n BIT 32 : PMC8_EN\n BIT 33 : PMC9_EN\n BIT 44 : PMC8_IRQ_EN\n BIT 45 : PMC9_IRQ_EN",
"PMCR1_EL1" : "Performance Monitor Control Register 1\n BITS 7 - 0: EL0_A32_PMC_0_7\n BITS 15 - 8: EL0_A64_PMC_0_7\n BITS 23 - 16: EL1_A64_PMC_0_7\n BITS 31 - 24: EL3_A64_PMC_0_7\n BITS 33 - 32: EL0_A32_PMC_8_9\n BITS 41 - 40: EL0_A64_PMC_8_9\n BITS 49 - 48: EL1_A64_PMC_8_9\n BITS 57 - 56: EL3_A64_PMC_8_9",
"PMCR2_EL1" : "Performance Monitor Control Register 2",
"PMCR3_EL1" : "Performance Monitor Control Register 3",
"PMCR4_EL1" : "Performance Monitor Control Register 4",
"PMESR0_EL1" : "Performance Monitor Event Selection Register 0\n BITS 7 - 0: PMC2_EVENT_SEL\n BITS 15 - 8: PMC3_EVENT_SEL\n BITS 23 - 16: PMC4_EVENT_SEL\n BITS 31 - 24: PMC5_EVENT_SEL",
"PMESR1_EL1" : "Performance Monitor Event Selection Register 1\n BITS 7 - 0: PMC6_EVENT_SEL\n BITS 15 - 8: PMC7_EVENT_SEL\n BITS 23 - 16: PMC8_EVENT_SEL\n BITS 31 - 24: PMC9_EVENT_SEL",
"PMCR1_GL1" : "Performance Monitor Control Register 1 (GL1)",
"PMSR_EL1" : "Performance Monitor Status Register\n BIT 0: PMC0_OVERFLOW\n BIT 1: PMC1_OVERFLOW\n BIT 2: PMC2_OVERFLOW\n BIT 3: PMC3_OVERFLOW\n BIT 4: PMC4_OVERFLOW\n BIT 5: PMC5_OVERFLOW\n BIT 6: PMC6_OVERFLOW\n BIT 7: PMC7_OVERFLOW\n BIT 8: PMC8_OVERFLOW\n BIT 9: PMC9_OVERFLOW",
"PMC0_EL1" : "Performance Monitor Counter 0",
"PMC1_EL1" : "Performance Monitor Counter 1",
"PMC2_EL1" : "Performance Monitor Counter 2",
"PMC3_EL1" : "Performance Monitor Counter 3",
"PMC4_EL1" : "Performance Monitor Counter 4",
"PMC5_EL1" : "Performance Monitor Counter 5",
"PMC6_EL1" : "Performance Monitor Counter 6",
"PMC7_EL1" : "Performance Monitor Counter 7",
"PMC8_EL1" : "Performance Monitor Counter 8",
"PMC9_EL1" : "Performance Monitor Counter 9",
"LSU_ERR_STS_EL1" : "Load-Store Unit Error Status",
"E_LSU_ERR_STS_EL1" : "Load-Store Unit Error Status (E-core)",
"LSU_ERR_CTL_EL1" : "Load-Store Unit Error Control",
"L2C_ERR_STS_EL1" : "L2 Cache Error Status",
"L2C_ERR_ADR_EL1" : "L2 Cache Address",
"L2C_ERR_INF_EL1" : "L2 Cache Error Information",
"FED_ERR_STS_EL1" : "FED Error Status",
"E_FED_ERR_STS_EL1" : "FED Error Status (E-Core)",
"APCTL_EL1" : "Pointer Authentication Control",
"SPR_LOCKDOWN_EL1" : "SPR Lockdown",
"KERNKEYLO_EL1" : "Pointer Authentication Kernel Key Low",
"KERNKEYHI_EL1" : "Pointer Authentication Kernel Key High",
"VMSA_LOCK_EL1" : "Virtual Memory System Architecture Lock",
"AMX_STATE_EL12" : "AMX State (EL1)",
"AMX_CONFIG_EL1" : "AMX Config (EL1)\n BIT 63: EN",
"APRR_EL0" : "APRR EL0",
"APRR_EL1" : "APRR EL1",
"CTRR_LOCK_EL1" : "CTRR Lock",
"CTRR_A_LWR_EL1" : "CTRR A Lower Address (EL1)",
"CTRR_A_UPR_EL1" : "CTRR A Upper Address (EL1)",
"CTRR_CTL_EL1" : "CTRR Control (EL1)",
"VMSA_LOCK_EL12" : "Virtual Memory System Architecture Lock (EL12)",
"APRR_JIT_MASK_EL2" : "APRR JIT Mask",
"AMX_CONFIG_EL12" : "AMX Config (EL12)",
"AMX_CTL_EL2" : "AMX Control (EL2)\n BIT 63: EN\n BIT 62: EN_EL1",
"CORE_INDEX" : "Core index in cluster",
"SPRR_PPERM_EL20" : "SPRR Permission Configuration Register (EL20, useless)",
"SPRR_UPERM_EL02" : "SPRR User Permission Configuration Register (EL02)",
"SPRR_UMPRR_EL2" : "SPRR User MPRR (EL2) (32 bit)",
"SPRR_UPERM_SH1_EL2" : "SPRR User Permission SH1 (EL2) (32 bit)",
"SPRR_UPERM_SH2_EL2" : "SPRR User Permission SH2 (EL2) (32 bit)",
"SPRR_UPERM_SH3_EL2" : "SPRR User Permission SH3 (EL2) (32 bit)",
"SPRR_UMPRR_EL12" : "SPRR User MPRR (EL12) (32 bit)",
"SPRR_UPERM_SH1_EL12" : "SPRR User Permission SH1 (EL12) (32 bit)",
"SPRR_UPERM_SH2_EL12" : "SPRR User Permission SH2 (EL12) (32 bit)",
"SPRR_UPERM_SH3_EL12" : "SPRR User Permission SH3 (EL12) (32 bit)",
"CTRR_A_LWR_EL12" : "CTRR A Lower Address (EL12)",
"CTRR_A_UPR_EL12" : "CTRR A Upper Address (EL12)",
"CTRR_B_LWR_EL12" : "CTRR B Lower Address (EL12)",
"CTRR_B_UPR_EL12" : "CTRR B Upper Address (EL12)",
"CTRR_CTL_EL12" : "CTRR Control (EL12)",
"CTRR_LOCK_EL12" : "CTRR Lock (EL12)",
"SIQ_CFG_EL1" : "System Interrupt Configuration (EL1)",
"ACNTPCT_EL0" : "Physical timer counter register (pre-spec CNTPCTSS_EL0)",
"ACNTVCT_EL0" : "Virtual timer counter register (pre-spec CNTVCTSS_EL0)",
"CTRR_A_LWR_EL2" : "",
"CTRR_A_UPR_EL2" : "",
"CTRR_CTL_EL2" : "",
"CTRR_LOCK_EL2" : "",
"JCTL_EL0" : "JITBox Control (EL0)",
"IPI_RR_LOCAL_EL1" : "IPI Request Register (Local)",
"IPI_RR_GLOBAL_EL1" : "IPI Request Register (Global)",
"DPC_ERR_STS_EL1" : "DPC Error Status",
"IPI_SR_EL1" : "IPI Status Register\n BIT 0: PENDING",
"VM_TMR_LR_EL2" : "VM Timer Link Register",
"VM_TMR_FIQ_ENA_EL2" : "VM Timer FIQ Enable\n BIT 0: ENA_V\n BIT 1: ENA_P",
"AWL_SCRATCH_EL1" : "AWL Scratch Register",
"IPI_CR_EL1" : "IPI Control Register",
"ACC_CFG_EL1" : "Apple Core Cluster Configuration",
"CYC_OVRD_EL1" : "Cyclone Override",
"ACC_OVRD_EL1" : "Apple Core Cluster Override",
"ACC_EBLK_OVRD_EL1" : "Apple Core Cluster E-Block Override",
"MMU_ERR_STS_EL1" : "MMU Error Status",
"AFSR1_GL1" : "Auxiliary Fault Status Register 1 (GL1)",
"AFSR1_GL2" : "Auxiliary Fault Status Register 1 (GL2)",
"AFSR1_GL12" : "Auxiliary Fault Status Register 1 (GL12)",
"SPRR_CONFIG_EL1" : "SPRR Configuration Register (EL1)\n BIT 0: EN\n BIT 1: LOCK_CONFIG\n BIT 4: LOCK_PERM\n BIT 5: LOCK_KERNEL_PERM",
"GXF_CONFIG_EL1" : "GXF Configuration Register (EL1)\n BIT 0: EN",
"SPRR_AMRANGE_EL1" : "SPRR AM Range (EL1)",
"GXF_CONFIG_EL2" : "GXF Configuration Register (EL2)",
"SPRR_UPERM_EL0" : "SPRR User Permission Configuration Register (EL0)",
"SPRR_PPERM_EL1" : "SPRR Kernel Permission Configuration Register (EL1)",
"SPRR_PPERM_EL2" : "SPRR Kernel Permission Configuration Register (EL2)",
"E_MMU_ERR_STS_EL1" : "MMU Error Status (E-Core)",
"APGAKeyLo_EL12" : "Pointer Authentication Key A for Code Low (EL12)",
"APGAKeyHi_EL12" : "Pointer Authentication Key A for Code High (EL12)",
"KERNKEYLO_EL12" : "Pointer Authentication Kernel Key Low (EL12)",
"KERNKEYHI_EL12" : "Pointer Authentication Kernel Key High (EL12)",
"AFPCR_EL0" : "Apple Floating-Point Control Register",
"AIDR2_EL1" : "Apple ID Register 2",
"SPRR_UMPRR_EL1" : "SPRR User MPRR (EL1) (32 bit)",
"SPRR_PMPRR_EL1" : "SPRR Kernel MPRR (EL1) (32 bit)",
"SPRR_PMPRR_EL2" : "SPRR Kernel MPRR (EL2) (32 bit)",
"SPRR_UPERM_SH1_EL1" : "SPRR User Permission SH1 (EL1) (32 bit)",
"SPRR_UPERM_SH2_EL1" : "SPRR User Permission SH2 (EL1) (32 bit)",
"SPRR_UPERM_SH3_EL1" : "SPRR User Permission SH3 (EL1) (32 bit)",
"SPRR_PPERM_SH1_EL1" : "SPRR Kernel Permission SH1 (EL1) (32 bit)",
"SPRR_PPERM_SH2_EL1" : "SPRR Kernel Permission SH2 (EL1) (32 bit)",
"SPRR_PPERM_SH3_EL1" : "SPRR Kernel Permission SH3 (EL1) (32 bit)",
"SPRR_PPERM_SH1_EL2" : "SPRR Kernel Permission SH1 (EL2) (32 bit)",
"SPRR_PPERM_SH2_EL2" : "SPRR Kernel Permission SH2 (EL2) (32 bit)",
"SPRR_PPERM_SH3_EL2" : "SPRR Kernel Permission SH3 (EL2) (32 bit)",
"SPRR_PMPRR_EL12" : "SPRR Kernel MPRR (EL12) (32 bit)",
"SPRR_PPERM_SH1_EL12" : "SPRR Kernel Permission SH1 (EL12) (32 bit)",
"SPRR_PPERM_SH2_EL12" : "SPRR Kernel Permission SH2 (EL12) (32 bit)",
"SPRR_PPERM_SH3_EL12" : "SPRR Kernel Permission SH3 (EL12) (32 bit)",
"APIAKeyLo_EL12" : "Pointer Authentication Key A for Instruction Low (EL12)",
"APIAKeyHi_EL12" : "Pointer Authentication Key A for Instruction High (EL12)",
"APIBKeyLo_EL12" : "Pointer Authentication Key A for Instruction Low (EL12)",
"APIBKeyHi_EL12" : "Pointer Authentication Key A for Instruction High (EL12)",
"APDAKeyLo_EL12" : "Pointer Authentication Key A for Data Low (EL12)",
"APDAKeyHi_EL12" : "Pointer Authentication Key A for Data High (EL12)",
"APDBKeyLo_EL12" : "Pointer Authentication Key A for Data Low (EL12)",
"APDBKeyHi_EL12" : "Pointer Authentication Key A for Data High (EL12)",
"GXF_STATUS_EL1" : "GXF Status Register (CurrentG)\n BIT 0: GUARDED",
"GXF_ENTRY_EL1" : "GXF genter Entry Vector Register (EL1)",
"GXF_PABENTRY_EL1" : "GXF Abort Vector Register (EL1)",
"ASPSR_EL1" : "ASPSR (EL1)",
"VBAR_GL12" : "Vector Base Address Register (GL12)",
"SPSR_GL12" : "Saved Program Status Register (GL12)",
"ASPSR_GL12" : "ASPSR (GL12)",
"ESR_GL12" : "Exception Syndrome Register (GL12)",
"ELR_GL12" : "Exception Link Register (GL12)",
"FAR_GL12" : "Fault Address Register (GL12)",
"SP_GL12" : "Stack Pointer Register (GL12)",
"TPIDR_GL1" : "Software Thread ID Register (GL1)",
"VBAR_GL1" : "Vector Base Address Register (GL1)",
"SPSR_GL1" : "Saved Program Status Register (GL1)",
"ASPSR_GL1" : "ASPSR (GL1)",
"ESR_GL1" : "Exception Syndrome Register (GL1)",
"ELR_GL1" : "Exception Link Register (GL1)",
"FAR_GL1" : "Fault Address Register (GL1)",
"TPIDR_GL2" : "Software Thread ID Register (GL2)",
"VBAR_GL2" : "Vector Base Address Register (GL2)",
"SPSR_GL2" : "Saved Program Status Register (GL2)",
"ASPSR_GL2" : "ASPSR (GL2)",
"ESR_GL2" : "Exception Syndrome Register (GL2)",
"ELR_GL2" : "Exception Link Register (GL2)",
"FAR_GL2" : "Fault Address Register (GL2)",
"GXF_ENTRY_EL2" : "GXF genter Entry Vector Register (EL2)",
"GXF_PABENTRY_EL2" : "GXF Abort Vector Register (EL2)",
"APCTL_EL2" : "Pointer Authentication Control (EL2)",
"APSTS_EL2_MAYBE" : "Pointer Authentication Status (EL2, maybe)",
"APSTS_EL1" : "Pointer Authentication Status",
"SPRR_CONFIG_EL2" : "SPRR Configuration Register (EL2)",
"SPRR_AMRANGE_EL2" : "SPRR AM Range (EL2)",
"VMKEYLO_EL2" : "Pointer Authentication VM Machine Key Low",
"VMKEYHI_EL2" : "Pointer Authentication VM Machine Key High",
"ACTLR_EL12" : "",
"APSTS_EL12" : "Pointer Authentication Status (EL12)",
"APCTL_EL12" : "Pointer Authentication Control (EL12)",
"GXF_CONFIG_EL12" : "GXF Configuration Register (EL12)",
"GXF_ENTRY_EL12" : "GXF genter Entry Vector Register (EL12)",
"GXF_PABENTRY_EL12" : "GXF Abort Vector Register (EL12)",
"SPRR_CONFIG_EL12" : "SPRR Configuration Register (EL12)",
"SPRR_AMRANGE_EL12" : "SPRR AM Range (EL12)",
"SPRR_PPERM_EL12" : "SPRR Permission Configuration Register (EL12)",
"UPMCR0_EL1" : "Uncore Performance Monitor Control Register 0",
"UPMESR0_EL1" : "Uncore Performance Monitor Event Selection Register 0",
"UPMECM0_EL1" : "Uncore Performance Monitor Event Core Mask 0",
"UPMECM1_EL1" : "Uncore Performance Monitor Event Core Mask 1",
"UPMPCM_EL1" : "Uncore Performance Monitor PMI Core Mask",
"UPMSR_EL1" : "Uncore Performance Monitor Status Register",
"UPMECM2_EL1" : "Uncore Performance Monitor Event Core Mask 2",
"UPMECM3_EL1" : "Uncore Performance Monitor Event Core Mask 3",
"UPMESR1_EL1" : "Uncore Performance Monitor Event Selection Register 1",
"UPMC0_EL1" : "Uncore Performance Monitor Counter 0",
"UPMC1_EL1" : "Uncore Performance Monitor Counter 1",
"UPMC2_EL1" : "Uncore Performance Monitor Counter 2",
"UPMC3_EL1" : "Uncore Performance Monitor Counter 3",
"UPMC4_EL1" : "Uncore Performance Monitor Counter 4",
"UPMC5_EL1" : "Uncore Performance Monitor Counter 5",
"UPMC6_EL1" : "Uncore Performance Monitor Counter 6",
"UPMC7_EL1" : "Uncore Performance Monitor Counter 7",
"UPMC8_EL1" : "Uncore Performance Monitor Counter 8",
"UPMC9_EL1" : "Uncore Performance Monitor Counter 9",
"UPMC10_EL1" : "Uncore Performance Monitor Counter 10",
"UPMC11_EL1" : "Uncore Performance Monitor Counter 11",
"UPMC12_EL1" : "Uncore Performance Monitor Counter 12",
"UPMC13_EL1" : "Uncore Performance Monitor Counter 13",
"UPMC14_EL1" : "Uncore Performance Monitor Counter 14",
"UPMC15_EL1" : "Uncore Performance Monitor Counter 15",
"TEECR32_EL1" : "Allows access to the AArch32 register TEECR from AArch64 state only.\nIts value has no effect on execution in AArch64 state.\nThis register is part of the Legacy feature registers functional group",
"TEEHBR32_EL1" : "Allows access to the AArch32 register TEEHBR from AArch64 state only.\nIts value has no effect on execution in AArch64 state.\nThis register is part of the Legacy feature registers functional group",
"OPMAT0" : "",
"OPMAT1" : "",
"OPMSK0" : "",
"OPMSK1" : "",
"PMTRHLD6" : "",
"PMTRHLD4" : "",
"PMTRHLD2" : "",
"PMMMAP" : "",
"L2_CRAMCONFIG" : "",
"L2E_ERR_STS" : "",
"L2E_ERR_ADR" : "",
"L2E_ERR_INF" : "",
"CTRR_B_UPR_EL1" : "",
"CTRR_B_LWR_EL1" : "",
"UAOIMM" : "",
"PANIMM" : "",
"SPSELIMM" : "",
"SSBSIMM" : "",
"DITIMM" : "",
"DAIFSET" : "",
"DAIFCLR" : "",
"DBGWFAR" : "",
"ID_AA32RES3_EL1" : "",
"ID_AA32RES7_EL1" : "",
"ID_AA64PFR3_EL1" : "",
"ID_AA64ZFR2_EL1" : "",
"ID_AA64DFR3_EL1" : "",
"ID_AA64AFR2_EL1" : "",
"ID_AA64AFR3_EL1" : "",
"ID_AA64ISAR4_EL1" : "",
"ID_AA64ISAR5_EL1" : "",
"ID_AA64ISAR6_EL1" : "",
"ID_AA64ISAR7_EL1" : "",
"ID_AA64MMFR5_EL1" : "",
"ID_AA64MMFR6_EL1" : "",
"ID_AA64MMFR7_EL1" : "",
"HID25" : "",
"HID28" : "",
"HID29" : "",
"BLOCK_CMAINT_CFG" : "",
"HID12" : "",
"HID15" : "",
"HID19" : "",
"BIU_TLIMIT" : "",
"LLC_WRR2" : "",
"HID24" : "",
"HID22" : "",
"HID23" : "",
"APPL_CONTEXTPTR" : "",
"LD_LATPROF_CTL_EL21" : "",
"AON_CPU_MSTALL_CTL01_EL1" : "",
"PM_MEMFLT_CTL23_EL1" : "",
"REDIR_ACNTV_CTL_EL0" : "",
"LCL_ACNTVCTSS_NOREDIR_EL0" : "",
"LD_LATPROF_INF_EL2" : "",
"AON_CPU_MSTALL_CTR2_EL1" : "",
"REDIR_ACNTP_CVAL_EL0" : "",
"CNTV_CVAL_NOREDIR_EL0" : "",
"LCL_ACNTPCT_NOREDIR_EL0" : "",
"PMCR_AFFINITY_EL1" : "",
"AON_CPU_MSTALL_CTR3_EL1" : "",
"REDIR_ACNTP_TVAL_EL0" : "",
"CNTV_TVAL_NOREDIR_EL0" : "",
"VMSA_HV_LOCK_EL2" : "",
"PMSWCTRL_EL1" : "",
"PMCR5_EL0" : "",
"AON_CPU_MSTALL_CTR4_EL1" : "",
"PMCompare0_EL1" : "",
"PMCompare1_EL1" : "",
"VMSA_NV_LOCK_EL2" : "",
"AON_CPU_MSTALL_CTR5_EL1" : "",
"REDIR_ACNTP_CTL_EL0" : "",
"PMCompare5_EL1" : "",
"PMCompare6_EL1" : "",
"PMCompare7_EL1" : "",
"PMCR_BVRNG4_EL1" : "",
"PM_PMI_PC" : "",
"AON_CPU_MSTALL_CTR6_EL1" : "",
"REDIR_ACNTV_CVAL_EL0" : "",
"LCL_ACNTVCT_NOREDIR_EL0" : "",
"PMCR_BVRNG5_EL1" : "",
"AON_CPU_MSTALL_CTR7_EL1" : "",
"REDIR_ACNTV_TVAL_EL0" : "",
"LCL_ACNTPCTSS_NOREDIR_EL0" : "",
"LD_LATPROF_CTR_EL1" : "",
"AON_CPU_MSTALL_CTL23_EL1" : "",
"PM_MEMFLT_CTL45_EL1" : "",
"ACNTRDIR_EL21" : "",
"ACNTKCTL_NOREDIR_EL1" : "",
"LD_LATPROF_STS_EL1" : "",
"AON_CPU_MSTALL_CTL45_EL1" : "",
"REDIR_ACNTHP_CVAL_EL2" : "",
"LCL_CNTVCT_NOREDIR_EL0" : "",
"ACNTP_CVAL_NOREDIR_EL0" : "",
"LD_LATPROF_INF_EL1" : "",
"AON_CPU_MSTALL_CTL67_EL1" : "",
"REDIR_ACNTHP_TVAL_EL2" : "",
"LCL_CNTPCTSS_NOREDIR_EL0" : "",
"ACNTP_TVAL_NOREDIR_EL0" : "",
"LD_LATPROF_CTL_EL2" : "",
"AON_CPU_MEMFLT_CTL01_EL1" : "",
"REDIR_ACNTHP_CTL_EL2" : "",
"LCL_CNTVCTSS_NOREDIR_EL0" : "",
"ACNTP_CTL_NOREDIR_EL0" : "",
"LD_LATPROF_CMD_EL1" : "",
"AON_CPU_MEMFLT_CTL23_EL1" : "",
"REDIR_ACNTHV_CVAL_EL2" : "",
"ACNTV_CVAL_NOREDIR_EL0" : "",
"PMCR1_EL2" : "",
"AON_CPU_MEMFLT_CTL45_EL1" : "",
"REDIR_ACNTHV_TVAL_EL2" : "",
"CNTKCTL_NOREDIR_EL1" : "",
"ACNTV_TVAL_NOREDIR_EL0" : "",
"PMCR1_EL12" : "",
"AON_CPU_MEMFLT_CTL67_EL1" : "",
"REDIR_ACNTHV_CTL_EL2" : "",
"CNTP_CVAL_NOREDIR_EL0" : "",
"ACNTV_CTL_NOREDIR_EL0" : "",
"AON_CPU_MSTALL_CTR0_EL1" : "",
"REDIR_ACNTFRQ_EL0" : "",
"CNTP_TVAL_NOREDIR_EL0" : "",
"LCL_CNTPCT_NOREDIR_EL0" : "",
"LD_LATPROF_CTL_EL12" : "",
"AON_CPU_MSTALL_CTR1_EL1" : "",
"ACNTVOFF_EL2" : "",
"CNTP_CTL_NOREDIR_EL0" : "",
"CNTV_CTL_NOREDIR_EL0" : "",
"UPMCFILTER0" : "",
"UPMCFILTER1" : "",
"UPMCFILTER2" : "",
"UPMCFILTER3" : "",
"UPMCFILTER4" : "",
"UPMCFILTER5" : "",
"UPMCFILTER6" : "",
"UPMCFILTER7" : "",
"AFLATCTL1_EL1" : "",
"AFLATVALBIN0_EL1" : "",
"AFLATINFLO_EL1" : "",
"UUSERTAG_EL0" : "",
"KUSERTAG_EL1" : "",
"HUSERTAG_EL2" : "",
"LLC_TRACE_CTL0" : "",
"LLC_TRACE_CTL1" : "",
"LLC_UP_REQ_VC" : "",
"LLC_UP_REQ_VC_THRESH" : "",
"LLC_UP_REQ_VC_2" : "",
"LLC_UP_REQ_VC_THRESH_2" : "",
"LLC_DRAM_HASH0" : "",
"LLC_DRAM_HASH1" : "",
"LLC_DRAM_HASH2" : "",
"LLC_DRAM_HASH3" : "",
"LLC_TRACE_CTL2" : "",
"LLC_HASH0" : "",
"LLC_HASH1" : "",
"LLC_HASH2" : "",
"LLC_HASH3" : "",
"LLC_WRR" : "",
"AFLATCTL2_EL1" : "",
"AFLATVALBIN1_EL1" : "",
"AFLATINFHI_EL1" : "",
"AFLATCTL3_EL1" : "",
"AFLATVALBIN2_EL1" : "",
"AFLATCTL4_EL1" : "",
"AFLATVALBIN3_EL1" : "",
"LLC_FILL_CTL" : "",
"AFLATCTL5_LO_EL1" : "",
"AFLATVALBIN4_EL1" : "",
"AFLATCTL5_HI_EL1" : "",
"LLC_FILL_DAT" : "",
"AFLATVALBIN5_EL1" : "",
"AFLATVALBIN6_EL1" : "",
"AFLATVALBIN7_EL1" : "",
"CMAINT_BCAST_LIST_1" : "",
"CMAINT_BCAST_CTL" : "",
"LLC_ERR_INJ" : "",
"FED_ERR_CTL" : "",
"IMPL_MSR_RO_CTRL0_EL2" : "",
"PREDAKEYLo_EL1" : "",
"PREDAKEYHi_EL1" : "",
"PREDBKEYLo_EL1" : "",
"PREDBKEYHi_EL1" : "",
"AVNCR_EL2" : "",
"ACC_CTRR_B_LWR_EL2" : "",
"ACC_CTRR_B_UPR_EL2" : "",
"REDIR_LCL_ACNTPCT_EL0" : "",
"REDIR_LCL_ACNTVCT_EL0" : "",
"ACFG_EL1" : "",
"AHCR_EL2" : "",
"APL_INTSTATUS_EL21" : "",
"APL_INTSTATUS_EL2" : "",
"IMPL_MSR_LOCK_EL21" : "",
"REDIR_ACNTHCTL_EL2" : "",
"IMPL_MSR_LOCK_EL2" : "",
"JAPIAKeyLo_EL2" : "",
"JAPIAKeyHi_EL2" : "",
"JAPIBKeyLo_EL2" : "",
"JAPIBKeyHi_EL2" : "",
"JAPIAKeyLo_EL21" : "",
"JAPIAKeyHi_EL21" : "",
"JAPIBKeyLo_EL21" : "",
"JAPIBKeyHi_EL21" : "",
"JAPIAKeyLo_EL12" : "",
"JAPIAKeyHi_EL12" : "",
"JAPIBKeyLo_EL12" : "",
"JAPIBKeyHi_EL12" : "",
"ACNTRDIR_EL2" : "",
"ACNTRDIR_EL12" : "",
"JRANGE_EL2" : "",
"JRANGE_EL21" : "",
"JRANGE_EL12" : "",
"JCTL_EL2" : "",
"JCTL_EL21" : "",
"JCTL_EL12" : "",
"AMDSCR_EL1" : "",
"VMSA_LOCK_EL2" : "",
"AMX_STATE_C0_EL1" : "",
"AMX_STATE_C1_EL1" : "",
"AMX_STATE_C2_EL1" : "",
"AMX_STATE_C3_EL1" : "",
"AMX_STATUS_C0_EL1" : "",
"AMX_STATUS_C1_EL1" : "",
"AMX_STATUS_C2_EL1" : "",
"AMX_STATUS_C3_EL1" : "",
"AMX_NUMCTXT_EL1" : "",
"ACNTP_CVAL_EL02" : "",
"REDIR_ACNTP_TVAL_EL02" : "",
"ACNTP_CTL_EL02" : "",
"ACNTV_CVAL_EL02" : "",
"ACNTV_TVAL_EL02" : "",
"AMX_PRIORITY_C0_EL1" : "",
"AMX_PRIORITY_C1_EL1" : "",
"AMX_PRIORITY_C2_EL1" : "",
"AMX_PRIORITY_C3_EL1" : "",
"CTRR_B_LWR_EL2" : "",
"CTRR_B_UPR_EL2" : "",
"SPRR_HUPERM_SH04_EL2" : "",
"SPRR_HUPERM_SH05_EL2" : "",
"SPRR_HUPERM_SH06_EL2" : "",
"SPRR_HUPERM_SH07_EL2" : "",
"SPRR_VUPERM_SH04_EL1" : "",
"SPRR_VUPERM_SH05_EL1" : "",
"SPRR_VUPERM_SH06_EL1" : "",
"SPRR_VUPERM_SH07_EL1" : "",
"REDIR_ACNTKCTL_EL1" : "",
"ACNTKCTL_EL12" : "",
"AF_ERR_CFG0" : "",
"AP_ERR_CFG0" : "",
"AF_ERR_SRC_IDS" : "",
"DPC_ERR_CTL" : "",
"CPU_STS" : "",
"HIST_TRIG" : "",
"ARRAY_INDEX" : "",
"IL1_DATA0" : "",
"IL1_DATA1" : "",
"DL1_DATA0" : "",
"DL1_DATA1" : "",
"MMUDATA0" : "",
"MMUDATA1" : "",
"LLC_DATA0" : "",
"LLC_DATA1" : "",
"TRACE_CORE_CFG" : "",
"KTRACE_MESSAGE" : "",
"TRACE_CORE_CFG_EXT" : "",
"WatchDogDiag0" : "",
"WatchDogDiag1" : "",
"DBG_WRAP_GLB" : "",
"TRACE_STREAM_BASE" : "",
"TRACE_STREAM_FILL" : "",
"TRACE_STREAM_BASE1" : "",
"TRACE_STREAM_FILL1" : "",
"TRACE_STREAM_IRQ" : "",
"TRACE_AUX_CTL" : "",
"UTRIG_EVENT" : "",
"TRACE_CTL" : "",
"TRACE_DAT" : "",
"PBLK_STS" : "",
"PBLK_EXE_ST" : "",
"CPM_PWRDN_CTL" : "",
"PRE_LLCFLUSH_TMR" : "",
"PRE_TD_TMR" : "",
"ACC_SLP_WAKE_UP_TMR" : "",
"PBLK_PSW_DLY" : "",
"BP_OBJC_ADR_EL1" : "",
"BP_OBJC_CTL_EL1" : "",
"SP_GL11_GL21" : "",
"MMU_SESR_EL2" : "",
"SP_GL2" : "",
"KERNKEYLo_EL2" : "",
"KERNKEYHi_EL2" : "",
"ASPSR_EL12" : "",
"APIAKeyLo_EL2" : "",
"APIAKeyHi_EL2" : "",
"APIBKeyLo_EL2" : "",
"APIBKeyHi_EL2" : "",
"APDAKeyLo_EL2" : "",
"APDAKeyHi_EL2" : "",
"APDBKeyLo_EL2" : "",
"APDBKeyHi_EL2" : "",
"APGAKeyLo_EL2" : "",
"APGAKeyHi_EL2" : "",
"MMU_SESR_CTL_EL2" : "",
"HPFAR_GL2" : "",
"SP_GL22" : "",
"SPRR_UPERM_SH04_EL1" : "",
"SPRR_UPERM_SH05_EL1" : "",
"SPRR_UPERM_SH06_EL1" : "",
"SPRR_UPERM_SH07_EL1" : "",
"SPRR_PPERM_SH04_EL21" : "",
"SPRR_PPERM_SH05_EL21" : "",
"SPRR_PPERM_SH06_EL21" : "",
"SPRR_PPERM_SH07_EL21" : "",
"SPRR_PPERM_SH04_EL2" : "",
"SPRR_PPERM_SH05_EL2" : "",
"SPRR_PPERM_SH06_EL2" : "",
"SPRR_PPERM_SH07_EL2" : "",
"SPRR_PPERM_SH04_EL12" : "",
"SPRR_PPERM_SH05_EL12" : "",
"SPRR_PPERM_SH06_EL12" : "",
"SPRR_PPERM_SH07_EL12" : "",
"ADSPSR_EL0" : "",
"PMCR1_GL2" : "",
"ASPSR_EL2" : "",
"PMCR1_GL21" : "",
"PWRDNSAVE0" : "",
"NRG_ACC_CTL" : "",
"AON_CNT0" : "",
"CPU_CNT0" : "",
"AON_CNT5" : "",
"CPU_CNT5" : "",
"UPMCR1_EL1" : "",
"AON_CNT_CTL5" : "",
"CPU_CNT_CTL5" : "",
"AON_CNT6" : "",
"CPU_CNT6" : "",
"AON_CNT_CTL6" : "",
"CPU_CNT_CTL6" : "",
"AON_CNT7" : "",
"CPU_CNT7" : "",
"AON_CNT_CTL7" : "",
"CPU_CNT_CTL7" : "",
"PWRDNSAVE1" : "",
"CORE_NRG_ACC_DAT" : "",
"AON_CNT_CTL0" : "",
"CPU_CNT_CTL0" : "",
"ACC_PWR_DN_SAVE" : "",
"CPM_NRG_ACC_DAT" : "",
"AON_CNT1" : "",
"CPU_CNT1" : "",
"UPMSWCTRL_EL1" : "",
"CORE_SRM_NRG_ACC_DAT" : "",
"AON_CNT_CTL1" : "",
"CPU_CNT_CTL1" : "",
"AON_CNT_CTL" : "",
"CPM_SRM_NRG_ACC_DAT" : "",
"AON_CNT2" : "",
"CPU_CNT2" : "",
"CPU_CNT_CTL" : "",
"AON_CNT_CTL2" : "",
"CPU_CNT_CTL2" : "",
"AON_CNT3" : "",
"CPU_CNT3" : "",
"AON_CNT_CTL3" : "",
"CPU_CNT_CTL3" : "",
"AON_CNT4" : "",
"CPU_CNT4" : "",
"AON_CNT_CTL4" : "",
"CPU_CNT_CTL4" : ""
}
HINTS_REGEX =
{
"SPMEVTYPER[0-9]{1,2}_EL0" : "With SPMEVFILTR<n>_EL0 and SPMEVFILT2R<n>_EL0, configures when event counter\nSPMEVCNTR<n>_EL0 in System PMU <s> increments.\nThe contents of this register are implementation defined. An Event Type\nSelect Register typically contains:",
"AMEVTYPER0[0-9]{1,2}_EL0" : "Provides information on the events that an architected activity monitor\nevent counter AMEVCNTR0<n>_EL0 counts.",
"TRCSEQEVR[0-9]{1,2}" : "Moves the Sequencer state:",
"TRCSSPCICR[0-9]{1,2}" : "Returns the status of the corresponding Single-shot Comparator Control.",
"S3_[0-9]{1,2}_C[0-9]{1,2}_C[0-9]{1,2}_[0-9]{1,2}" : "This area of the instruction set space is reserved for implementation defined\nregisters.",
"AMEVCNTVOFF0[0-9]{1,2}_EL2" : "Holds the 64-bit virtual offset for architected activity monitor events.",
"AMEVCNTR1[0-9]{1,2}_EL0" : "Provides access to the auxiliary activity monitor event counters.",
"SPMEVFILT2R[0-9]{1,2}_EL0" : "With SPMEVTYPER<n>_EL0 and SPMEVFILTR<n>_EL0, configures when event counter\nSPMEVCNTR<n>_EL0 in System PMU <s> increments.\nThe contents of this register are implementation defined. For more information,\nsee SPMEVTYPER<n>_EL0.",
"BRBTGT[0-9]{1,2}_EL1" : "The target address of Branch record n + (BRBFCR_EL1.BANK * 32).",
"DBGBVR[0-9]{1,2}_EL1" : "Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint\nmatching. Forms breakpoint n together with control register DBGBCR<n>_EL1.",
"BRBINF[0-9]{1,2}_EL1" : "The information for Branch record n + (BRBFCR_EL1.BANK * 32).",
"ICC_AP0R[0-9]{1,2}_EL1" : "Provides information about Group 0 active priorities.",
"TRCVMIDCVR[0-9]{1,2}" : "Contains the Virtual Context Identifier Comparator value.",
"SPMEVCNTR[0-9]{1,2}_EL0" : "Event counter <n> in System PMU <s>, where n is 0 to 63.",
"TRCRSCTLR[0-9]{1,2}" : "Controls the selection of the resources in the trace unit.",
"TRCACVR[0-9]{1,2}" : "Contains the address value.",
"PMEVTYPER[0-9]{1,2}_EL0" : "Configures event counter n, where n is 0 to 30.",
"DBGBCR[0-9]{1,2}_EL1" : "Holds control information for a breakpoint. Forms breakpoint n together\nwith value register DBGBVR<n>_EL1.",
"ICV_AP0R[0-9]{1,2}_EL1" : "Provides information about virtual Group 0 active priorities.",
"TRCCNTRLDVR[0-9]{1,2}" : "This sets or returns the reload count value for Counter <n>.",
"DBGWVR[0-9]{1,2}_EL1" : "Holds a data address value for use in watchpoint matching. Forms watchpoint\nn together with control register DBGWCR<n>_EL1.",
"SPMCGCR[0-9]{1,2}_EL1" : "Describes the configuration of counter groups in System PMU <s>.",
"TRCEXTINSELR[0-9]{1,2}" : "Use this to set, or read, which External Inputs are resources to the trace\nunit.\nThe name TRCEXTINSELR is an alias of TRCEXTINSELR0.",
"TRCCIDCVR[0-9]{1,2}" : "Contains a Context identifier value.",
"PMEVCNTR[0-9]{1,2}_EL0" : "Holds event counter n, which counts events, where n is 0 to 30.",
"ICV_AP1R[0-9]{1,2}_EL1" : "Provides information about virtual Group 1 active priorities.",
"PMEVCNTSVR[0-9]{1,2}_EL1" : "Captures the PMU Event counter <n>, PMEVCNTR<n>_EL0.",
"AMEVCNTVOFF1[0-9]{1,2}_EL2" : "Holds the 64-bit virtual offset for auxiliary activity monitor events.",
"AMEVTYPER1[0-9]{1,2}_EL0" : "Provides information on the events that an auxiliary activity monitor event\ncounter AMEVCNTR1<n>_EL0 counts.",
"TRCACATR[0-9]{1,2}" : "Defines the type of access for the corresponding TRCACVR<n> Register. This\nregister configures the context type, Exception levels, alignment, masking\nthat is applied by the Address Comparator, and how the Address Comparator\nbehaves when it is one half of an Address Range Comparator.",
"BRBSRC[0-9]{1,2}_EL1" : "The source address of Branch record n + (BRBFCR_EL1.BANK * 32).",
"SPMEVFILTR[0-9]{1,2}_EL0" : "With SPMEVTYPER<n>_EL0 and SPMEVFILT2R<n>_EL0, configures when event counter\nSPMEVCNTR<n>_EL0 in System PMU <s> increments.\nThe contents of this register are implementation defined. For more information,\nsee SPMEVTYPER<n>_EL0.",
"TRCSSCCR[0-9]{1,2}" : "Controls the corresponding Single-shot Comparator Control resource.",
"TRCCNTVR[0-9]{1,2}" : "This sets or returns the value of Counter <n>.",
"DBGWCR[0-9]{1,2}_EL1" : "Holds control information for a watchpoint. Forms watchpoint n together\nwith value register DBGWVR<n>_EL1.",
"AMEVCNTR0[0-9]{1,2}_EL0" : "Provides access to the architected activity monitor event counters.",
"S1_[0-9]{1,2}_C[0-9]{1,2}_C[0-9]{1,2}_[0-9]{1,2}" : "This area of the System instruction encoding space is reserved for implementation\ndefined System instructions.",
"ICH_AP0R[0-9]{1,2}_EL2" : "Provides information about Group 0 virtual active priorities for EL2.",
"TRCIMSPEC[0-9]{1,2}" : "These registers might return information that is specific to an implementation,\nor enable features specific to an implementation to be programmed. The\nproduct Technical Reference Manual describes these registers.",
"ICC_AP1R[0-9]{1,2}_EL1" : "Provides information about Group 1 active priorities.",
"TRCSSCSR[0-9]{1,2}" : "Returns the status of the corresponding Single-shot Comparator Control.",
"ICH_LR[0-9]{1,2}_EL2" : "Provides interrupt context information for the virtual CPU interface.",
"ICH_AP1R[0-9]{1,2}_EL2" : "Provides information about Group 1 virtual active priorities for EL2.",
"TRCCNTCTLR[0-9]{1,2}" : "Controls the operation of Counter <n>."
}
SYSM =
{
"APSR" : 0b00000000,
"IAPSR" : 0b00000001,
"EAPSR" : 0b00000010,
"XPSR" : 0b00000011,
"IPSR" : 0b00000101,
"EPSR" : 0b00000110,
"IEPSR" : 0b00000111,
"MSP" : 0b00001000,
"PSP" : 0b00001001,
"MSPLIM" : 0b00001010,
"PSPLIM" : 0b00001011,
"PRIMASK" : 0b00010000,
"BASEPRI" : 0b00010001,
"BASEPRI_MAX" : 0b00010010,
"FAULTMASK" : 0b00010011,
"CONTROL" : 0b00010100,
"PAC_KEY_P_0" : 0b00100000,
"PAC_KEY_P_1" : 0b00100001,
"PAC_KEY_P_2" : 0b00100010,
"PAC_KEY_P_3" : 0b00100011,
"PAC_KEY_U_0" : 0b00100100,
"PAC_KEY_U_1" : 0b00100101,
"PAC_KEY_U_2" : 0b00100110,
"PAC_KEY_U_3" : 0b00100111,
"MSP_NS" : 0b10001000,
"PSP_NS" : 0b10001001,
"MSPLIM_NS" : 0b10001010,
"PSPLIM_NS" : 0b10001011,
"PRIMASK_NS" : 0b10010000,
"BASEPRI_NS" : 0b10010001,
"FAULTMASK_NS" : 0b10010011,
"CONTROL_NS" : 0b10010100,
"SP_NS" : 0b10011000,
"PAC_KEY_P_0_NS" : 0b10100000,
"PAC_KEY_P_1_NS" : 0b10100001,
"PAC_KEY_P_2_NS" : 0b10100010,
"PAC_KEY_P_3_NS" : 0b10100011,
"PAC_KEY_U_0_NS" : 0b10100100,
"PAC_KEY_U_1_NS" : 0b10100101,
"PAC_KEY_U_2_NS" : 0b10100110,
"PAC_KEY_U_3_NS" : 0b10100111
}