// Maximum packet size supported by remote stub.
//
// If not set, IDA will detect the maximum packet size as follows:
//   - use value specified by PacketSize response to qSupported (if available)
//   - use size of 'g' packet response
//   - use min size of 399 bytes

// MAXPACKETSIZE = 399


// Default timeout for remote GDB stub responses (milliseconds)

REMOTE_TIMEOUT = 1000


// Enable no-acknowledgment mode if supported.

NOACK_MODE = 1


// Use stub's support for single-stepping, if available.
// Overrides configuration parameters below.
// SINGLE_STEP = 1


// x86 stub options:
// Stub reports software breakpoints one byte later than the actual address
X86_SWBP_PLUS1 = 1
// Stub returns only 16 bits of the linear EIP when in real mode, so we need to add CS<<4 to it
// X86_USE_CSIP = 1


// arm stub options:
// Check that the T bit in CPSR matches the operating mode when PC changes
ARM_UPDATE_CPSR = 1


// Run an external debugger before starting the debugger
// see gdb_arch.cfg for details

// EXT_CMDLINE = "qemu-system-arm -s -S -p -kernel \"%e\" -M versatilepb"; // NB: semicolon is mandatory!
// EXT_INITSP = 0x08000000

// copied from idp.hpp
#define PLFM_386         0        ///< Intel 80x86 (and x86_64/AMD64)
#define PLFM_Z80         1        ///< 8085, Z80
#define PLFM_68K         7        ///< Motorola 680x0
#define PLFM_MIPS       12        ///< MIPS
#define PLFM_ARM        13        ///< ARM (also includes AArch64)
#define PLFM_PPC        15        ///< PowerPC
#define PLFM_TRICORE    27        ///< Tasking Tricore
#define PLFM_NEC_V850X  55        ///< NEC V850 and V850ES/E1/E2

// processor-specific flags
#define M_PROFILE       0x01    // Set for ARM m-profile.
#define BANKED          0x02    // Set for ARM banked.


// format of the entries:
// "user description":
//  [
//    <IDA Platform ID>,
//    <0 for little-endian/1 for big-endian>,
//    <address size>,
//    <required processor-specific flags>,
//    <IDA processor name>,
//    <GDB architecture name>,
//    <root XML file name with register layout>,
//    <hex bytes of the software breakpoint instruction>,
//    <use stub's support for single-stepping, if available> (override with SINGLE_STEP)
//  ],

CONFIGURATIONS =
{
  // description               platform        bigendian addrsize reqflags   processor       archictecture       xmlfile                  softbpt     ss
  "Intel x86":               [ PLFM_386,       0,        4,       0,         "metapc",       "i386",             "i386-avx.xml",          "CC",       1 ],
  "Intel x64":               [ PLFM_386,       0,        8,       0,         "metapc",       "i386:x86-64",      "amd64-avx.xml",         "CC",       1 ],
  "ARM (M profile)":         [ PLFM_ARM,       0,        4,       M_PROFILE, "arm:ARMv7-ME", "arm",              "arm-with-m.xml",        "01DE",     1 ],
  "ARM (banked)":            [ PLFM_ARM,       0,        4,       BANKED,    "arm",          "arm",              "arm-with-banked.xml",   "FEDEFFE7", 1 ],
  "ARM Little-endian":       [ PLFM_ARM,       0,        4,       0,         "arm",          "arm",              "arm-with-neon.xml",     "FEDEFFE7", 1 ],
  "ARM Big-endian":          [ PLFM_ARM,       1,        4,       0,         "armb",         "arm",              "arm-with-neon.xml",     "E7FFDEFE", 1 ],
  "ARM64 (AArch64)":         [ PLFM_ARM,       0,        8,       0,         "arm",          "aarch64",          "aarch64.xml",           "D4200020", 1 ],
  "PowerPC Big-endian":      [ PLFM_PPC,       1,        4,       0,         "ppc",          "powerpc:common",   "powerpc-32.xml",        "7FE00008", 0 ],
  "PowerPC Little-endian":   [ PLFM_PPC,       0,        4,       0,         "ppcl",         "powerpc:common",   "powerpc-32.xml",        "0800E07F", 0 ],
  "PowerPC64 Big-endian":    [ PLFM_PPC,       1,        8,       0,         "ppc",          "powerpc:common64", "powerpc-altivec64.xml", "7FE00008", 0 ],
  "PowerPC64 Little-endian": [ PLFM_PPC,       0,        8,       0,         "ppcl",         "powerpc:common64", "powerpc-altivec64.xml", "0800E07F", 0 ],
  "MIPS Big-endian":         [ PLFM_MIPS,      1,        4,       0,         "mipsb",        "mips",             "mips-linux.xml",        "0005000D", 0 ],
  "MIPS Little-endian":      [ PLFM_MIPS,      0,        4,       0,         "mipsl",        "mips",             "mips-linux.xml",        "0D000500", 0 ],
  "MIPS64 Big-endian":       [ PLFM_MIPS,      1,        8,       0,         "mipsb",        "mips",             "mips64-linux.xml",      "0005000D", 0 ],
  "MIPS64 Little-endian":    [ PLFM_MIPS,      0,        8,       0,         "mipsl",        "mips",             "mips64-linux.xml",      "0D000500", 0 ],
  "Motorola 68k":            [ PLFM_68K,       1,        4,       0,         "68k",          "m68k",             "m68k.xml",              "4E4F",     1 ],
  "Infineon TriCore":        [ PLFM_TRICORE,   0,        4,       0,         "tricore",      "tricore",          "tricore.xml",           "00A0",     1 ],
  "Zilog Z80":               [ PLFM_Z80,       0,        4,       0,         "z80",          "z80",              "",                      "",         1 ],
  "Renesas RH850":           [ PLFM_NEC_V850X, 0,        4,       0,         "rh850",        "rh850",            "rh850.xml",             "40F8",     1 ]
}

// Default configuration for instant debugging (without database)
#ifdef __EA64__
#ifdef __IDAHOME__
#ifdef __PC__
DEFAULT_CONFIG = "Intel x64";
#endif // __PC__

#ifdef __ARM__
DEFAULT_CONFIG = "ARM64 (AArch64)";
#endif // __ARM__

#ifdef __MIPS__
DEFAULT_CONFIG = "MIPS64 Little-endian";
#endif // __MIPS__

#ifdef __PPC__
DEFAULT_CONFIG = "PowerPC64 Little-endian";
#endif // __PPC__

#ifdef __MC68K__
DEFAULT_CONFIG = "Motorola 68k";
#endif // __MC68K__

#else // __IDAHOME__
DEFAULT_CONFIG = "Intel x64";
#endif
#else
DEFAULT_CONFIG = "Intel x86";
#endif

IDA_FEATURES =
{
  "i386":
  {
    "org.gnu.gdb.i386.core":
    {
      "title": "General registers",
      "rename": { "eflags": "EFL" },
      "code_ptr": "eip",
      "stack_ptr": "esp",
      "frame_ptr": "ebp",
      "data_ptr": [ "eax", "ebx", "ecx", "edx", "esi", "edi" ],
      "bitfields":
      {
        "EFL":
        {
          "CF":  [  0,  0 ],
          "PF":  [  2,  2 ],
          "AF":  [  4,  4 ],
          "ZF":  [  6,  6 ],
          "SF":  [  7,  7 ],
          "TF":  [  8,  8 ],
          "IF":  [  9,  9 ],
          "DF":  [ 10, 10 ],
          "OF":  [ 11, 11 ],
          "NT":  [ 14, 14 ],
          "RF":  [ 16, 16 ],
          "VM":  [ 17, 17 ],
          "AC":  [ 18, 18 ],
          "VIF": [ 19, 19 ],
          "VIP": [ 20, 20 ],
          "ID":  [ 21, 21 ]
        }
      }
    },
    "org.gnu.gdb.i386.linux":
    {
      "title": "Linux registers",
      "data_ptr": [ "orig_eax" ]
    },
    "org.gnu.gdb.i386.sse":
    {
      "title": "SSE registers"
    },
    "org.gnu.gdb.i386.avx":
    {
      "title": "AVX registers"
    },
    "org.gnu.gdb.i386.avx512":
    {
      "title": "AVX512 registers"
    }
  },

  "i386:x86-64":
  {
    "org.gnu.gdb.i386.core":
    {
      "title": "General registers",
      "rename": { "eflags": "EFL" },
      "code_ptr": "rip",
      "stack_ptr": "rsp",
      "frame_ptr": "rbp",
      "data_ptr":
      [
        "rax", "rbx", "rcx", "rdx", "rsi", "rdi",
        "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
      ]
    },
    "org.gnu.gdb.i386.linux":
    {
      "title": "Linux registers",
      "data_ptr": [ "orig_rax" ]
    },
    "org.gnu.gdb.i386.sse":
    {
      "title": "SSE registers"
    },
    "org.gnu.gdb.i386.avx":
    {
      "title": "AVX registers"
    },
    "org.gnu.gdb.i386.avx512":
    {
      "title": "AVX512 registers"
    }
  },

  "arm":
  {
    "org.gnu.gdb.arm.core":
    {
      "title": "General registers",
      "rename": { "cpsr": "psr" },
      "code_ptr": "pc",
      "stack_ptr": "sp",
      "data_ptr":
      [
        "r0", "r1", "r2",  "r3",  "r4", "r5", "r6", "r7",
        "r8", "r9", "r10", "r11", "r12"
      ],
      "bitfields":
      {
        "psr":
        {
          "MODE": [  0,  4 ],
          "T":    [  5,  5 ],
          "F":    [  6,  6 ],
          "I":    [  7,  7 ],
          "A":    [  8,  8 ],
          "E":    [  9,  9 ],
          "IT":   [ 10, 15 ],
          "GE":   [ 16, 19 ],
          "J":    [ 24, 24 ],
          "IT2":  [ 25, 26 ],
          "Q":    [ 27, 27 ],
          "V":    [ 28, 28 ],
          "C":    [ 29, 29 ],
          "Z":    [ 30, 30 ],
          "N":    [ 31, 31 ]
        }
      }
    },
    "org.gnu.gdb.arm.m-profile":
    {
      "title": "General registers",
      "rename": { "xpsr": "psr" },
      "stack_ptr": "sp",
      "bitfields":
      {
        "psr":
        {
          "ISR_NUMBER": [  0,  8 ],
          "IT[3:2]":    [ 10, 11 ],
          "IT[7:4]":    [ 12, 15 ],
          "GE":         [ 16, 19 ],
          "T":          [ 24, 24 ],
          "IT[1:0]":    [ 25, 26 ],
          "Q":          [ 27, 27 ],
          "V":          [ 28, 28 ],
          "C":          [ 29, 29 ],
          "Z":          [ 30, 30 ],
          "N":          [ 31, 31 ]
        }
      }
    },
    "org.gnu.gdb.arm.vfp":
    {
      "title": "VFP registers"
    }
  },

  "aarch64":
  {
    "org.gnu.gdb.aarch64.core":
    {
      "title": "General registers",
      "rename": { "cpsr": "psr" },
      "stack_ptr": "sp",
      "data_ptr":
      [
         "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
         "x8",  "x9", "x10", "x11", "x12", "x13", "x14", "x15",
        "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
        "x24", "x25", "x26", "x27", "x28", "x29", "x30"
      ]
    },
    "org.gnu.gdb.aarch64.fpu":
    {
      "title": "FPU registers"
    }
  },

  "powerpc:common":
  {
    "org.gnu.gdb.power.core":
    {
      "title": "General registers",
      "stack_ptr": "r1",
      "code_ptr": "pc",
      "data_ptr":
      [
        "r0",         "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
        "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
        "lr",  "ctr"
      ]
    },
    "org.gnu.gdb.power.fpu":
    {
      "title": "FPU registers"
    },
    "org.gnu.gdb.power.altivec":
    {
      "title": "Altivec registers"
    },
    "org.gnu.gdb.power.linux":
    {
      "title": "Linux registers"
    }
  },

  "powerpc:common64":
  {
    "org.gnu.gdb.power.core":
    {
      "title": "General registers",
      "stack_ptr": "r1",
      "code_ptr": "pc",
      "data_ptr":
      [
        "r0",         "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
        "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
        "lr",  "ctr"
      ]
    },
    "org.gnu.gdb.power.fpu":
    {
      "title": "FPU registers"
    },
    "org.gnu.gdb.power.altivec":
    {
      "title": "Altivec registers"
    },
    "org.gnu.gdb.power.linux":
    {
      "title": "Linux registers"
    }
  },

  "mips":
  {
    "org.gnu.gdb.mips.cpu":
    {
      "title": "General registers",
      "rename":
      {
        "r0":  "zero",
        "r1":  "at",
        "r2":  "v0",
        "r3":  "v1",
        "r4":  "a0",
        "r5":  "a1",
        "r6":  "a2",
        "r7":  "a3",
        "r8":  "t0",
        "r9":  "t1",
        "r10": "t2",
        "r11": "t3",
        "r12": "t4",
        "r13": "t5",
        "r14": "t6",
        "r15": "t7",
        "r16": "s0",
        "r17": "s1",
        "r18": "s2",
        "r19": "s3",
        "r20": "s4",
        "r21": "s5",
        "r22": "s6",
        "r23": "s7",
        "r24": "t8",
        "r25": "t9",
        "r26": "k0",
        "r27": "k1",
        "r28": "gp",
        "r29": "sp",
        "r30": "fp",
        "r31": "ra"
      },
      "stack_ptr": "sp",
      "frame_ptr": "fp",
      "code_ptr": "pc",
      "data_ptr":
      [
        "zero",
        "at",
        "v0", "v1",
        "a0", "a1", "a2", "a3",
        "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
        "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
        "t8", "t9",
        "k0", "k1",
        "gp", "sp", "ra"
      ]
    },
    "org.gnu.gdb.mips.fpu":
    {
      "title": "FPU registers"
    },
    "org.gnu.gdb.mips.cp0":
    {
      "title": "CP0 registers"
    },
    "org.gnu.gdb.mips.dsp":
    {
      "title": "DSP registers"
    },
    "org.gnu.gdb.mips.linux":
    {
      "title": "Linux registers"
    }
  },

  "m68k":
  {
    "org.gnu.gdb.m68k.core":
    {
      "title": "General registers",
      "rename":
      {
        "fp": "a6",
        "sp": "a7",
        "ps": "sr"
      },
      "code_ptr": "pc",
      "stack_ptr": "a7",
      "bitfields":
      {
        "sr":
        {
          "C": [ 0, 0 ],
          "V": [ 1, 1 ],
          "Z": [ 2, 2 ],
          "N": [ 3, 3 ],
          "X": [ 4, 4 ]
        }
      }
    }
  },

  "tricore":
  {
    "tricore.core":
    {
      "title": "General registers",
      "rename": { "a10": "sp" },
      "code_ptr": "pc",
      "stack_ptr": "sp",
      "data_ptr":
      [
        "d0", "d1", "d2",  "d3",  "d4",  "d5",  "d6",  "d7",
        "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
        "a0", "a1", "a2",  "a3",  "a4",  "a5",  "a6",  "a7",
        "a8", "a9",        "a11", "a12", "a13", "a14", "a15"
      ],
      "bitfields":
      {
        "psw":
        {
          "CDC": [  0,  6 ],
          "CDE": [  7,  7 ],
          "GW":  [  8,  8 ],
          "IS":  [  9,  9 ],
          "IO":  [ 10, 10 ],
          "PRS": [ 12, 13 ],
          "USB": [ 24, 31 ]
        },
        "pcxi":
        {
          "PCX0": [  0, 15 ],
          "PCXS": [ 16, 19 ],
          "UL":   [ 22, 22 ],
          "PIE":  [ 23, 23 ],
          "PCPN": [ 24, 31 ]
        }
      }
    }
  },

  "rh850":
  {
    "rh850.core":
    {
      "title": "General registers",
      "rename":
      {
        "r3": "sp",
        "r4": "gp",
        "r30": "ep",
        "r31": "lp"
      },
      "code_ptr": "pc",
      "stack_ptr": "sp",
      "data_ptr":
      [
        "r0",  "r1",  "r2",                "r5",  "r6",  "r7",
        "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
        "r24", "r25", "r26", "r27", "r28", "r29"
      ],
      "bitfields":
      {
        "ecr":
        {
          "EICC": [  0, 15 ],
          "FECC": [ 16, 31 ]
        },
        "psw":
        {
          "Z":   [  0,  0 ],
          "S":   [  1,  1 ],
          "OV":  [  2,  2 ],
          "CY":  [  3,  3 ],
          "SAT": [  4,  4 ],
          "ID":  [  5,  5 ],
          "EP":  [  6,  6 ],
          "NP":  [  7,  7 ],
          "IMP": [ 16, 16 ],
          "DMP": [ 17, 17 ],
          "NPV": [ 18, 18 ]
        }
      }
    }
  }
}


// IDA detects the architecture by using the target information sent by the GDB stub.
// The necessary information is: cpu name, endianness, and bitness.
// Extra flags may also be used to distinguish between sub-architectures.
//
// Since the GDB stub fails to provide the necessary information in a simple manner,
// IDA uses a combination of different methods until all fields are obtained.
//
// Each method may provide any number of fields, where the value of -1 represents a
// field that cannot be unequivocally detected by this method.
//
// If the target information sent by the GDB stub fails to provide endianness and
// bitness, IDA will attempt to detect those fields after starting or attaching to
// the debuggee by reading the returned registers values.

// Architecture name given by the <architecture> tag.
ARCH_MAP =
{ //                    cpu             is_64 is_be flags
  "i386":             [ PLFM_386,        0,    0,   -1 ],
  "i386:x86-64":      [ PLFM_386,        1,    0,   -1 ],
  "arm":              [ PLFM_ARM,        0,   -1,   -1 ],
  "aarch64":          [ PLFM_ARM,        1,   -1,   -1 ],
  "powerpc:common":   [ PLFM_PPC,        0,   -1,   -1 ],
  "powerpc:common64": [ PLFM_PPC,        1,   -1,   -1 ],
  "mips":             [ PLFM_MIPS,      -1,   -1,   -1 ],
  "m68k":             [ PLFM_68K,        0,    1,   -1 ],
  "tricore":          [ PLFM_TRICORE,    0,    0,   -1 ],
  "z80":              [ PLFM_Z80,        0,    0,   -1 ],
  "rh850":            [ PLFM_NEC_V850X,  0,    0,   -1 ]
}

// Feature name given by the <feature> tags' "name" attribute.
FEATURE_MAP =
{ //                                  cpu             is_64 is_be flags
  "org.gnu.gdb.i386.core":          [ PLFM_386,       -1,    0,   -1 ],
  "org.gnu.gdb.arm.m-profile":      [ PLFM_ARM,        0,   -1,   M_PROFILE ],
  "net.sourceforge.openocd.banked": [ PLFM_ARM,       -1,   -1,   BANKED ],
  "org.gnu.gdb.arm.core":           [ PLFM_ARM,        0,   -1,   -1 ],
  "org.gnu.gdb.aarch64.core":       [ PLFM_ARM,        1,   -1,   -1 ],
  "org.gnu.gdb.power.core":         [ PLFM_PPC,       -1,   -1,   -1 ],
  "org.gnu.gdb.mips.cpu":           [ PLFM_MIPS,      -1,   -1,   -1 ],
  "org.gnu.gdb.m68k.core":          [ PLFM_68K,        0,    1,   -1 ],
  "tricore.core":                   [ PLFM_TRICORE,    0,    0,   -1 ],
  "rh850.core":                     [ PLFM_NEC_V850X,  0,    0,   -1 ]
}

// A register name (from all <reg> entries) that uniquely identifies the architecture.
UNIQUE_REGISTER_MAP =
{ // reg   cpu       is_64 is_be flags
  "eip": [ PLFM_386,  0,    0,   -1 ],
  "rip": [ PLFM_386,  1,    0,   -1 ]
}