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|
Version:
9.0~240807-1.fc42 ▾
|
; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; MOTOROLA SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:
; area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
; START and END are addresses, the end address is not included
; Interrupt vectors are declared in the following way:
; interrupt NAME ADDRESS COMMENT
.default MC9S12A128B
.MC9S12B64
.MC9S12B128
.MC9S12B256
.MC9S12C32
.MC9S12C64
.MC9S12C96
.MC9S12C128
.MC9S12D32
.MC9S12D64
.MC9S12DB128
.MC9S12DG128
.MC9S12DG256
.MC9S12DJ64
.MC9S12DJ128
.MC9S12DJ256
.MC9S12DP256
.MC9S12DP512
.MC9S12DT128
.MC9S12DT256
.MC9S12H128
.MC9S12H256
.MC9S12KG128
.MC9S12KT256
.MC9S12T64
.MC9S12XDP512
.MC9S12DB128B
.MC9S12DG128B
.MC9S12DG256B
.MC9S12DJ128B
.MC9S12DJ256B
.MC9S12DP256B
.MC9S12DT128B
;----------------------------------------------------------------------------
.MC9S12DT256
; MEMORY MAP
area DATA FSR 0x0000:0x0400
area DATA EEPROM_ 0x0400:0x1000
area DATA RAM_ 0x1000:0x4000
area CODE ROM 0x4000:0xFF00
area DATA USER_VEC 0xFF00:0x10000
; Interrupt and reset vector assignments
interrupt _Reset 0xFFFE
interrupt _Clock_Monitor_fail_reset 0xFFFC
interrupt _COP_failure_reset 0xFFFA
interrupt _trap 0xFFF8
interrupt _SWI 0xFFF6
interrupt _XIRQ 0xFFF4
interrupt _IRQ 0xFFF2
interrupt _Real_Time_Interrupt 0xFFF0
interrupt _Enhanced_Capture_Timer_channel_0 0xFFEE
interrupt _Enhanced_Capture_Timer_channel_1 0xFFEC
interrupt _Enhanced_Capture_Timer_channel_2 0xFFEA
interrupt _Enhanced_Capture_Timer_channel_3 0xFFE8
interrupt _Enhanced_Capture_Timer_channel_4 0xFFE6
interrupt _Enhanced_Capture_Timer_channel_5 0xFFE4
interrupt _Enhanced_Capture_Timer_channel_6 0xFFE2
interrupt _Enhanced_Capture_Timer_channel_7 0xFFE0
interrupt _Enhanced_Capture_Timer_overflow 0xFFDE
interrupt _Pulse_accumulator_A_overflow 0xFFDC
interrupt _Pulse_accumulator_input_edge 0xFFDA
interrupt _SPI0 0xFFD8
interrupt _SCI0 0xFFD6
interrupt _SCI1 0xFFD4
interrupt _ATD0 0xFFD2
interrupt _ATD1 0xFFD0
interrupt _Port_J 0xFFCE
interrupt _Port_H 0xFFCC
interrupt _Modulus_Down_Counter_underflow 0xFFCA
interrupt _Pulse_Accumulator_B_Overflow 0xFFC8
interrupt _CRG_PLL_lock 0xFFC6
interrupt _CRG_Self_Clock_Mode 0xFFC4
interrupt _BDLC 0xFFC2
interrupt _IIC_Bus 0xFFC0
interrupt _SPI1 0xFFBE
interrupt _SPI2 0xFFBC
interrupt _EEPROM 0xFFBA
interrupt _FLASH 0xFFB8
interrupt _CAN0_wakeup 0xFFB6
interrupt _CAN0_errors 0xFFB4
interrupt _CAN0_receive 0xFFB2
interrupt _CAN0_transmit 0xFFB0
interrupt _CAN1_wakeup 0xFFAE
interrupt _CAN1_errors 0xFFAC
interrupt _CAN1_receive 0xFFAA
interrupt _CAN1_transmit 0xFFA8
interrupt _CAN4_wakeup 0xFF96
interrupt _CAN4_errors 0xFF94
interrupt _CAN4_receive 0xFF92
interrupt _CAN4_transmit 0xFF90
interrupt _Port_P_Interrupt 0xFF8E
interrupt _PWM_Emergency_Shutdown 0xFF8C
; INPUT/ OUTPUT PORTS
PORTA 0x0000
PORTB 0x0001
DDRA 0x0002
DDRB 0x0003
PORTE 0x0008
DDRE 0x0009
PEAR 0x000A
MODE 0x000B
PUCR 0x000C
RDRIV 0x000D
EBICTL 0x000E
INITRM 0x0010
INITEE 0x0012
MISC 0x0013
ITCR 0x0015
ITEST 0x0016
PARTIDH 0x001A
PARTIDL 0x001B
MEMSIZ0 0x001C
MEMSIZ1 0x001D
INTCR 0x001E
HPRIO 0x001F
BKPCT0 0x0028
BKPCT1 0x0029
BKP0X 0x002A
BKP0H 0x002B
BKP0L 0x002C
BKP1X 0x002D
BKP1H 0x002E
BKP1L 0x002F
PPAGE 0x0030
PORTK 0x0032
DDRK 0x0033
SYNR 0x0034
REFDV 0x0035
CTFLG 0x0036
CRGFLG 0x0037
CRGINT 0x0038
CLKSEL 0x0039
PLLCTL 0x003A
RTICTL 0x003B
COPCTL 0x003C
FORBYP 0x003D
CTCTL 0x003E
ARMCOP 0x003F
TIOS 0x0040
CFORC 0x0041
OC7M 0x0042
OC7D 0x0043
TCNT 0x0044
TSCR1 0x0046
TTOV 0x0047
TCTL1 0x0048
TCTL2 0x0049
TCTL3 0x004A
TCTL4 0x004B
TIE 0x004C
TSCR2 0x004D
TFLG1 0x004E
TFLG2 0x004F
TC0 0x0050
TC1 0x0052
TC2 0x0054
TC3 0x0056
TC4 0x0058
TC5 0x005A
TC6 0x005C
TC7 0x005E
PACTL 0x0060
PAFLG 0x0061
PACN3 0x0062
PACN1 0x0064
PACN0 0x0065
MCCTL 0x0066
MCFLG 0x0067
ICPAR 0x0068
DLYCT 0x0069
ICOVW 0x006A
ICSYS 0x006B
TIMTST 0x006D
PBCTL 0x0070
PBFLG 0x0071
PA3H 0x0072
PA2H 0x0073
PA1H 0x0074
PA0H 0x0075
MCCNT 0x0076
TC0H 0x0078
TC1H 0x007A
TC2H 0x007C
TC3H 0x007E
ATD0CTL0 0x0080
ATD0CTL1 0x0081
ATD0CTL2 0x0082
ATD0CTL3 0x0083
ATD0CTL4 0x0084
ATD0CTL5 0x0085
ATD0STAT0 0x0086
ATD0TEST0 0x0088
ATD0TEST1 0x0089
ATD0STAT1 0x008B
ATD0DIEN 0x008D
PORTAD0 0x008F
ATD0DR0H 0x0090
ATD0DR0L 0x0091
ATD0DR1H 0x0092
ATD0DR1L 0x0093
ATD0DR2H 0x0094
ATD0DR2L 0x0095
ATD0DR3H 0x0096
ATD0DR3L 0x0097
ATD0DR4H 0x0098
ATD0DR4L 0x0099
ATD0DR5H 0x009A
ATD0DR5L 0x009B
ATD0DR6H 0x009C
ATD0DR6L 0x009D
ATD0DR7H 0x009E
ATD0DR7L 0x009F
PWME 0x00A0
PWMPOL 0x00A1
PWMCLK 0x00A2
PWMPRCLK 0x00A3
PWMCAE 0x00A4
PWMCTL 0x00A5
PWMTST 0x00A6
PWMPRSC 0x00A7
PWMSCLA 0x00A8
PWMSCLB 0x00A9
PWMSCNTA 0x00AA
PWMSCNTB 0x00AB
PWMCNT0 0x00AC
PWMCNT1 0x00AD
PWMCNT2 0x00AE
PWMCNT3 0x00AF
PWMCNT4 0x00B0
PWMCNT5 0x00B1
PWMCNT6 0x00B2
PWMCNT7 0x00B3
PWMPER0 0x00B4
PWMPER1 0x00B5
PWMPER2 0x00B6
PWMPER3 0x00B7
PWMPER4 0x00B8
PWMPER5 0x00B9
PWMPER6 0x00BA
PWMPER7 0x00BB
PWMDTY0 0x00BC
PWMDTY1 0x00BD
PWMDTY2 0x00BE
PWMDTY3 0x00BF
PWMDTY4 0x00C0
PWMDTY5 0x00C1
PWMDTY6 0x00C2
PWMDTY7 0x00C3
PWMSDN 0x00C4
SCI0BDH 0x00C8
SCI0BDL 0x00C9
SCI0CR1 0x00CA
SCI0CR2 0x00CB
SCI0SR1 0x00CC
SCI0SR2 0x00CD
SCI0DRH 0x00CE
SCI0DRL 0x00CF
SCI1BDH 0x00D0
SCI1BDL 0x00D1
SCI1CR1 0x00D2
SCI1CR2 0x00D3
SCI1SR1 0x00D4
SCI1SR2 0x00D5
SCI1DRH 0x00D6
SCI1DRL 0x00D7
SPI0CR1 0x00D8
SPI0CR2 0x00D9
SPI0BR 0x00DA
SPI0SR 0x00DB
SPI0DR 0x00DD
IBAD 0x00E0
IBFD 0x00E1
IBCR 0x00E2
IBSR 0x00E3
IBDR 0x00E4
DLCBCR1 0x00E8
DLCBSVR 0x00E9
DLCBCR2 0x00EA
DLCBDR 0x00EB
DLCBARD 0x00EC
DLCBRSR 0x00ED
DLCSCR 0x00EE
DLCBSTAT 0x00EF
SPI1CR1 0x00F0
SPI1CR2 0x00F1
SPI1BR 0x00F2
SPI1SR 0x00F3
SPI1DR 0x00F5
SPI2CR1 0x00F8
SPI2CR2 0x00F9
SPI2BR 0x00FA
SPI2SR 0x00FB
SPI2DR 0x00FD
FCLKDIV 0x0100
FSEC 0x0101
FTSTMOD 0x0102
FCNFG 0x0103
FPROT 0x0104
FSTAT 0x0105
FCMD 0x0106
FADDRHI 0x0108
FADDRLO 0x0109
FDATAHI 0x010A
FDATALO 0x010B
ECLKDIV 0x0110
ECNFG 0x0113
EPROT 0x0114
ESTAT 0x0115
ECMD 0x0116
EADDRHI 0x0118
EADDRLO 0x0119
EDATAHI 0x011A
EDATALO 0x011B
ATD1CTL0 0x0120
ATD1CTL1 0x0121
ATD1CTL2 0x0122
ATD1CTL3 0x0123
ATD1CTL4 0x0124
ATD1CTL5 0x0125
ATD1STAT0 0x0126
ATD1TEST0 0x0128
ATD1TEST1 0x0129
ATD1STAT1 0x012B
ATD1DIEN 0x012D
PORTAD1 0x012F
ATD1DR0H 0x0130
ATD1DR0L 0x0131
ATD1DR1H 0x0132
ATD1DR1L 0x0133
ATD1DR2H 0x0134
ATD1DR2L 0x0135
ATD1DR3H 0x0136
ATD1DR3L 0x0137
ATD1DR4H 0x0138
ATD1DR4L 0x0139
ATD1DR5H 0x013A
ATD1DR5L 0x013B
ATD1DR6H 0x013C
ATD1DR6L 0x013D
ATD1DR7H 0x013E
ATD1DR7L 0x013F
CAN0CTL0 0x0140
CAN0CTL1 0x0141
CAN0BTR0 0x0142
CAN0BTR1 0x0143
CAN0RFLG 0x0144
CAN0RIER 0x0145
CAN0TFLG 0x0146
CAN0TIER 0x0147
CAN0TARQ 0x0148
CAN0TAAK 0x0149
CAN0TBSEL 0x014A
CAN0IDAC 0x014B
CAN0RXERR 0x014E
CAN0TXERR 0x014F
CAN0IDAR0_CAN0IDAR3 0x0150
CAN0IDMR0_CAN0IDMR3 0x0154
CAN0IDAR4_CAN0IDAR7 0x0158
CAN0IDMR4_CAN0IDMR7 0x015C
CAN0RXFG 0x0160
CAN0TXFG 0x0170
CAN1CTL0 0x0180
CAN1CTL1 0x0181
CAN1BTR0 0x0182
CAN1BTR1 0x0183
CAN1RFLG 0x0184
CAN1RIER 0x0185
CAN1TFLG 0x0186
CAN1TIER 0x0187
CAN1TARQ 0x0188
CAN1TAAK 0x0189
CAN1TBSEL 0x018A
CAN1IDAC 0x018B
CAN1RXERR 0x018E
CAN1TXERR 0x018F
CAN1IDAR0 0x0190
CAN1IDAR1 0x0191
CAN1IDAR2 0x0192
CAN1IDAR3 0x0193
CAN1IDMR0 0x0194
CAN1IDMR1 0x0195
CAN1IDMR2 0x0196
CAN1IDMR3 0x0197
CAN1IDAR4 0x0198
CAN1IDAR5 0x0199
CAN1IDAR6 0x019A
CAN1IDAR7 0x019B
CAN1IDMR4 0x019C
CAN1IDMR5 0x019D
CAN1IDMR6 0x019E
CAN1IDMR7 0x019F
CAN1RXFG 0x01A0
CAN1TXFG 0x01B0
PTT 0x0240
PTIT 0x0241
DDRT 0x0242
RDRT 0x0243
PERT 0x0244
PPST 0x0245
PTS 0x0248
PTIS 0x0249
DDRS 0x024A
RDRS 0x024B
PERS 0x024C
PPSS 0x024D
WOMS 0x024E
PTM 0x0250
PTIM 0x0251
DDRM 0x0252
RDRM 0x0253
PERM 0x0254
PPSM 0x0255
WOMM 0x0256
MODRR 0x0257
PTP 0x0258
PTIP 0x0259
DDRP 0x025A
RDRP 0x025B
PERP 0x025C
PPSP 0x025D
PIEP 0x025E
PIFP 0x025F
PTH 0x0260
PTIH 0x0261
DDRH 0x0262
RDRH 0x0263
PERH 0x0264
PPSH 0x0265
PIEH 0x0266
PIFH 0x0267
PTJ 0x0268
PTIJ 0x0269
DDRJ 0x026A
RDRJ 0x026B
PERJ 0x026C
PPSJ 0x026D
PIEJ 0x026E
PIFJ 0x026F
CAN4CTL0 0x0280
CAN4CTL1 0x0281
CAN4BTR0 0x0282
CAN4BTR1 0x0283
CAN4RFLG 0x0284
CAN4RIER 0x0285
CAN4TFLG 0x0286
CAN4TIER 0x0287
CAN4TARQ 0x0288
CAN4TAAK 0x0289
CAN4TBSEL 0x028A
CAN4IDAC 0x028B
CAN4RXERR 0x028E
CAN4TXERR 0x028F
CAN4IDAR0 0x0290
CAN4IDAR1 0x0291
CAN4IDAR2 0x0292
CAN4IDAR3 0x0293
CAN4IDMR0 0x0294
CAN4IDMR1 0x0295
CAN4IDMR2 0x0296
CAN4IDMR3 0x0297
CAN4IDAR4 0x0298
CAN4IDAR5 0x0299
CAN4IDAR6 0x029A
CAN4IDAR7 0x029B
CAN4IDMR4 0x029C
CAN4IDMR5 0x029D
CAN4IDMR6 0x029E
CAN4IDMR7 0x029F
CAN4RXFG 0x02A0
CAN4TXFG 0x02B0
;----------------------------------------------------------------------------
.MC9S12A128
.MC9S12A512
.MC9S12E64
.MC9S12E128
.MC9S12NE64
.MC9S12UF32
.MC9S12A128B
; MEMORY MAP
area DATA FSR 0x0000:0x0400
area BSS RESERVED 0x0400:0x0800
area DATA EEPROM_ 0x0800:0x1000
area BSS RESERVED 0x1000:0x2000
area DATA RAM_ 0x2000:0x4000
area BSS RESERVED 0x4000:0xFF00
area DATA USER_VEC 0xFF00:0x10000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Power-on reset
interrupt PLLCTL_ 0xFFFC Clock Monitor fail reset
interrupt COP_ 0xFFFA COP rate select
interrupt SWI_ 0xFFF6 SWI
interrupt XIRQ_ 0xFFF4 XIRQ
interrupt IRQCR_IRQEN 0xFFF2 IRQ
interrupt CRGINT_RTIE 0xFFF0 Real Time Interrupt
interrupt TIE_C0I 0xFFEE Enhanced Capture Timer channel 0
interrupt TIE_C1I 0xFFEC Enhanced Capture Timer channel 1
interrupt TIE_C2I 0xFFEA Enhanced Capture Timer channel 2
interrupt TIE_C3I 0xFFE8 Enhanced Capture Timer channel 3
interrupt TIE_C4I 0xFFE6 Enhanced Capture Timer channel 4
interrupt TIE_C5I 0xFFE4 Enhanced Capture Timer channel 5
interrupt TIE_C6I 0xFFE2 Enhanced Capture Timer channel 6
interrupt TIE_C7I 0xFFE0 Enhanced Capture Timer channel 7
interrupt TSRC2_TOF 0xFFDE Enhanced Capture Timer overflow
interrupt PACTL_PAOVI 0xFFDC Pulse accumulator A overflow
interrupt PACTL_PAI 0xFFDA Pulse accumulator input edge
interrupt SP0CR1_ 0xFFD8 SPI0
interrupt SC0CR2_ 0xFFD6 SCI0
interrupt SC1CR2_ 0xFFD4 SCI1
interrupt ATD0CTL2_ 0xFFD2 ATD0
interrupt ATD1CTL2_ 0xFFD0 ATD1
interrupt PTJIF_PTJIE 0xFFCE Port J
interrupt PTHIF_PTHIE 0xFFCC Port H
interrupt MCCTL_MCZI 0xFFCA Modulus Down Counter underflow
interrupt PBCTL_PBOVI 0xFFC8 Pulse Accumulator B Overflow
interrupt CRGINT_LOCKIE 0xFFC6 CRG PLL lock
interrupt CRGINT_SCMIE 0xFFC4 CRG Self Clock Mode
interrupt IBCR_IBIE 0xFFC0 IIC Bus
interrupt SP1CR1_ 0xFFBE SPI1
interrupt EECTL_ 0xFFBA EEPROM
interrupt FCTL_ 0xFFB8 FLASH
interrupt PTPIF_PTPIE 0xFF8E Port P Interrupt
interrupt PWMSDN_PWMIE 0xFF8C PWM Emergency Shutdown
; INPUT/ OUTPUT PORTS
; Port Integration Module
PTT 0x0000 Port T I/O Register
PTT.PTT7 7 Port T I/O Register bit 7
PTT.PTT6 6 Port T I/O Register bit 6
PTT.PTT5 5 Port T I/O Register bit 5
PTT.PTT4 4 Port T I/O Register bit 4
PTT.PTT3 3 Port T I/O Register bit 3
PTT.PTT2 2 Port T I/O Register bit 2
PTT.PTT1 1 Port T I/O Register bit 1
PTT.PTT0 0 Port T I/O Register bit 0
PTIT 0x0001 Port T Input Register
PTIT.PTIT7 7 Port T Input Register bit 7
PTIT.PTIT6 6 Port T Input Register bit 6
PTIT.PTIT5 5 Port T Input Register bit 5
PTIT.PTIT4 4 Port T Input Register bit 4
PTIT.PTIT3 3 Port T Input Register bit 3
PTIT.PTIT2 2 Port T Input Register bit 2
PTIT.PTIT1 1 Port T Input Register bit 1
PTIT.PTIT0 0 Port T Input Register bit 0
DDRT 0x0002 Port T Data Direction Register
DDRT.DDRT7 7 Data Direction Port T bit 7
DDRT.DDRT6 6 Data Direction Port T bit 6
DDRT.DDRT5 5 Data Direction Port T bit 5
DDRT.DDRT4 4 Data Direction Port T bit 4
DDRT.DDRT3 3 Data Direction Port T bit 3
DDRT.DDRT2 2 Data Direction Port T bit 2
DDRT.DDRT1 1 Data Direction Port T bit 1
DDRT.DDRT0 0 Data Direction Port T bit 0
RDRT 0x0003 Port T Reduced Drive Register
RDRT.RDRT7 7 Reduced Drive Port T bit 7
RDRT.RDRT6 6 Reduced Drive Port T bit 6
RDRT.RDRT5 5 Reduced Drive Port T bit 5
RDRT.RDRT4 4 Reduced Drive Port T bit 4
RDRT.RDRT3 3 Reduced Drive Port T bit 3
RDRT.RDRT2 2 Reduced Drive Port T bit 2
RDRT.RDRT1 1 Reduced Drive Port T bit 1
RDRT.RDRT0 0 Reduced Drive Port T bit 0
PERT 0x0004 Port T Pull Device Enable Register
PERT.PERT7 7 Pull Device Enable Port T bit 7
PERT.PERT6 6 Pull Device Enable Port T bit 6
PERT.PERT5 5 Pull Device Enable Port T bit 5
PERT.PERT4 4 Pull Device Enable Port T bit 4
PERT.PERT3 3 Pull Device Enable Port T bit 3
PERT.PERT2 2 Pull Device Enable Port T bit 2
PERT.PERT1 1 Pull Device Enable Port T bit 1
PERT.PERT0 0 Pull Device Enable Port T bit 0
PPST 0x0005 Port T Polarity Select Register
PPST.PPST7 7 Pull Select Port T bit 7
PPST.PPST6 6 Pull Select Port T bit 6
PPST.PPST5 5 Pull Select Port T bit 5
PPST.PPST4 4 Pull Select Port T bit 4
PPST.PPST3 3 Pull Select Port T bit 3
PPST.PPST2 2 Pull Select Port T bit 2
PPST.PPST1 1 Pull Select Port T bit 1
PPST.PPST0 0 Pull Select Port T bit 0
RESERVED0006 0x0006 RESERVED
RESERVED0007 0x0007 RESERVED
PTS 0x0008 Port S I/O Register
PTS.PTS7 7 Port S I/O Register bit 7
PTS.PTS6 6 Port S I/O Register bit 6
PTS.PTS5 5 Port S I/O Register bit 5
PTS.PTS4 4 Port S I/O Register bit 4
PTS.PTS3 3 Port S I/O Register bit 3
PTS.PTS2 2 Port S I/O Register bit 2
PTS.PTS1 1 Port S I/O Register bit 1
PTS.PTS0 0 Port S I/O Register bit 0
PTIS 0x0009 Port S Input Register
PTIS.PTIS7 7 Port S Input Register bit 7
PTIS.PTIS6 6 Port S Input Register bit 6
PTIS.PTIS5 5 Port S Input Register bit 5
PTIS.PTIS4 4 Port S Input Register bit 4
PTIS.PTIS3 3 Port S Input Register bit 3
PTIS.PTIS2 2 Port S Input Register bit 2
PTIS.PTIS1 1 Port S Input Register bit 1
PTIS.PTIS0 0 Port S Input Register bit 0
DDRS 0x000A Port S Data Direction Register
DDRS.DDRS7 7 Data Direction Port S bit 7
DDRS.DDRS6 6 Data Direction Port S bit 6
DDRS.DDRS5 5 Data Direction Port S bit 5
DDRS.DDRS4 4 Data Direction Port S bit 4
DDRS.DDRS3 3 Data Direction Port S bit 3
DDRS.DDRS2 2 Data Direction Port S bit 2
DDRS.DDRS1 1 Data Direction Port S bit 1
DDRS.DDRS0 0 Data Direction Port S bit 0
RDRS 0x000B Port S Reduced Drive Register
RDRS.RDRS7 7 Reduced Drive Port S bit 7
RDRS.RDRS6 6 Reduced Drive Port S bit 6
RDRS.RDRS5 5 Reduced Drive Port S bit 5
RDRS.RDRS4 4 Reduced Drive Port S bit 4
RDRS.RDRS3 3 Reduced Drive Port S bit 3
RDRS.RDRS2 2 Reduced Drive Port S bit 2
RDRS.RDRS1 1 Reduced Drive Port S bit 1
RDRS.RDRS0 0 Reduced Drive Port S bit 0
PERS 0x000C Port S Pull Device Enable Register
PERS.PERS7 7 Pull Device Enable Port S bit 7
PERS.PERS6 6 Pull Device Enable Port S bit 6
PERS.PERS5 5 Pull Device Enable Port S bit 5
PERS.PERS4 4 Pull Device Enable Port S bit 4
PERS.PERS3 3 Pull Device Enable Port S bit 3
PERS.PERS2 2 Pull Device Enable Port S bit 2
PERS.PERS1 1 Pull Device Enable Port S bit 1
PERS.PERS0 0 Pull Device Enable Port S bit 0
PPSS 0x000D Port S Polarity Select Register
PPSS.PPSS7 7 Pull Select Port S bit 7
PPSS.PPSS6 6 Pull Select Port S bit 6
PPSS.PPSS5 5 Pull Select Port S bit 5
PPSS.PPSS4 4 Pull Select Port S bit 4
PPSS.PPSS3 3 Pull Select Port S bit 3
PPSS.PPSS2 2 Pull Select Port S bit 2
PPSS.PPSS1 1 Pull Select Port S bit 1
PPSS.PPSS0 0 Pull Select Port S bit 0
WOMS 0x000E Port S Wired-OR Mode Register
WOMS.WOMS7 7 Wired-OR Mode Port S bit 7
WOMS.WOMS6 6 Wired-OR Mode Port S bit 6
WOMS.WOMS5 5 Wired-OR Mode Port S bit 5
WOMS.WOMS4 4 Wired-OR Mode Port S bit 4
WOMS.WOMS3 3 Wired-OR Mode Port S bit 3
WOMS.WOMS2 2 Wired-OR Mode Port S bit 2
WOMS.WOMS1 1 Wired-OR Mode Port S bit 1
WOMS.WOMS0 0 Wired-OR Mode Port S bit 0
RESERVED000F 0x000F RESERVED
PTM 0x0010 Port M I/O Register
PTM.PTM7 7 Port M I/O Register bit 7
PTM.PTM6 6 Port M I/O Register bit 6
PTM.PTM5 5 Port M I/O Register bit 5
PTM.PTM4 4 Port M I/O Register bit 4
PTM.PTM3 3 Port M I/O Register bit 3
PTM.PTM2 2 Port M I/O Register bit 2
PTM.PTM1 1 Port M I/O Register bit 1
PTM.PTM0 0 Port M I/O Register bit 0
PTIM 0x0011 Port M Input Register
PTIM.PTIM7 7 Port M Input Register bit 7
PTIM.PTIM6 6 Port M Input Register bit 6
PTIM.PTIM5 5 Port M Input Register bit 5
PTIM.PTIM4 4 Port M Input Register bit 4
PTIM.PTIM3 3 Port M Input Register bit 3
PTIM.PTIM2 2 Port M Input Register bit 2
PTIM.PTIM1 1 Port M Input Register bit 1
PTIM.PTIM0 0 Port M Input Register bit 0
DDRM 0x0012 Port M Data Direction Register
DDRM.DDRM7 7 Data Direction Port M bit 7
DDRM.DDRM6 6 Data Direction Port M bit 6
DDRM.DDRM5 5 Data Direction Port M bit 5
DDRM.DDRM4 4 Data Direction Port M bit 4
DDRM.DDRM3 3 Data Direction Port M bit 3
DDRM.DDRM2 2 Data Direction Port M bit 2
DDRM.DDRM1 1 Data Direction Port M bit 1
DDRM.DDRM0 0 Data Direction Port M bit 0
RDRM 0x0013 Port M Reduced Drive Register
RDRM.RDRM7 7 Reduced Drive Port M bit 7
RDRM.RDRM6 6 Reduced Drive Port M bit 6
RDRM.RDRM5 5 Reduced Drive Port M bit 5
RDRM.RDRM4 4 Reduced Drive Port M bit 4
RDRM.RDRM3 3 Reduced Drive Port M bit 3
RDRM.RDRM2 2 Reduced Drive Port M bit 2
RDRM.RDRM1 1 Reduced Drive Port M bit 1
RDRM.RDRM0 0 Reduced Drive Port M bit 0
PERM 0x0014 Port M Pull Device Enable Register
PERM.PERM7 7 Pull Device Enable Port M bit 7
PERM.PERM6 6 Pull Device Enable Port M bit 6
PERM.PERM5 5 Pull Device Enable Port M bit 5
PERM.PERM4 4 Pull Device Enable Port M bit 4
PERM.PERM3 3 Pull Device Enable Port M bit 3
PERM.PERM2 2 Pull Device Enable Port M bit 2
PERM.PERM1 1 Pull Device Enable Port M bit 1
PERM.PERM0 0 Pull Device Enable Port M bit 0
PPSM 0x0015 Port M Polarity Select Register
PPSM.PPSM7 7 Pull Select Port M bit 7
PPSM.PPSM6 6 Pull Select Port M bit 6
PPSM.PPSM5 5 Pull Select Port M bit 5
PPSM.PPSM4 4 Pull Select Port M bit 4
PPSM.PPSM3 3 Pull Select Port M bit 3
PPSM.PPSM2 2 Pull Select Port M bit 2
PPSM.PPSM1 1 Pull Select Port M bit 1
PPSM.PPSM0 0 Pull Select Port M bit 0
WOMM 0x0016 Port M Wired-OR Mode Register
WOMM.WOMM7 7 Wired-OR Mode Port M bit 7
WOMM.WOMM6 6 Wired-OR Mode Port M bit 6
WOMM.WOMM5 5 Wired-OR Mode Port M bit 5
WOMM.WOMM4 4 Wired-OR Mode Port M bit 4
WOMM.WOMM3 3 Wired-OR Mode Port M bit 3
WOMM.WOMM2 2 Wired-OR Mode Port M bit 2
WOMM.WOMM1 1 Wired-OR Mode Port M bit 1
WOMM.WOMM0 0 Wired-OR Mode Port M bit 0
MODRR 0x0017 Module Routing Register
MODRR.MODRR5 5 SPI1 Routing
MODRR.MODRR4 4 SPI0 Routing
PTP 0x0018 Port P I/O Register
PTP.PTP7 7 Port P I/O Register bit 7
PTP.PTP6 6 Port P I/O Register bit 6
PTP.PTP5 5 Port P I/O Register bit 5
PTP.PTP4 4 Port P I/O Register bit 4
PTP.PTP3 3 Port P I/O Register bit 3
PTP.PTP2 2 Port P I/O Register bit 2
PTP.PTP1 1 Port P I/O Register bit 1
PTP.PTP0 0 Port P I/O Register bit 0
PTIP 0x0019 Port P Input Register
PTIP.PTIP7 7 Port P Input Register bit 7
PTIP.PTIP6 6 Port P Input Register bit 6
PTIP.PTIP5 5 Port P Input Register bit 5
PTIP.PTIP4 4 Port P Input Register bit 4
PTIP.PTIP3 3 Port P Input Register bit 3
PTIP.PTIP2 2 Port P Input Register bit 2
PTIP.PTIP1 1 Port P Input Register bit 1
PTIP.PTIP0 0 Port P Input Register bit 0
DDRP 0x001A Port P Data Direction Register
DDRP.DDRP7 7 Data Direction Port P bit 7
DDRP.DDRP6 6 Data Direction Port P bit 6
DDRP.DDRP5 5 Data Direction Port P bit 5
DDRP.DDRP4 4 Data Direction Port P bit 4
DDRP.DDRP3 3 Data Direction Port P bit 3
DDRP.DDRP2 2 Data Direction Port P bit 2
DDRP.DDRP1 1 Data Direction Port P bit 1
DDRP.DDRP0 0 Data Direction Port P bit 0
RDRP 0x001B Port P Reduced Drive Register
RDRP.RDRP7 7 Reduced Drive Port P bit 7
RDRP.RDRP6 6 Reduced Drive Port P bit 6
RDRP.RDRP5 5 Reduced Drive Port P bit 5
RDRP.RDRP4 4 Reduced Drive Port P bit 4
RDRP.RDRP3 3 Reduced Drive Port P bit 3
RDRP.RDRP2 2 Reduced Drive Port P bit 2
RDRP.RDRP1 1 Reduced Drive Port P bit 1
RDRP.RDRP0 0 Reduced Drive Port P bit 0
PERP 0x001C Port P Pull Device Enable Register
PERP.PERP7 7 Pull Device Enable Port P bit 7
PERP.PERP6 6 Pull Device Enable Port P bit 6
PERP.PERP5 5 Pull Device Enable Port P bit 5
PERP.PERP4 4 Pull Device Enable Port P bit 4
PERP.PERP3 3 Pull Device Enable Port P bit 3
PERP.PERP2 2 Pull Device Enable Port P bit 2
PERP.PERP1 1 Pull Device Enable Port P bit 1
PERP.PERP0 0 Pull Device Enable Port P bit 0
PPSP 0x001D Port P Polarity Select Register
PPSP.PPSP7 7 Polarity Select Port P bit 7
PPSP.PPSP6 6 Polarity Select Port P bit 6
PPSP.PPSP5 5 Polarity Select Port P bit 5
PPSP.PPSP4 4 Polarity Select Port P bit 4
PPSP.PPSP3 3 Polarity Select Port P bit 3
PPSP.PPSP2 2 Polarity Select Port P bit 2
PPSP.PPSP1 1 Polarity Select Port P bit 1
PPSP.PPSP0 0 Polarity Select Port P bit 0
PIEP 0x001E Port P Interrupt Enable Register
PIEP.PIEP7 7 Interrupt Enable Port P bit 7
PIEP.PIEP6 6 Interrupt Enable Port P bit 6
PIEP.PIEP5 5 Interrupt Enable Port P bit 5
PIEP.PIEP4 4 Interrupt Enable Port P bit 4
PIEP.PIEP3 3 Interrupt Enable Port P bit 3
PIEP.PIEP2 2 Interrupt Enable Port P bit 2
PIEP.PIEP1 1 Interrupt Enable Port P bit 1
PIEP.PIEP0 0 Interrupt Enable Port P bit 0
PIFP 0x001F Port P Interrupt Flag Register
PIFP.PIFP7 7 Interrupt Flags Port P bit 7
PIFP.PIFP6 6 Interrupt Flags Port P bit 6
PIFP.PIFP5 5 Interrupt Flags Port P bit 5
PIFP.PIFP4 4 Interrupt Flags Port P bit 4
PIFP.PIFP3 3 Interrupt Flags Port P bit 3
PIFP.PIFP2 2 Interrupt Flags Port P bit 2
PIFP.PIFP1 1 Interrupt Flags Port P bit 1
PIFP.PIFP0 0 Interrupt Flags Port P bit 0
PTH 0x0020 Port H I/O Register
PTH.PTH7 7 Port H I/O Register bit 7
PTH.PTH6 6 Port H I/O Register bit 6
PTH.PTH5 5 Port H I/O Register bit 5
PTH.PTH4 4 Port H I/O Register bit 4
PTH.PTH3 3 Port H I/O Register bit 3
PTH.PTH2 2 Port H I/O Register bit 2
PTH.PTH1 1 Port H I/O Register bit 1
PTH.PTH0 0 Port H I/O Register bit 0
PTIH 0x0021 Port H Input Register
PTIH.PTIH7 7 Port H Input Register bit 7
PTIH.PTIH6 6 Port H Input Register bit 6
PTIH.PTIH5 5 Port H Input Register bit 5
PTIH.PTIH4 4 Port H Input Register bit 4
PTIH.PTIH3 3 Port H Input Register bit 3
PTIH.PTIH2 2 Port H Input Register bit 2
PTIH.PTIH1 1 Port H Input Register bit 1
PTIH.PTIH0 0 Port H Input Register bit 0
DDRH 0x0022 Port H Data Direction Register
DDRH.DDRH7 7 Data Direction Port H bit 7
DDRH.DDRH6 6 Data Direction Port H bit 6
DDRH.DDRH5 5 Data Direction Port H bit 5
DDRH.DDRH4 4 Data Direction Port H bit 4
DDRH.DDRH3 3 Data Direction Port H bit 3
DDRH.DDRH2 2 Data Direction Port H bit 2
DDRH.DDRH1 1 Data Direction Port H bit 1
DDRH.DDRH0 0 Data Direction Port H bit 0
RDRH 0x0023 Port H Reduced Drive Register
RDRH.RDRH7 7 Reduced Drive Port H bit 7
RDRH.RDRH6 6 Reduced Drive Port H bit 6
RDRH.RDRH5 5 Reduced Drive Port H bit 5
RDRH.RDRH4 4 Reduced Drive Port H bit 4
RDRH.RDRH3 3 Reduced Drive Port H bit 3
RDRH.RDRH2 2 Reduced Drive Port H bit 2
RDRH.RDRH1 1 Reduced Drive Port H bit 1
RDRH.RDRH0 0 Reduced Drive Port H bit 0
PERH 0x0024 Port H Pull Device Enable Register
PERH.PERH7 7 Pull Device Enable Port H bit 7
PERH.PERH6 6 Pull Device Enable Port H bit 6
PERH.PERH5 5 Pull Device Enable Port H bit 5
PERH.PERH4 4 Pull Device Enable Port H bit 4
PERH.PERH3 3 Pull Device Enable Port H bit 3
PERH.PERH2 2 Pull Device Enable Port H bit 2
PERH.PERH1 1 Pull Device Enable Port H bit 1
PERH.PERH0 0 Pull Device Enable Port H bit 0
PPSH 0x0025 Port H Polarity Select Register
PPSH.PPSH7 7 Polarity Select Port H bit 7
PPSH.PPSH6 6 Polarity Select Port H bit 6
PPSH.PPSH5 5 Polarity Select Port H bit 5
PPSH.PPSH4 4 Polarity Select Port H bit 4
PPSH.PPSH3 3 Polarity Select Port H bit 3
PPSH.PPSH2 2 Polarity Select Port H bit 2
PPSH.PPSH1 1 Polarity Select Port H bit 1
PPSH.PPSH0 0 Polarity Select Port H bit 0
PIEH 0x0026 Port H Interrupt Enable Register
PIEH.PIEH7 7 Interrupt Enable Port H bit 7
PIEH.PIEH6 6 Interrupt Enable Port H bit 6
PIEH.PIEH5 5 Interrupt Enable Port H bit 5
PIEH.PIEH4 4 Interrupt Enable Port H bit 4
PIEH.PIEH3 3 Interrupt Enable Port H bit 3
PIEH.PIEH2 2 Interrupt Enable Port H bit 2
PIEH.PIEH1 1 Interrupt Enable Port H bit 1
PIEH.PIEH0 0 Interrupt Enable Port H bit 0
PIFH 0x0027 Port H Interrupt Flag Register
PIFH.PIFH7 7 Interrupt Flags Port H bit 7
PIFH.PIFH6 6 Interrupt Flags Port H bit 6
PIFH.PIFH5 5 Interrupt Flags Port H bit 5
PIFH.PIFH4 4 Interrupt Flags Port H bit 4
PIFH.PIFH3 3 Interrupt Flags Port H bit 3
PIFH.PIFH2 2 Interrupt Flags Port H bit 2
PIFH.PIFH1 1 Interrupt Flags Port H bit 1
PIFH.PIFH0 0 Interrupt Flags Port H bit 0
PTJ 0x0028 Port J I/O Register
PTJ.PTJ7 7 Port J I/O Register bit 7
PTJ.PTJ6 6 Port J I/O Register bit 6
PTJ.PTJ1 1 Port J I/O Register bit 1
PTJ.PTJ0 0 Port J I/O Register bit 0
PTIJ 0x0029 Port J Input Register
PTIJ.PTIJ7 7 Port J Input Register bit 7
PTIJ.PTIJ6 6 Port J Input Register bit 6
PTIJ.PTIJ1 1 Port J Input Register bit 1
PTIJ.PTIJ0 0 Port J Input Register bit 0
DDRJ 0x002A Port J Data Direction Register
DDRJ.DDRJ7 7 Data Direction Port J bit 7
DDRJ.DDRJ6 6 Data Direction Port J bit 6
DDRJ.DDRJ1 1 Data Direction Port J bit 1
DDRJ.DDRJ0 0 Data Direction Port J bit 0
RDRJ 0x002B Port J Reduced Drive Register
RDRJ.RDRJ7 7 Reduced Drive Port J bit 7
RDRJ.RDRJ6 6 Reduced Drive Port J bit 6
RDRJ.RDRJ1 1 Reduced Drive Port J bit 1
RDRJ.RDRJ0 0 Reduced Drive Port J bit 0
PERJ 0x002C Port J Pull Device Enable Register
PERJ.PERJ7 7 Pull Device Enable Port J bit 7
PERJ.PERJ6 6 Pull Device Enable Port J bit 6
PERJ.PERJ1 1 Pull Device Enable Port J bit 1
PERJ.PERJ0 0 Pull Device Enable Port J bit 0
PPSJ 0x002D Port J Polarity Select Register
PPSJ.PPSJ7 7 Polarity Select Port J bit 7
PPSJ.PPSJ6 6 Polarity Select Port J bit 6
PPSJ.PPSJ1 1 Polarity Select Port J bit 1
PPSJ.PPSJ0 0 Polarity Select Port J bit 0
PIEJ 0x002E Port J Interrupt Enable Register
PIEJ.PIEJ7 7 Interrupt Enable Port J bit 7
PIEJ.PIEJ6 6 Interrupt Enable Port J bit 6
PIEJ.PIEJ1 1 Interrupt Enable Port J bit 1
PIEJ.PIEJ0 0 Interrupt Enable Port J bit 0
PIFJ 0x002F Port J Interrupt Flag Register
PIFJ.PIFJ7 7 Interrupt Flags Port J bit 7
PIFJ.PIFJ6 6 Interrupt Flags Port J bit 6
PIFJ.PIFJ1 1 Interrupt Flags Port J bit 1
PIFJ.PIFJ0 0 Interrupt Flags Port J bit 0
RESERVED0030 0x0030 RESERVED
RESERVED0031 0x0031 RESERVED
RESERVED0032 0x0032 RESERVED
RESERVED0033 0x0033 RESERVED
RESERVED0034 0x0034 RESERVED
RESERVED0035 0x0035 RESERVED
RESERVED0036 0x0036 RESERVED
RESERVED0037 0x0037 RESERVED
RESERVED0038 0x0038 RESERVED
RESERVED0039 0x0039 RESERVED
RESERVED003A 0x003A RESERVED
RESERVED003B 0x003B RESERVED
RESERVED003C 0x003C RESERVED
RESERVED003D 0x003D RESERVED
RESERVED003E 0x003E RESERVED
RESERVED003F 0x003F RESERVED
; ATD_10B8C registers
ATDCTL0 0x0000 ATD Control Register 0
ATDCTL1 0x0001 ATD Control Register 1
ATDCTL2 0x0002 ATD Control Register 2
ATDCTL2.ADPU 7 ATD Power Down
ATDCTL2.AFFC 6 ATD Fast Flag Clear All
ATDCTL2.AWAI 5 ATD Power Down in Wait Mode
ATDCTL2.ETRIGLE 4 External Trigger Level/Edge Control
ATDCTL2.ETRIGP 3 External Trigger Polarity
ATDCTL2.ETRIGE 2 External Trigger Mode Enable
ATDCTL2.ASCIE 1 ATD Sequence Complete Interrupt Enable
ATDCTL2.ASCIF 0 ATD Sequence Complete Interrupt Flag
ATDCTL3 0x0003 ATD Control Register 3
ATDCTL3.S8C 6 S8C - Conversion Sequence Length
ATDCTL3.S4C 5 S4C - Conversion Sequence Length
ATDCTL3.S2C 4 S2C - Conversion Sequence Length
ATDCTL3.S1C 3 S1C - Conversion Sequence Length
ATDCTL3.FIFO 2 Result Register FIFO Mode
ATDCTL3.FRZ1 1 Background Debug Freeze Enable bit 1
ATDCTL3.FRZ0 0 Background Debug Freeze Enable bit 0
ATDCTL4 0x0004 ATD Control Register 4
ATDCTL4.SRES8 7 A/D Resolution Select
ATDCTL4.SMP1 6 Sample Time Select bit 1
ATDCTL4.SMP0 5 Sample Time Select bit 0
ATDCTL4.PRS4 4 ATD Clock Prescaler bit 4
ATDCTL4.PRS3 3 ATD Clock Prescaler bit 3
ATDCTL4.PRS2 2 ATD Clock Prescaler bit 2
ATDCTL4.PRS1 1 ATD Clock Prescaler bit 1
ATDCTL4.PRS0 0 ATD Clock Prescaler bit 0
ATDCTL5 0x0005 ATD Control Register 5
ATDCTL5.DJM 7 Result Register Data Justification
ATDCTL5.DSGN 6 Result Register Data Signed or Unsigned Representation
ATDCTL5.SCAN 5 Continuous Conversion Sequence Mode
ATDCTL5.MULT 4 Multi-Channel Sample Mode
ATDCTL5.CC 2 CC - Analog Input Channel Select Code
ATDCTL5.CB 1 CB - Analog Input Channel Select Code
ATDCTL5.CA 0 CA - Analog Input Channel Select Code
ATDSTAT0 0x0006 ATD Status Register 0
ATDSTAT0.SCF 7 Sequence Complete Flag
ATDSTAT0.ETORF 5 External Trigger Overrun Flag
ATDSTAT0.FIFOR 4 FIFO Over Run Flag
ATDSTAT0.CC2 2 Conversion Counter bit 2
ATDSTAT0.CC1 1 Conversion Counter bit 1
ATDSTAT0.CC0 0 Conversion Counter bit 0
RESERVED0007 0x0007 RESERVED
ATDTEST0 0x0008 ATD Test Register 0
ATDTEST1 0x0009 ATD Test Register 1
RESERVED000A 0x000A RESERVED
ATDSTAT1 0x000B ATD Status Register 1
ATDSTAT1.CCF7 7 Conversion Complete Flag 7
ATDSTAT1.CCF6 6 Conversion Complete Flag 6
ATDSTAT1.CCF5 5 Conversion Complete Flag 5
ATDSTAT1.CCF4 4 Conversion Complete Flag 4
ATDSTAT1.CCF3 3 Conversion Complete Flag 3
ATDSTAT1.CCF2 2 Conversion Complete Flag 2
ATDSTAT1.CCF1 1 Conversion Complete Flag 1
ATDSTAT1.CCF0 0 Conversion Complete Flag 0
RESERVED000C 0x000C RESERVED
ATDDIEN 0x000D ATD Input Enable Register
ATDDIEN.IEN7 7 ATD Digital Input Enable on channel bit 7
ATDDIEN.IEN6 6 ATD Digital Input Enable on channel bit 6
ATDDIEN.IEN5 5 ATD Digital Input Enable on channel bit 5
ATDDIEN.IEN4 4 ATD Digital Input Enable on channel bit 4
ATDDIEN.IEN3 3 ATD Digital Input Enable on channel bit 3
ATDDIEN.IEN2 2 ATD Digital Input Enable on channel bit 2
ATDDIEN.IEN1 1 ATD Digital Input Enable on channel bit 1
ATDDIEN.IEN0 0 ATD Digital Input Enable on channel bit 0
RESERVED000E 0x000E RESERVED
PORTAD 0x000F Port Data Register
PORTAD.PTAD7 7 A/D Channel 7 (AN7) Digital Input
PORTAD.PTAD6 6 A/D Channel 6 (AN6) Digital Input
PORTAD.PTAD5 5 A/D Channel 5 (AN5) Digital Input
PORTAD.PTAD4 4 A/D Channel 4 (AN4) Digital Input
PORTAD.PTAD3 3 A/D Channel 3 (AN3) Digital Input
PORTAD.PTAD2 2 A/D Channel 2 (AN2) Digital Input
PORTAD.PTAD1 1 A/D Channel 1 (AN1) Digital Input
PORTAD.PTAD0 0 A/D Channel 0 (AN0) Digital Input
ATDDR0H 0x0010 ATD Result Register 0 H
ATDDR0L 0x0011 ATD Result Register 0 L
ATDDR1H 0x0012 ATD Result Register 1 H
ATDDR1L 0x0013 ATD Result Register 1 L
ATDDR2H 0x0014 ATD Result Register 2 H
ATDDR2L 0x0015 ATD Result Register 2 L
ATDDR3H 0x0016 ATD Result Register 3 H
ATDDR3L 0x0017 ATD Result Register 3 L
ATDDR4H 0x0018 ATD Result Register 4 H
ATDDR4L 0x0019 ATD Result Register 4 L
ATDDR5H 0x001A ATD Result Register 5 H
ATDDR5L 0x001B ATD Result Register 5 L
ATDDR6H 0x001C ATD Result Register 6 H
ATDDR6L 0x001D ATD Result Register 6 L
ATDDR7H 0x001E ATD Result Register 7 H
ATDDR7L 0x001F ATD Result Register 7 L
; BDLC
DLCBCR1 0x0000 BDLC Control Register 1
DLCBCR1.IMSG 7 Ignore Message
DLCBCR1.CLKS 6 Clock Select
DLCBCR1.IE 1 Interrupt Enable
DLCBCR1.WCM 0 Wait Clock Mode
DLCBSVR 0x0001 BDLC State Vector Register
DLCBSVR.I3 5 Interrupt State Vector bit 3
DLCBSVR.I2 4 Interrupt State Vector bit 2
DLCBSVR.I1 3 Interrupt State Vector bit 1
DLCBSVR.I0 2 Interrupt State Vector bit 0
DLCBCR2 0x0002 BDLC Control Register 2
DLCBCR2.SMRST 7 State Machine Reset
DLCBCR2.DLOOP 6 Digital Loopback Mode
DLCBCR2.RX4XE 5 Receive 4X Enable
DLCBCR2.NBFS 4 Normalization Bit Format Select
DLCBCR2.TEOD 3 Transmit End of Data
DLCBCR2.TSIFR 2 TSIFR - Transmit In-Frame Response Control
DLCBCR2.TMIFR1 1 TMIFR1 - Transmit In-Frame Response Control
DLCBCR2.TMIFR0 0 TMIFR0 - Transmit In-Frame Response Control
DLCBDR 0x0003 BDLC Data Register
DLCBDR.D7 7 Receive/Transmit Data bit 7
DLCBDR.D6 6 Receive/Transmit Data bit 6
DLCBDR.D5 5 Receive/Transmit Data bit 5
DLCBDR.D4 4 Receive/Transmit Data bit 4
DLCBDR.D3 3 Receive/Transmit Data bit 3
DLCBDR.D2 2 Receive/Transmit Data bit 2
DLCBDR.D1 1 Receive/Transmit Data bit 1
DLCBDR.D0 0 Receive/Transmit Data bit 0
DLCBARD 0x0004 BDLC Analog RoundTrip Delay Register
DLCBARD.RXPOL 6 Receive Pin Polarity
DLCBARD.BO3 3 BDLC Analog Roundtrip Delay Offset Field bit 3
DLCBARD.BO2 2 BDLC Analog Roundtrip Delay Offset Field bit 2
DLCBARD.BO1 1 BDLC Analog Roundtrip Delay Offset Field bit 1
DLCBARD.BO0 0 BDLC Analog Roundtrip Delay Offset Field bit 0
DLCBRSR 0x0005 BDLC Rate Select Register
DLCBRSR.R5 5 Rate Select bit 5
DLCBRSR.R4 4 Rate Select bit 4
DLCBRSR.R3 3 Rate Select bit 3
DLCBRSR.R2 2 Rate Select bit 2
DLCBRSR.R1 1 Rate Select bit 1
DLCBRSR.R0 0 Rate Select bit 0
DLCSCR 0x0006 BDLC Control Register
DLCSCR.BDLCE 4 BDLC Enable
DLCBSTAT 0x0007 BDLC Status Register
DLCBSTAT.IDLE 0 Idle
; CRG
SYNR 0x0000 CRG Synthesizer Register
SYNR.SYN5 5
SYNR.SYN4 4
SYNR.SYN3 3
SYNR.SYN2 2
SYNR.SYN1 1
SYNR.SYN0 0
REFDV 0x0001 CRG Reference Divider Register
REFDV.REFDV3 3
REFDV.REFDV2 2
REFDV.REFDV1 1
REFDV.REFDV0 0
CTFLG 0x0002 CRG Test Flags Register
CRGFLG 0x0003 CRG Flags Register
CRGFLG.RTIF 7 Real Time Interrupt Flag
CRGFLG.PORF 6 Power on Reset Flag
CRGFLG.LOCKIF 4 PLL Lock Interrupt Flag
CRGFLG.LOCK 3 Lock Status Bit
CRGFLG.TRACK 2 Track Status Bit
CRGFLG.SCMIF 1 Self Clock Mode Interrupt Flag
CRGFLG.SCM 0 Self Clock Mode Status Bit
CRGINT 0x0004 CRG Interrupt Enable Register
CRGINT.RTIE 7 Real Time Interrupt Enable Bit
CRGINT.LOCKIE 4 Lock Interrupt Enable Bit
CRGINT.SCMIE 1 Self Clock Mode Interrupt Enable Bit
CLKSEL 0x0005 CRG Clock Select Register
CLKSEL.PLLSEL 7 PLL Select Bit
CLKSEL.PSTP 6 Pseudo Stop Bit
CLKSEL.SYSWAI 5 System clocks stop in Wait Mode Bit
CLKSEL.ROAWAI 4 Reduced Oscillator Amplitude in Wait Mode Bit
CLKSEL.PLLWAI 3 PLL stops in Wait Mode Bit
CLKSEL.CWAI 2 Core stops in Wait Mode Bit
CLKSEL.RTIWAI 1 RTI stops in Wait Mode Bit
CLKSEL.COPWAI 0 COP stops in Wait Mode Bit
PLLCTL 0x0006 CRG PLL Control Register
PLLCTL.CME 7 Clock Monitor Enable Bit
PLLCTL.PLLON 6 Phase Lock Loop On Bit
PLLCTL.AUTO 5 Automatic Bandwidth Control Bit
PLLCTL.ACQ 4 Acquisition Bit
PLLCTL.PRE 2 RTI Enable during Pseudo Stop Bit
PLLCTL.PCE 1 COP Enable during Pseudo Stop Bit
PLLCTL.SCME 0 Self Clock Mode Enable Bit
RTICTL 0x0007 CRG RTI Control Register
RTICTL.RTR6 6 Real Time Interrupt Prescale Rate Select Bit 6
RTICTL.RTR5 5 Real Time Interrupt Prescale Rate Select Bit 5
RTICTL.RTR4 4 Real Time Interrupt Prescale Rate Select Bit 4
RTICTL.RTR3 3 Real Time Interrupt Modulus Counter Select Bit 3
RTICTL.RTR2 2 Real Time Interrupt Modulus Counter Select Bit 2
RTICTL.RTR1 1 Real Time Interrupt Modulus Counter Select Bit 1
RTICTL.RTR0 0 Real Time Interrupt Modulus Counter Select Bit 0
COPCTL 0x0008 CRG COP Control Register
COPCTL.WCOP 7 Window COP Mode Bit
COPCTL.RSBCK 6 COP and RTI stop in Active BDM mode Bit
COPCTL.CR2 2 COP Watchdog Timer Rate select bit 2
COPCTL.CR1 1 COP Watchdog Timer Rate select bit 1
COPCTL.CR0 0 COP Watchdog Timer Rate select bit 0
FORBYP 0x0009 CRG Force and Bypass Test Register
CTCTL 0x000A CRG Test Control Register
ARMCOP 0x000B CRG COP Arm/Timer Reset
; ECT_16B8C
TIOS 0x0000 Timer Input Capture/Output Compare Select
TIOS.IOS7 7 Input Capture or Output Compare Channel Configuration bit 7
TIOS.IOS6 6 Input Capture or Output Compare Channel Configuration bit 6
TIOS.IOS5 5 Input Capture or Output Compare Channel Configuration bit 5
TIOS.IOS4 4 Input Capture or Output Compare Channel Configuration bit 4
TIOS.IOS3 3 Input Capture or Output Compare Channel Configuration bit 3
TIOS.IOS2 2 Input Capture or Output Compare Channel Configuration bit 2
TIOS.IOS1 1 Input Capture or Output Compare Channel Configuration bit 1
TIOS.IOS0 0 Input Capture or Output Compare Channel Configuration bit 0
CFORC 0x0001 Timer Compare Force Register
CFORC.FOC7 7 Force Output Compare Action for Channel 7
CFORC.FOC6 6 Force Output Compare Action for Channel 6
CFORC.FOC5 5 Force Output Compare Action for Channel 5
CFORC.FOC4 4 Force Output Compare Action for Channel 4
CFORC.FOC3 3 Force Output Compare Action for Channel 3
CFORC.FOC2 2 Force Output Compare Action for Channel 2
CFORC.FOC1 1 Force Output Compare Action for Channel 1
CFORC.FOC0 0 Force Output Compare Action for Channel 0
OC7M 0x0002 Output Compare 7 Mask Register
OC7M.OC7M7 7
OC7M.OC7M6 6
OC7M.OC7M5 5
OC7M.OC7M4 4
OC7M.OC7M3 3
OC7M.OC7M2 2
OC7M.OC7M1 1
OC7M.OC7M0 0
OC7D 0x0003 Output Compare 7 Data Register
OC7D.OC7D7 7
OC7D.OC7D6 6
OC7D.OC7D5 5
OC7D.OC7D4 4
OC7D.OC7D3 3
OC7D.OC7D2 2
OC7D.OC7D1 1
OC7D.OC7D0 0
TCNTH 0x0004 Timer Count Register High
TCNTH.tcnt15 15
TCNTH.tcnt14 14
TCNTH.tcnt13 13
TCNTH.tcnt12 12
TCNTH.tcnt11 11
TCNTH.tcnt10 10
TCNTH.tcnt9 9
TCNTH.tcnt8 8
TCNTL 0x0005 Timer Count Register Low
TCNTL.tcnt7 7
TCNTL.tcnt6 6
TCNTL.tcnt5 5
TCNTL.tcnt4 4
TCNTL.tcnt3 3
TCNTL.tcnt2 2
TCNTL.tcnt1 1
TCNTL.tcnt0 0
TSCR1 0x0006 Timer System Control Register1
TSCR1.TEN 7 Timer Enable
TSCR1.TSWAI 6 Timer Module Stops While in Wait
TSCR1.TSFRZ 5 Timer and Modulus Counter Stop While in Freeze Mode
TSCR1.TFFCA 4 Timer Fast Flag Clear All
TTOV 0x0007 Timer Toggle Overflow Register
TTOV.TOV7 7 Toggle On Overflow Bit 7
TTOV.TOV6 6 Toggle On Overflow Bit 6
TTOV.TOV5 5 Toggle On Overflow Bit 5
TTOV.TOV4 4 Toggle On Overflow Bit 4
TTOV.TOV3 3 Toggle On Overflow Bit 3
TTOV.TOV2 2 Toggle On Overflow Bit 2
TTOV.TOV1 1 Toggle On Overflow Bit 1
TTOV.TOV0 0 Toggle On Overflow Bit 0
TCTL1 0x0008 Timer Control Register1
TCTL1.OM7 7 Output Mode bit 7
TCTL1.OL7 6 Output Level bit 7
TCTL1.OM6 5 Output Mode bit 6
TCTL1.OL6 4 Output Level bit 6
TCTL1.OM5 3 Output Mode bit 5
TCTL1.OL5 2 Output Level bit 5
TCTL1.OM4 1 Output Mode bit 4
TCTL1.OL4 0 Output Level bit 4
TCTL2 0x0009 Timer Control Register2
TCTL1.OM3 7 Output Mode bit 3
TCTL1.OL3 6 Output Level bit 3
TCTL1.OM2 5 Output Mode bit 2
TCTL1.OL2 4 Output Level bit 2
TCTL1.OM1 3 Output Mode bit 1
TCTL1.OL1 2 Output Level bit 1
TCTL1.OM0 1 Output Mode bit 0
TCTL1.OL0 0 Output Level bit 0
TCTL3 0x000A Timer Control Register3
TCTL3.EDG7B 7 EDG7B - Input Capture Edge Control
TCTL3.EDG7A 6 EDG7A - Input Capture Edge Control
TCTL3.EDG6B 5 EDG6B - Input Capture Edge Control
TCTL3.EDG6A 4 EDG6A - Input Capture Edge Control
TCTL3.EDG5B 3 EDG5B - Input Capture Edge Control
TCTL3.EDG5A 2 EDG5A - Input Capture Edge Control
TCTL3.EDG4B 1 EDG4B - Input Capture Edge Control
TCTL3.EDG4A 0 EDG4A - Input Capture Edge Control
TCTL4 0x000B Timer Control Register4
TCTL4.EDG3B 7 EDG3B - Input Capture Edge Control
TCTL4.EDG3A 6 EDG3A - Input Capture Edge Control
TCTL4.EDG2B 5 EDG2B - Input Capture Edge Control
TCTL4.EDG2A 4 EDG2A - Input Capture Edge Control
TCTL4.EDG1B 3 EDG1B - Input Capture Edge Control
TCTL4.EDG1A 2 EDG1A - Input Capture Edge Control
TCTL4.EDG0B 1 EDG0B - Input Capture Edge Control
TCTL4.EDG0A 0 EDG0A - Input Capture Edge Control
TIE 0x000C Timer Interrupt Enable Register
TIE.C7I 7 Input Capture/Output Compare "7" Interrupt Enable
TIE.C6I 6 Input Capture/Output Compare "6" Interrupt Enable
TIE.C5I 5 Input Capture/Output Compare "5" Interrupt Enable
TIE.C4I 4 Input Capture/Output Compare "4" Interrupt Enable
TIE.C3I 3 Input Capture/Output Compare "3" Interrupt Enable
TIE.C2I 2 Input Capture/Output Compare "2" Interrupt Enable
TIE.C1I 1 Input Capture/Output Compare "1" Interrupt Enable
TIE.C0I 0 Input Capture/Output Compare "0" Interrupt Enable
TSCR2 0x000D Timer System Control Register2
TSCR2.TOI 7 Timer Overflow Interrupt Enable
TSCR2.TCRE 3 Timer Counter Reset Enable
TSCR2.PR2 2 Timer Prescaler Select bit 2
TSCR2.PR1 1 Timer Prescaler Select bit 1
TSCR2.PR0 0 Timer Prescaler Select bit 0
TFLG1 0x000E Main Timer Interrupt Flag1
TFLG1.C7F 7 Input Capture/Output Compare Channel "7" Flag
TFLG1.C6F 6 Input Capture/Output Compare Channel "6" Flag
TFLG1.C5F 5 Input Capture/Output Compare Channel "5" Flag
TFLG1.C4F 4 Input Capture/Output Compare Channel "4" Flag
TFLG1.C3F 3 Input Capture/Output Compare Channel "3" Flag
TFLG1.C2F 2 Input Capture/Output Compare Channel "2" Flag
TFLG1.C1F 1 Input Capture/Output Compare Channel "1" Flag
TFLG1.C0F 0 Input Capture/Output Compare Channel "0" Flag
TFLG2 0x000F Main Timer Interrupt Flag2
TFLG2.TOF 7 Timer Overflow Flag
TC0H 0x0010 Timer Input Capture/Output Compare Register0 High
TC0H.tc015 15
TC0H.tc014 14
TC0H.tc013 13
TC0H.tc012 12
TC0H.tc011 11
TC0H.tc010 10
TC0H.tc09 9
TC0H.tc08 8
TC0L 0x0011 Timer Input Capture/Output Compare Register0 Low
TC0L.tc07 7
TC0L.tc06 6
TC0L.tc05 5
TC0L.tc04 4
TC0L.tc03 3
TC0L.tc02 2
TC0L.tc01 1
TC0L.tc00 0
TC1H 0x0012 Timer Input Capture/Output Compare Register1 High
TC1H.tc015 15
TC1H.tc014 14
TC1H.tc013 13
TC1H.tc012 12
TC1H.tc011 11
TC1H.tc010 10
TC1H.tc09 9
TC1H.tc08 8
TC1L 0x0013 Timer Input Capture/Output Compare Register1 Low
TC1L.tc07 7
TC1L.tc06 6
TC1L.tc05 5
TC1L.tc04 4
TC1L.tc03 3
TC1L.tc02 2
TC1L.tc01 1
TC1L.tc00 0
TC2H 0x0014 Timer Input Capture/Output Compare Register2 High
TC2H.tc015 15
TC2H.tc014 14
TC2H.tc013 13
TC2H.tc012 12
TC2H.tc011 11
TC2H.tc010 10
TC2H.tc09 9
TC2H.tc08 8
TC2L 0x0015 Timer Input Capture/Output Compare Register2 Low
TC2L.tc07 7
TC2L.tc06 6
TC2L.tc05 5
TC2L.tc04 4
TC2L.tc03 3
TC2L.tc02 2
TC2L.tc01 1
TC2L.tc00 0
TC3H 0x0016 Timer Input Capture/Output Compare Register3 High
TC3H.tc015 15
TC3H.tc014 14
TC3H.tc013 13
TC3H.tc012 12
TC3H.tc011 11
TC3H.tc010 10
TC3H.tc09 9
TC3H.tc08 8
TC3L 0x0017 Timer Input Capture/Output Compare Register3 Low
TC3L.tc07 7
TC3L.tc06 6
TC3L.tc05 5
TC3L.tc04 4
TC3L.tc03 3
TC3L.tc02 2
TC3L.tc01 1
TC3L.tc00 0
TC4H 0x0018 Timer Input Capture/Output Compare Register4 High
TC4H.tc015 15
TC4H.tc014 14
TC4H.tc013 13
TC4H.tc012 12
TC4H.tc011 11
TC4H.tc010 10
TC4H.tc09 9
TC4H.tc08 8
TC4L 0x0019 Timer Input Capture/Output Compare Register4 Low
TC4L.tc07 7
TC4L.tc06 6
TC4L.tc05 5
TC4L.tc04 4
TC4L.tc03 3
TC4L.tc02 2
TC4L.tc01 1
TC4L.tc00 0
TC5H 0x001A Timer Input Capture/Output Compare Register5 High
TC5H.tc015 15
TC5H.tc014 14
TC5H.tc013 13
TC5H.tc012 12
TC5H.tc011 11
TC5H.tc010 10
TC5H.tc09 9
TC5H.tc08 8
TC5L 0x001B Timer Input Capture/Output Compare Register5 Low
TC5L.tc07 7
TC5L.tc06 6
TC5L.tc05 5
TC5L.tc04 4
TC5L.tc03 3
TC5L.tc02 2
TC5L.tc01 1
TC5L.tc00 0
TC6H 0x001C Timer Input Capture/Output Compare Register6 High
TC6H.tc015 15
TC6H.tc014 14
TC6H.tc013 13
TC6H.tc012 12
TC6H.tc011 11
TC6H.tc010 10
TC6H.tc09 9
TC6H.tc08 8
TC6L 0x001D Timer Input Capture/Output Compare Register6 Low
TC6L.tc07 7
TC6L.tc06 6
TC6L.tc05 5
TC6L.tc04 4
TC6L.tc03 3
TC6L.tc02 2
TC6L.tc01 1
TC6L.tc00 0
TC7H 0x001E Timer Input Capture/Output Compare Register7 High
TC7H.tc015 15
TC7H.tc014 14
TC7H.tc013 13
TC7H.tc012 12
TC7H.tc011 11
TC7H.tc010 10
TC7H.tc09 9
TC7H.tc08 8
TC7L 0x001F Timer Input Capture/Output Compare Register7 Low
TC7L.tc07 7
TC7L.tc06 6
TC7L.tc05 5
TC7L.tc04 4
TC7L.tc03 3
TC7L.tc02 2
TC7L.tc01 1
TC7L.tc00 0
PACTL 0x0020 16-Bit Pulse Accumulator A Control Register
PACTL.PAEN 6 Pulse Accumulator A System Enable
PACTL.PAMOD 5 Pulse Accumulator Mode
PACTL.PEDGE 4 Pulse Accumulator Edge Control
PACTL.CLK1 3 Clock Select Bit 1
PACTL.CLK0 2 Clock Select Bit 0
PACTL.PAOVI 1 Pulse Accumulator A Overflow Interrupt enable
PACTL.PAI 0 Pulse Accumulator Input Interrupt enable
PAFLG 0x0021 Pulse Accumulator A Flag Register
PAFLG.PAOVF 1 Pulse Accumulator A Overflow Flag
PAFLG.PAIF 0 Pulse Accumulator Input edge Flag
PACN3 0x0022 Pulse Accumulator Count Register3
PACN3.pacnt7_15 7
PACN3.pacnt6_14 6
PACN3.pacnt5_13 5
PACN3.pacnt4_12 4
PACN3.pacnt3_11 3
PACN3.pacnt2_10 2
PACN3.pacnt1_9 1
PACN3.pacnt0_8 0
PACN2 0x0023 Pulse Accumulator Count Register2
PACN2.pacnt7 7
PACN2.pacnt6 6
PACN2.pacnt5 5
PACN2.pacnt4 4
PACN2.pacnt3 3
PACN2.pacnt2 2
PACN2.pacnt1 1
PACN2.pacnt0 0
PACN1 0x0024 Pulse Accumulator Count Register1
PACN1.pacnt7_15 7
PACN1.pacnt6_14 6
PACN1.pacnt5_13 5
PACN1.pacnt4_12 4
PACN1.pacnt3_11 3
PACN1.pacnt2_10 2
PACN1.pacnt1_9 1
PACN1.pacnt0_8 0
PACN0 0x0025 Pulse Accumulator Count Register0
PACN0.pacnt7 7
PACN0.pacnt6 6
PACN0.pacnt5 5
PACN0.pacnt4 4
PACN0.pacnt3 3
PACN0.pacnt2 2
PACN0.pacnt1 1
PACN0.pacnt0 0
MCCTL 0x0026 16-Bit Modulus Down Counter Register
MCCTL.MCZI 7 Modulus Counter Underflow Interrupt Enable
MCCTL.MODMC 6 Modulus Mode Enable
MCCTL.RDMCL 5 Read Modulus Down-Counter Load
MCCTL.ICLAT 4 Input Capture Force Latch Action
MCCTL.FLMC 3 Force Load Register into the Modulus Counter Count Register
MCCTL.MCEN 2 Modulus Down-Counter Enable
MCCTL.MCPR1 1 Modulus Counter Prescaler select bit 1
MCCTL.MCPR0 0 Modulus Counter Prescaler select bit 0
MCFLG 0x0027 16-Bit Modulus Down Counter Flag Register
MCFLG.MCZF 7 Modulus Counter Underflow Flag
MCFLG.POLF3 3 First Input Capture Polarity Status bit 3
MCFLG.POLF2 2 First Input Capture Polarity Status bit 2
MCFLG.POLF1 1 First Input Capture Polarity Status bit 1
MCFLG.POLF0 0 First Input Capture Polarity Status bit 0
ICPAR 0x0028 Input Control Pulse Accumulator Register
ICPAR.PA3EN 3 8-Bit Pulse Accumulator '3' Enable
ICPAR.PA2EN 2 8-Bit Pulse Accumulator '2' Enable
ICPAR.PA1EN 1 8-Bit Pulse Accumulator '1' Enable
ICPAR.PA0EN 0 8-Bit Pulse Accumulator '0' Enable
DLYCT 0x0029 Delay Counter Control Register
DLYCT.DLY1 1 Delay Counter Select bit 1
DLYCT.DLY0 0 Delay Counter Select bit 0
ICOVW 0x002A Input Control Overwrite Register
ICOVW.NOVW7 7 No Input Capture Overwrite bit 7
ICOVW.NOVW6 6 No Input Capture Overwrite bit 6
ICOVW.NOVW5 5 No Input Capture Overwrite bit 5
ICOVW.NOVW4 4 No Input Capture Overwrite bit 4
ICOVW.NOVW3 3 No Input Capture Overwrite bit 3
ICOVW.NOVW2 2 No Input Capture Overwrite bit 2
ICOVW.NOVW1 1 No Input Capture Overwrite bit 1
ICOVW.NOVW0 0 No Input Capture Overwrite bit 0
ICSYS 0x002B Input Control System Control Register
ICSYS.SH37 7 Share Input action of Input Capture Channels 3 and 7
ICSYS.SH26 6 Share Input action of Input Capture Channels 2 and 6
ICSYS.SH15 5 Share Input action of Input Capture Channels 1 and 5
ICSYS.SH04 4 Share Input action of Input Capture Channels 0 and 4
ICSYS.TFMOD 3 Timer Flag-setting Mode
ICSYS.PACMX 2 8-Bit Pulse Accumulators Maximum Count
ICSYS.BUFEN 1 IC Buffer Enable
ICSYS.LATQ 0 Input Control Latch or Queue Mode Enable
RESERVED002C 0x002C RESERVED
TIMTST 0x002D Timer Test Register
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
PBCTL 0x0030 16-Bit Pulse Accumulator B Control Register
PBCTL.PBEN 6 Pulse Accumulator B System Enable
PBCTL.PBOVI 1 Pulse Accumulator B Overflow Interrupt enable
PBFLG 0x0031 16-Bit Pulse Accumulator B Flag Register
PBFLG.PBOVF 1 Pulse Accumulator B Overflow Flag
PA3H 0x0032 8-Bit Pulse Accumulator Holding Register3
PA3H.PA3H7 7
PA3H.PA3H6 6
PA3H.PA3H5 5
PA3H.PA3H4 4
PA3H.PA3H3 3
PA3H.PA3H2 2
PA3H.PA3H1 1
PA3H.PA3H0 0
PA2H 0x0033 8-Bit Pulse Accumulator Holding Register2
PA2H.PA2H7 7
PA2H.PA2H6 6
PA2H.PA2H5 5
PA2H.PA2H4 4
PA2H.PA2H3 3
PA2H.PA2H2 2
PA2H.PA2H1 1
PA2H.PA2H0 0
PA1H 0x0034 8-Bit Pulse Accumulator Holding Register1
PA1H.PA1H7 7
PA1H.PA1H6 6
PA1H.PA1H5 5
PA1H.PA1H4 4
PA1H.PA1H3 3
PA1H.PA1H2 2
PA1H.PA1H1 1
PA1H.PA1H0 0
PA0H 0x0035 8-Bit Pulse Accumulator Holding Register0
PA0H.PA0H7 7
PA0H.PA0H6 6
PA0H.PA0H5 5
PA0H.PA0H4 4
PA0H.PA0H3 3
PA0H.PA0H2 2
PA0H.PA0H1 1
PA0H.PA0H0 0
MCCNT 0x0036 Modulus Down-Counter Count Register High
MCCNT.mccnt15 15
MCCNT.mccnt14 14
MCCNT.mccnt13 13
MCCNT.mccnt12 12
MCCNT.mccnt11 11
MCCNT.mccnt10 10
MCCNT.mccnt9 9
MCCNT.mccnt8 8
MCCNT.mccnt7 7
MCCNT.mccnt6 6
MCCNT.mccnt5 5
MCCNT.mccnt4 4
MCCNT.mccnt3 3
MCCNT.mccnt2 2
MCCNT.mccnt1 1
MCCNT.mccnt0 0
TC0H 0x0038 Timer Input Capture Holding Register0 High
TC0H.TC15 15
TC0H.TC14 14
TC0H.TC13 13
TC0H.TC12 12
TC0H.TC11 11
TC0H.TC10 10
TC0H.TC9 9
TC0H.TC8 8
TC0H.TC7 7
TC0H.TC6 6
TC0H.TC5 5
TC0H.TC4 4
TC0H.TC3 3
TC0H.TC2 2
TC0H.TC1 1
TC0H.TC0 0
TC1H 0x003A Timer Input Capture Holding Register1 High
TC1H.TC15 15
TC1H.TC14 14
TC1H.TC13 13
TC1H.TC12 12
TC1H.TC11 11
TC1H.TC10 10
TC1H.TC9 9
TC1H.TC8 8
TC1H.TC7 7
TC1H.TC6 6
TC1H.TC5 5
TC1H.TC4 4
TC1H.TC3 3
TC1H.TC2 2
TC1H.TC1 1
TC1H.TC0 0
TC2H 0x003C Timer Input Capture Holding Register2 High
TC2H.TC15 15
TC2H.TC14 14
TC2H.TC13 13
TC2H.TC12 12
TC2H.TC11 11
TC2H.TC10 10
TC2H.TC9 9
TC2H.TC8 8
TC2H.TC7 7
TC2H.TC6 6
TC2H.TC5 5
TC2H.TC4 4
TC2H.TC3 3
TC2H.TC2 2
TC2H.TC1 1
TC2H.TC0 0
TC3H 0x003E Timer Input Capture Holding Register3 High
TC3H.TC15 15
TC3H.TC14 14
TC3H.TC13 13
TC3H.TC12 12
TC3H.TC11 11
TC3H.TC10 10
TC3H.TC9 9
TC3H.TC8 8
TC3H.TC7 7
TC3H.TC6 6
TC3H.TC5 5
TC3H.TC4 4
TC3H.TC3 3
TC3H.TC2 2
TC3H.TC1 1
TC3H.TC0 0
; EETS2K
ECLKDIV 0x0000 EEPROM Clock Divider Register
ECLKDIV.EDIVLD 7 Clock Divider Loaded
ECLKDIV.PRDIV8 6 Enable Prescaler by 8
ECLKDIV.EDIV5 5 Clock Divider Bit 5
ECLKDIV.EDIV4 4 Clock Divider Bit 4
ECLKDIV.EDIV3 3 Clock Divider Bit 3
ECLKDIV.EDIV2 2 Clock Divider Bit 2
ECLKDIV.EDIV1 1 Clock Divider Bit 1
ECLKDIV.EDIV0 0 Clock Divider Bit 0
RESERVED0001 0x0001 RESERVED
RESERVED0002 0x0002 RESERVED
ECNFG 0x0003 EEPROM Configuration Register
ECNFG.CBEIE 7 Command Buffer Empty Interrupt Enable
ECNFG.CCIE 6 Command Complete Interrupt Enable
EPROT 0x0004 EEPROM Protection Register
EPROT.EPOPEN 7 Opens the EEPROM for program or erase
EPROT.NV6 6 Non Volatile Flag Bit 6
EPROT.NV5 5 Non Volatile Flag Bit 5
EPROT.NV4 4 Non Volatile Flag Bit 4
EPROT.EPDIS 3 EEPROM Protection address range Disable
EPROT.EP2 2 EEPROM Protection Address Size bit 2
EPROT.EP1 1 EEPROM Protection Address Size bit 1
EPROT.EP0 0 EEPROM Protection Address Size bit 0
ESTAT 0x0005 EEPROM Status Register
ESTAT.CBEIF 7 Command Buffer Empty Interrupt Flag
ESTAT.CCIF 6 Command Complete Interrupt Flag
ESTAT.PVIOL 5 Protection Violation
ESTAT.ACCERR 4 EEPROM Access Error
ESTAT.BLANK 2 Array has been verified as erased
ECMD 0x0006 EEPROM Command Register
ECMD.CMDB6 6
ECMD.CMDB5 5
ECMD.CMDB2 2
ECMD.CMDB0 0
RESERVED0007 0x0007 RESERVED
RESERVED0008 0x0008 RESERVED
RESERVED0009 0x0009 RESERVED
RESERVED000A 0x000A RESERVED
RESERVED000B 0x000B RESERVED
; FTS128K
FCLKDIV 0x0000 Flash Clock Divider Register
FCLKDIV.FDIVLD 7 Clock Divider Loaded
FCLKDIV.PRDIV8 6 Enable Prescaler by 8
FCLKDIV.FDIV5 5 Clock Divider Bit 5
FCLKDIV.FDIV4 4 Clock Divider Bit 4
FCLKDIV.FDIV3 3 Clock Divider Bit 3
FCLKDIV.FDIV2 2 Clock Divider Bit 2
FCLKDIV.FDIV1 1 Clock Divider Bit 1
FCLKDIV.FDIV0 0 Clock Divider Bit 0
FSEC 0x0001 Flash Security Register
FSEC.KEYEN 7 Enable backdoor key to security
FSEC.NV6 6 Non Volatile Flag Bit 6
FSEC.NV5 5 Non Volatile Flag Bit 5
FSEC.NV4 4 Non Volatile Flag Bit 4
FSEC.NV3 3 Non Volatile Flag Bit 3
FSEC.NV2 2 Non Volatile Flag Bit 2
FSEC.SEC1 1 Memory Security Bit 1
FSEC.SEC0 0 Memory Security Bit 0
FTSTMOD 0x0002 Flash Test Mode Register
FTSTMOD.WRALL 4 Write to all register banks
FCNFG 0x0003 Flash Configuration Register
FCNFG.CBEIE 7 Command Buffer Empty Interrupt Enable
FCNFG.CCIE 6 Command Complete Interrupt Enable
FCNFG.KEYACC 5 Enable Security Key Writing
FCNFG.BKSEL 0 Register Bank Select
FPROT 0x0004 Flash Protection Register
FPROT.FPOPEN 7 Opens the Flash for program or erase
FPROT.NV6 6 Non Volatile Flag Bit
FPROT.FPHDIS 5 Flash Protection Higher address range Disable
FPROT.FPHS1 4 Flash Protection Higher Address Size bit 1
FPROT.FPHS0 3 Flash Protection Higher Address Size bit 0
FPROT.FPLDIS 2 Flash Protection Lower address range Disable
FPROT.FPLS1 1 Flash Protection Lower Address Size bit 1
FPROT.FPLS0 0 Flash Protection Lower Address Size bit 0
FSTAT 0x0005 Flash Status Register
FSTAT.CBEIF 7 Command Buffer Empty Interrupt Flag
FSTAT.CCIF 6 Command Complete Interrupt Flag
FSTAT.PVIOL 5 Protection Violation
FSTAT.ACCERR 4 Flash Access Error
FSTAT.BLANK 2 Array has been verified as erased
FCMD 0x0006 Flash Command Register
FCMD.CMDB6 6
FCMD.CMDB5 5
FCMD.CMDB2 2
FCMD.CMDB0 0
RESERVED0007 0x0007 RESERVED
FADDRHI 0x0008 16-bit Address Register
FADDRLO 0x0009 16-bit Address Register
FDATAHI 0x000A 16-bit Data Register
FDATALO 0x000B 16-bit Data Register
; HCS12
IBAD 0x0000 IIC-Bus Address Register
IBAD.ADR7 7 Slave Address bit 7
IBAD.ADR6 6 Slave Address bit 6
IBAD.ADR5 5 Slave Address bit 5
IBAD.ADR4 4 Slave Address bit 4
IBAD.ADR3 3 Slave Address bit 3
IBAD.ADR2 2 Slave Address bit 2
IBAD.ADR1 1 Slave Address bit 1
IBFD 0x0001 IIC-Bus Frequency Divider Register
IBFD.IBC7 7 I-Bus Clock Rate 7
IBFD.IBC6 6 I-Bus Clock Rate 6
IBFD.IBC5 5 I-Bus Clock Rate 5
IBFD.IBC4 4 I-Bus Clock Rate 4
IBFD.IBC3 3 I-Bus Clock Rate 3
IBFD.IBC2 2 I-Bus Clock Rate 2
IBFD.IBC1 1 I-Bus Clock Rate 1
IBFD.IBC0 0 I-Bus Clock Rate 0
IBCR 0x0002 IIC-Bus Control Register
IBCR.IBEN 7 I-Bus Enable
IBCR.IBIE 6 I-Bus Interrupt Enable
IBCR.MS_SL 5 Master/Slave mode select bit
IBCR.Tx_Rx 4 Transmit/Receive mode select bit
IBCR.TXAK 3 Transmit Acknowledge enable
IBCR.RSTA 2 Repeat Start
IBCR.IBSWAI 0 I-Bus Interface Stop in WAIT mode
IBSR 0x0003 IIC-Bus Status Register
IBSR.TCF 7 Data transferring bit
IBSR.IAAS 6 Addressed as a slave bit
IBSR.IBB 5 Bus busy bit
IBSR.IBAL 4 Arbitration Lost
IBSR.SRW 2 Slave Read/Write
IBSR.IBIF 1 I-Bus Interrupt
IBSR.RXAK 0 Received Acknowledge
IBDR 0x0004 IIC-Bus Data I/O Register
IBDR.D7 7
IBDR.D6 6
IBDR.D5 5
IBDR.D4 4
IBDR.D3 3
IBDR.D2 2
IBDR.D1 1
IBDR.D0 0
; PWM_8B8C
PWME 0x0000 PWM Enable Register
PWME.PWME7 7 Pulse Width Channel 7 Enable
PWME.PWME6 6 Pulse Width Channel 6 Enable
PWME.PWME5 5 Pulse Width Channel 5 Enable
PWME.PWME4 4 Pulse Width Channel 4 Enable
PWME.PWME3 3 Pulse Width Channel 3 Enable
PWME.PWME2 2 Pulse Width Channel 2 Enable
PWME.PWME1 1 Pulse Width Channel 1 Enable
PWME.PWME0 0 Pulse Width Channel 0 Enable
PWMPOL 0x0001 PWM Polarity Register
PWMPOL.PPOL7 7 Pulse Width Channel 7 Polarity
PWMPOL.PPOL6 6 Pulse Width Channel 6 Polarity
PWMPOL.PPOL5 5 Pulse Width Channel 5 Polarity
PWMPOL.PPOL4 4 Pulse Width Channel 4 Polarity
PWMPOL.PPOL3 3 Pulse Width Channel 3 Polarity
PWMPOL.PPOL2 2 Pulse Width Channel 2 Polarity
PWMPOL.PPOL1 1 Pulse Width Channel 1 Polarity
PWMPOL.PPOL0 0 Pulse Width Channel 0 Polarity
PWMCLK 0x0002 PWM Clock Select Register
PWMCLK.PCLK7 7 Pulse Width Channel 7 Clock Select
PWMCLK.PCLK6 6 Pulse Width Channel 6 Clock Select
PWMCLK.PCLK5 5 Pulse Width Channel 5 Clock Select
PWMCLK.PCLK4 4 Pulse Width Channel 4 Clock Select
PWMCLK.PCLK3 3 Pulse Width Channel 3 Clock Select
PWMCLK.PCLK2 2 Pulse Width Channel 2 Clock Select
PWMCLK.PCLK1 1 Pulse Width Channel 1 Clock Select
PWMCLK.PCLK0 0 Pulse Width Channel 0 Clock Select
PWMPRCLK 0x0003 PWM Prescale Clock Select Register
PWMPRCLK.PCKB2 6 Prescaler Select for Clock B bit 2
PWMPRCLK.PCKB1 5 Prescaler Select for Clock B bit 1
PWMPRCLK.PCKB0 4 Prescaler Select for Clock B bit 0
PWMPRCLK.PCKA2 2 Prescaler Select for Clock A bit 2
PWMPRCLK.PCKA1 1 Prescaler Select for Clock A bit 1
PWMPRCLK.PCKA0 0 Prescaler Select for Clock A bit 0
PWMCAE 0x0004 PWM Center Align Enable Register
PWMCAE.CAE7 7 Center Aligned Output Mode on channel 7
PWMCAE.CAE6 6 Center Aligned Output Mode on channel 6
PWMCAE.CAE5 5 Center Aligned Output Mode on channel 5
PWMCAE.CAE4 4 Center Aligned Output Mode on channel 4
PWMCAE.CAE3 3 Center Aligned Output Mode on channel 3
PWMCAE.CAE2 2 Center Aligned Output Mode on channel 2
PWMCAE.CAE1 1 Center Aligned Output Mode on channel 1
PWMCAE.CAE0 0 Center Aligned Output Mode on channel 0
PWMCTL 0x0005 PWM Control Register
PWMCTL.CON67 7 Concatenate channels 6 and 7
PWMCTL.CON45 6 Concatenate channels 4 and 5
PWMCTL.CON23 5 Concatenate channels 2 and 3
PWMCTL.CON01 4 Concatenate channels 0 and 1
PWMCTL.PSWAI 3 PWM Stops in Wait Mode
PWMCTL.PFRZ 2 PWM Counters Stop in Freeze Mode
PWMTST 0x0006 PWM Test Register
PWMPRSC 0x0007 PWM Prescale Counter Register
PWMSCLA 0x0008 PWM Scale A Register
PWMSCLB 0x0009 PWM Scale B Register
PWMSCNTA 0x000A PWM Scale A Counter Register
PWMSCNTB 0x000B PWM Scale B Counter Register
PWMCNT0 0x000C PWM Channel 0 Counter Register
PWMCNT1 0x000D PWM Channel 1 Counter Register
PWMCNT2 0x000E PWM Channel 2 Counter Register
PWMCNT3 0x000F PWM Channel 3 Counter Register
PWMCNT4 0x0010 PWM Channel 4 Counter Register
PWMCNT5 0x0011 PWM Channel 5 Counter Register
PWMCNT6 0x0012 PWM Channel 6 Counter Register
PWMCNT7 0x0013 PWM Channel 7 Counter Register
PWMPER0 0x0014 PWM Channel 0 Period Register
PWMPER1 0x0015 PWM Channel 1 Period Register
PWMPER2 0x0016 PWM Channel 2 Period Register
PWMPER3 0x0017 PWM Channel 3 Period Register
PWMPER4 0x0018 PWM Channel 4 Period Register
PWMPER5 0x0019 PWM Channel 5 Period Register
PWMPER6 0x001A PWM Channel 6 Period Register
PWMPER7 0x001B PWM Channel 7 Period Register
PWMDTY0 0x001C PWM Channel 0 Duty Register
PWMDTY1 0x001D PWM Channel 1 Duty Register
PWMDTY2 0x001E PWM Channel 2 Duty Register
PWMDTY3 0x001F PWM Channel 3 Duty Register
PWMDTY4 0x0020 PWM Channel 4 Duty Register
PWMDTY5 0x0021 PWM Channel 5 Duty Register
PWMDTY6 0x0022 PWM Channel 6 Duty Register
PWMDTY7 0x0023 PWM Channel 7 Duty Register
PWMSDN 0x0024 PWM Shutdown Register
PWMSDN.PWMIF 7 PWM Interrupt Flag
PWMSDN.PWMIE 6 PWM Interrupt Enable
PWMSDN.PWMRSTRT 5 PWM Restart
PWMSDN.PWMLVL 4 PWM shutdown output Level
PWMSDN.PWM7IN 2 PWM channel 7 input status
PWMSDN.PWM7INL 1 PWM shutdown active input level for channel 7
PWMSDN.PWM7ENA 0 PWM emergency shutdown Enable
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
; HCS12 Serial Communications Interface (SCI)
SCIBDH 0x0000 SCI Baud Rate Register High
SCIBDH.SBR12 4 SCI Baud Rate Bit 12
SCIBDH.SBR11 3 SCI Baud Rate Bit 11
SCIBDH.SBR10 2 SCI Baud Rate Bit 10
SCIBDH.SBR9 1 SCI Baud Rate Bit 9
SCIBDH.SBR8 0 SCI Baud Rate Bit 8
SCIBDL 0x0001 SCI Baud Rate Register Low
SCIBDL.SBR7 7 SCI Baud Rate Bit 7
SCIBDL.SBR6 6 SCI Baud Rate Bit 6
SCIBDL.SBR5 5 SCI Baud Rate Bit 5
SCIBDL.SBR4 4 SCI Baud Rate Bit 4
SCIBDL.SBR3 3 SCI Baud Rate Bit 3
SCIBDL.SBR2 2 SCI Baud Rate Bit 2
SCIBDL.SBR1 1 SCI Baud Rate Bit 1
SCIBDL.SBR0 0 SCI Baud Rate Bit 0
SCICR1 0x0002 SCI Control Register1
SCICR1.LOOPS 7 Loop Select Bit
SCICR1.SCISWAI 6 SCI Stop in Wait Mode Bit
SCICR1.RSRC 5 Receiver Source Bit
SCICR1.M 4 Data Format Mode Bit
SCICR1.WAKE 3 Wakeup Condition Bit
SCICR1.ILT 2 Idle Line Type Bit
SCICR1.PE 1 Parity Enable Bit
SCICR1.PT 0 Parity Type Bit
SCICR2 0x0003 SCI Control Register 2
SCICR2.TIE 7 Transmitter Interrupt Enable Bit
SCICR2.TCIE 6 Transmission Complete Interrupt Enable Bit
SCICR2.RIE 5 Receiver Full Interrupt Enable Bit
SCICR2.ILIE 4 Idle Line Interrupt Enable Bit
SCICR2.TE 3 Transmitter Enable Bit
SCICR2.RE 2 Receiver Enable Bit
SCICR2.RWU 1 Receiver Wakeup Bit
SCICR2.SBK 0 Send Break Bit
SCISR1 0x0004 SCI Status Register 1
SCISR1.TDRE 7 Transmit Data Register Empty Flag
SCISR1.TC 6 Transmit Complete Flag
SCISR1.RDRF 5 Receive Data Register Full Flag
SCISR1.IDLE 4 Idle Line Flag
SCISR1.OR 3 Overrun Flag
SCISR1.NF 2 Noise Flag
SCISR1.FE 1 Framing Error Flag
SCISR1.PF 0 Parity Error Flag
SCISR2 0x0005 SCI Status Register 2
SCISR2.BRK13 2 Break Transmit character length
SCISR2.TXDIR 1 Transmitter pin data direction in Single-Wire mode
SCISR2.RAF 0 Receiver Active Flag
SCIDRH 0x0006 SCI Data Register High
SCIDRH.R8 7 Received Bit 8
SCIDRH.T8 6 Transmit Bit 8
SCIDRL 0x0007 SCI Data Register Low
SCIDRL.R7_T7 7 Received/Transmit bit 7
SCIDRL.R6_T6 6 Received/Transmit bit 6
SCIDRL.R5_T5 5 Received/Transmit bit 5
SCIDRL.R4_T4 4 Received/Transmit bit 4
SCIDRL.R3_T3 3 Received/Transmit bit 3
SCIDRL.R2_T2 2 Received/Transmit bit 2
SCIDRL.R1_T1 1 Received/Transmit bit 1
SCIDRL.R0_T0 0 Received/Transmit bit 0
; SPI
SPICR1 0x0000 SPI Control Register 1
SPICR1.SPIE 7 SPI Interrupt Enable Bit
SPICR1.SPE 6 SPI System Enable Bit
SPICR1.SPTIE 5 SPI Transmit Interrupt Enable
SPICR1.MSTR 4 SPI Master/Slave Mode Select Bit
SPICR1.CPOL 3 SPI Clock Polarity Bit
SPICR1.CPHA 2 SPI Clock Phase Bit
SPICR1.SSOE 1 Slave Select Output Enable
SPICR1.LSBFE 0 SPI LSB-First Enable
SPICR2 0x0001 SPI Control Register 2
SPICR2.MODFEN 4 Mode Fault Enable Bit
SPICR2.BIDIROE 3 Output enable in the Bidirectional mode of operation
SPICR2.SPISWAI 1 SPI Stop in Wait Mode Bit
SPICR2.SPC0 0 Serial Pin Control Bit 0
SPIBR 0x0002 SPI Baud Rate Register
SPIBR.SPPR2 6 SPI Baud Rate Preselection Bit 2
SPIBR.SPPR1 5 SPI Baud Rate Preselection Bit 1
SPIBR.SPPR0 4 SPI Baud Rate Preselection Bit 0
SPIBR.SPR2 2 SPI Baud Rate Selection Bit 2
SPIBR.SPR1 1 SPI Baud Rate Selection Bit 1
SPIBR.SPR0 0 SPI Baud Rate Selection Bit 0
SPISR 0x0003 SPI Status Register
SPISR.SPIF 7 SPIF Interrupt Flag
SPISR.SPTEF 5 SPI Transmit Empty Interrupt Flag
SPISR.MODF 4 Mode Fault Flag
RESERVED004 0x0004 RESERVED
SPIDR 0x0005 SPI Data Register
RESERVED006 0x0006 RESERVED
RESERVED007 0x0007 RESERVED
.MC9S12A256B