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|
Version:
9.0~240807-1.fc42 ▾
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;; Copied from m7900.cfg
; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; MITSUBISHI 7900 SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:
; area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
; START and END are addresses, the end address is not included
; Interrupt vectors are declared in the following way:
; entry NAME ADDRESS COMMENT
.default snes
.snes
; --------------------- PPU Picture Processing Unit (Write-Only Ports)
INIDISP 0x2100 Display Control 1 (a000bbbb a: 0=screen on 1=screen off, b = brightness)
OBSEL 0x2101 Object Size and Object Base (aaabbccc a = Size, b = Name Selection, c = Base Selection)
OAMADDL 0x2102 OAM Address (lower 8bit)
OAMADDH 0x2103 OAM Address (upper 1bit) and Priority Rotation
OAMDATA 0x2104 OAM Data Write (write-twice)
BGMODE 0x2105 BG Mode and BG Character Size (abcdefff abcd = BG tile size (4321): 0 = 8x8 1 = 16x16, e = BG 3 High Priority, f = BG Mode)
MOSAIC 0x2106 Mosaic Size and Mosaic Enable (aaaabbbb a = Mosaic Size b = Mosaic BG Enable)
BG1SC 0x2107 BG1 Screen Base and Screen Size (aaaaaabb a = Screen Base Address (Upper 6-bit), b = Screen Size)
BG2SC 0x2108 BG2 Screen Base and Screen Size (aaaaaabb a = Screen Base Address (Upper 6-bit), b = Screen Size)
BG3SC 0x2109 BG3 Screen Base and Screen Size (aaaaaabb a = Screen Base Address (Upper 6-bit), b = Screen Size)
BG4SC 0x210a BG4 Screen Base and Screen Size (aaaaaabb a = Screen Base Address (Upper 6-bit), b = Screen Size)
BG12NBA 0x210b BG Character Data Area Designation (aaaabbbb a = BG 2 Tile Base Address, b = BG 1 Tile Base Address)
BG34NBA 0x210c BG Character Data Area Designation (aaaabbbb a = BG 4 Tile Base Address, b = BG 3 Tile Base Address)
BG1HOFS 0x210d BG1 Horizontal Scroll (X) (write-twice) / M7HOFS
BG1VOFS 0x210e BG1 Vertical Scroll (Y) (write-twice) / M7VOFS
BG2HOFS 0x210f BG2 Horizontal Scroll (X) (write-twice)
BG2VOFS 0x2110 BG2 Vertical Scroll (Y) (write-twice)
BG3HOFS 0x2111 BG3 Horizontal Scroll (X) (write-twice)
BG3VOFS 0x2112 BG3 Vertical Scroll (Y) (write-twice)
BG4HOFS 0x2113 BG4 Horizontal Scroll (X) (write-twice)
BG4VOFS 0x2114 BG4 Vertical Scroll (Y) (write-twice)
VMAIN 0x2115 VRAM Address Increment Mode
VMADDL 0x2116 VRAM Address (lower 8bit)
VMADDH 0x2117 VRAM Address (upper 8bit)
VMDATAL 0x2118 VRAM Data Write (lower 8bit)
VMDATAH 0x2119 VRAM Data Write (upper 8bit)
M7SEL 0x211a Rotation/Scaling Mode Settings (aa0000bc a = Screen Over b = Vertical Flip c = Horizontal Flip)
M7A 0x211b Rotation/Scaling Parameter A & Maths 16bit operand
M7B 0x211c Rotation/Scaling Parameter B & Maths 8bit operand
M7C 0x211d Rotation/Scaling Parameter C (write-twice)
M7D 0x211e Rotation/Scaling Parameter D (write-twice)
M7X 0x211f Rotation/Scaling Center Coordinate X (write-twice)
M7Y 0x2120 Rotation/Scaling Center Coordinate Y (write-twice)
CGADD 0x2121 Palette CGRAM Address
CGDATA 0x2122 Palette CGRAM Data Write (write-twice)
W12SEL 0x2123 Window BG1/BG2 Mask Settings (aaaabbbb a = BG 2 Window Settings b = BG 1 Window Settings)
W34SEL 0x2124 Window BG3/BG4 Mask Settings (aaaabbbb a = BG 4 Window Settings b = BG 3 Window Settings)
WOBJSEL 0x2125 Window OBJ/MATH Mask Settings (aaaabbbb a = Color Window Settings b = OBJ Window Settings)
WH0 0x2126 Window 1 Left Position (X1)
WH1 0x2127 Window 1 Right Position (X2)
WH2 0x2128 Window 2 Left Position (X1)
WH3 0x2129 Window 2 Right Position (X2)
WBGLOG 0x212a Window 1/2 Mask Logic (BG1-BG4) (aabbccdd a = Bg4, b = Bg3, c = Bg2, d = Bg1)
WOBJLOG 0x212b Window 1/2 Mask Logic (OBJ/MATH) (0000aabb a = Color Window b = OBJ Window)
TM 0x212c Main Screen Designation (000abcde a = Object b = Bg4 c = Bg3 d = Bg2 e = Bg1)
TS 0x212d Sub Screen Designation (000abcde a = Object b = Bg4 c = Bg3 d = Bg2 e = Bg1)
TMW 0x212e Window Area Main Screen Disable (000abcde a = Object b = Bg4 c = Bg3 d = Bg2 e = Bg1)
TSW 0x212f Window Area Sub Screen Disable (000abcde a = Object b = Bg4 c = Bg3 d = Bg2 e = Bg1)
CGWSEL 0x2130 Color Math Control Register A (aabb00cd a = Main Color Window On/Off, b = Sub Color Window On/Off, c = Fixed Color Add/Subtract Enable, d = Direct Select)
CGADSUB 0x2131 Color Math Control Register B (abcdefgh a = 0 for Addition, 1 for Subtraction, b = 1/2 Enable c = Back Enable, d = Object Enable, efgh = Enable Bg 4, 3, 2, 1)
COLDATA 0x2132 Color Math Sub Screen Backdrop Color (abcddddd a = Blue b = Green c = Red ddddd = Color Data)
SETINI 0x2133 Display Control 2 (ab00cdef a = External Sync, b = ExtBG Mode, c = Pseudo 512 Mode, d = Vertical Size, e = Object-V Select, f = Interlace)
; --------------------- PPU Picture Processing Unit (Read-Only Ports)
MPYL 0x2134 PPU1 Signed Multiply Result (lower 8bit)
MPYM 0x2135 PPU1 Signed Multiply Result (middle 8bit)
MPYH 0x2136 PPU1 Signed Multiply Result (upper 8bit)
SLHV 0x2137 PPU1 Latch H/V-Counter by Software (Read=Strobe)
RDOAM 0x2138 PPU1 OAM Data Read (read-twice)
RDVRAML 0x2139 PPU1 VRAM Data Read (lower 8bits)
RDVRAMH 0x213a PPU1 VRAM Data Read (upper 8bits)
RDCGRAM 0x213b PPU2 CGRAM Data Read (Palette) (read-twice)
OPHCT 0x213c PPU2 Horizontal Counter Latch (read-twice)
OPVCT 0x213d PPU2 Vertical Counter Latch (read-twice)
STAT77 0x213e PPU1 Status and PPU1 Version Number
STAT78 0x213f PPU2 Status and PPU2 Version Number
; --------------------- APU Audio Processing Unit (R/W)
APUI00 0x2140 Main CPU to Sound CPU Communication Port 0
APUI01 0x2141 Main CPU to Sound CPU Communication Port 1
APUI02 0x2142 Main CPU to Sound CPU Communication Port 2
APUI03 0x2143 Main CPU to Sound CPU Communication Port 3
; --------------------- WRAM Access
WMDATA 0x2180 WRAM Data Read/Write (R/W)
WMADDL 0x2181 WRAM Address (lower 8bit) (W)
WMADDM 0x2182 WRAM Address (middle 8bit) (W)
WMADDH 0x2183 WRAM Address (upper 1bit) (W)
; --------------------- CPU On-Chip I/O Ports
JOYA 0x4016 Joypad Input Register A (R) / Joypad Output (W)
JOYB 0x4017 Joypad Input Register B (R)
; --------------------- CPU On-Chip I/O Ports (Write-only) (Read=open bus)
NMITIMEN 0x4200 Interrupt Enable and Joypad Request (a0bc000d a = NMI b = V-Count c = H-Count d = Joypad)
WRIO 0x4201 Joypad Programmable I/O Port (Open-Collector Output)
WRMPYA 0x4202 Set unsigned 8bit Multiplicand
WRMPYB 0x4203 Set unsigned 8bit Multiplier and Start Multiplication
WRDIVL 0x4204 Set unsigned 16bit Dividend (lower 8bit)
WRDIVH 0x4205 Set unsigned 16bit Dividend (upper 8bit)
WRDIVB 0x4206 Set unsigned 8bit Divisor and Start Division
HTIMEL 0x4207 H-Count Timer Setting (lower 8bits)
HTIMEH 0x4208 H-Count Timer Setting (upper 1bit)
VTIMEL 0x4209 V-Count Timer Setting (lower 8bits)
VTIMEH 0x420a V-Count Timer Setting (upper 1bit)
MDMAEN 0x420b Select General Purpose DMA Channel(s) and Start Transfer (abcdefgh a = Channel 7...h = Channel 0: 1 = Enable 0 = Disable
HDMAEN 0x420c Select H-Blank DMA (H-DMA) Channel(s) (abcdefgh a = Channel 7 .. h = Channel 0: 1 = Enable 0 = Disable
MEMSEL 0x420d Memory-2 Waitstate Control (0000000a a: 0 = 2.68 MHz, 1 = 3.58 MHz
; --------------------- CPU On-Chip I/O Ports (Read-only)
RDNMI 0x4210 V-Blank NMI Flag and CPU Version Number (Read/Ack)
TIMEUP 0x4211 H/V-Timer IRQ Flag (Read/Ack)
HVBJOY 0x4212 H/V-Blank flag and Joypad Busy flag (R)
RDIO 0x4213 Joypad Programmable I/O Port (Input)
RDDIVL 0x4214 Unsigned Division Result (Quotient) (lower 8bit)
RDDIVH 0x4215 Unsigned Division Result (Quotient) (upper 8bit)
RDMPYL 0x4216 Unsigned Division Remainder / Multiply Product (lower 8bit)
RDMPYH 0x4217 Unsigned Division Remainder / Multiply Product (upper 8bit)
JOY1L 0x4218 Joypad 1 (gameport 1, pin 4) (lower 8bit) (abcd0000 a = Button A b = X c = L d = R)
JOY1H 0x4219 Joypad 1 (gameport 1, pin 4) (upper 8bit) (abcdefgh a = B b = Y c = Select d = Start efgh = Up/Dn/Lt/Rt)
JOY2L 0x421a Joypad 2 (gameport 2, pin 4) (lower 8bit)
JOY2H 0x421b Joypad 2 (gameport 2, pin 4) (upper 8bit)
JOY3L 0x421c Joypad 3 (gameport 1, pin 5) (lower 8bit)
JOY3H 0x421d Joypad 3 (gameport 1, pin 5) (upper 8bit)
JOY4L 0x421e Joypad 4 (gameport 2, pin 5) (lower 8bit)
JOY4H 0x421f Joypad 4 (gameport 2, pin 5) (upper 8bit)
; --------------------- DMA
DMAP0 0x4300 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD0 0x4301 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T0L 0x4302 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T0H 0x4303 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B0 0x4304 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS0L 0x4305 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS0H 0x4306 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS00 0x4307 Indirect HDMA Address (bank)
A2A0L 0x4308 HDMA Table Current Address (low)
A2A0H 0x4309 HDMA Table Current Address (high)
NTRL0 0x430a HDMA Line-Counter (from current Table entry)
UNUSED0 0x430b Unused byte (read/write-able)
MIRR0 0x430f Mirror of 430Bh (R/W)
DMAP1 0x4310 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD1 0x4311 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T1L 0x4312 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T1H 0x4313 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B1 0x4314 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS1L 0x4315 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS1H 0x4316 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS10 0x4317 Indirect HDMA Address (bank)
A2A1L 0x4318 HDMA Table Current Address (low)
A2A1H 0x4319 HDMA Table Current Address (high)
NTRL1 0x431a HDMA Line-Counter (from current Table entry)
UNUSED1 0x431b Unused byte (read/write-able)
MIRR1 0x431f Mirror of 431Bh (R/W)
DMAP2 0x4320 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD2 0x4321 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T2L 0x4322 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T2H 0x4323 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B2 0x4324 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS2L 0x4325 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS2H 0x4326 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS20 0x4327 Indirect HDMA Address (bank)
A2A2L 0x4328 HDMA Table Current Address (low)
A2A2H 0x4329 HDMA Table Current Address (high)
NTRL2 0x432a HDMA Line-Counter (from current Table entry)
UNUSED2 0x432b Unused byte (read/write-able)
MIRR2 0x432f Mirror of 432Bh (R/W)
DMAP3 0x4330 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD3 0x4331 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T3L 0x4332 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T3H 0x4333 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B3 0x4334 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS3L 0x4335 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS3H 0x4336 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS30 0x4337 Indirect HDMA Address (bank)
A2A3L 0x4338 HDMA Table Current Address (low)
A2A3H 0x4339 HDMA Table Current Address (high)
NTRL3 0x433a HDMA Line-Counter (from current Table entry)
UNUSED3 0x433b Unused byte (read/write-able)
MIRR3 0x433f Mirror of 433Bh (R/W)
DMAP4 0x4340 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD4 0x4341 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T4L 0x4342 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T4H 0x4343 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B4 0x4344 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS4L 0x4345 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS4H 0x4346 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS40 0x4347 Indirect HDMA Address (bank)
A2A4L 0x4348 HDMA Table Current Address (low)
A2A4H 0x4349 HDMA Table Current Address (high)
NTRL4 0x434a HDMA Line-Counter (from current Table entry)
UNUSED4 0x434b Unused byte (read/write-able)
MIRR4 0x434f Mirror of 434Bh (R/W)
DMAP5 0x4350 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD5 0x4351 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T5L 0x4352 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T5H 0x4353 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B5 0x4354 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS5L 0x4355 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS5H 0x4356 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS50 0x4357 Indirect HDMA Address (bank)
A2A5L 0x4358 HDMA Table Current Address (low)
A2A5H 0x4359 HDMA Table Current Address (high)
NTRL5 0x435a HDMA Line-Counter (from current Table entry)
UNUSED5 0x435b Unused byte (read/write-able)
MIRR5 0x435f Mirror of 435Bh (R/W)
DMAP6 0x4360 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD6 0x4361 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T6L 0x4362 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T6H 0x4363 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B6 0x4364 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS6L 0x4365 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS6H 0x4366 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS60 0x4367 Indirect HDMA Address (bank)
A2A6L 0x4368 HDMA Table Current Address (low)
A2A6H 0x4369 HDMA Table Current Address (high)
NTRL6 0x436a HDMA Line-Counter (from current Table entry)
UNUSED6 0x436b Unused byte (read/write-able)
MIRR6 0x436f Mirror of 436Bh (R/W)
DMAP7 0x4370 DMA/HDMA Parameters (ab0cdeee a = Direction b = Type c = Inc/Dec d = Auto/Fixed e = Word Size Select)
BBAD7 0x4371 DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus)
A1T7L 0x4372 HDMA Table Start Address (low) / DMA Curr Addr (low)
A1T7H 0x4373 HDMA Table Start Address (high) / DMA Curr Addr (high)
A1B7 0x4374 HDMA Table Start Address (bank) / DMA Curr Addr (bank)
DAS7L 0x4375 Indirect HDMA Address (low) / DMA Byte-Counter (low)
DAS7H 0x4376 Indirect HDMA Address (high) / DMA Byte-Counter (high)
DAS70 0x4377 Indirect HDMA Address (bank)
A2A7L 0x4378 HDMA Table Current Address (low)
A2A7H 0x4379 HDMA Table Current Address (high)
NTRL7 0x437a HDMA Line-Counter (from current Table entry)
UNUSED7 0x437b Unused byte (read/write-able)
MIRR7 0x437f Mirror of 437Bh (R/W)
.superfx
; --------------------- GSU I/O Map
R0 0x3000 Default source/destination register (Sreg/Dreg) (R/W)
R1 0x3002 PLOT opcode: X coordinate (0000h on reset) (R/W)
R2 0x3004 PLOT opcode: Y coordinate (0000h on reset) (R/W)
R3 0x3006 General purpose (R/W)
R4 0x3008 LMULT opcode: lower 16bits of result (R/W)
R5 0x300a General purpose (R/W)
R6 0x300c LMULT and FMULT opcodes: multiplier (R/W)
R7 0x300e MERGE opcode (R/W)
R8 0x3010 MERGE opcode (R/W)
R9 0x3012 General purpose (R/W)
R10 0x3014 General purpose (conventionally stack pointer) (R/W)
R11 0x3016 LINK opcode: destination (R/W)
R12 0x3018 LOOP opcode: counter (R/W)
R13 0x301a LOOP opcode: address (R/W)
R14 0x301c GETxx opcodes: Game Pak ROM Address Pointer (R/W)
R15 0x301e Program Counter, writing MSB starts GSU operation (R/W)
SFR 0x3030 Status/Flag Register (R) (Bit1-5: R/W)
BRAMR 0x3033 Back-up RAM Register (W)
PBR 0x3034 Program Bank Register (8bit, bank 00h..FFh) (R/W)
ROMBR 0x3036 Game Pak ROM Bank Register (8bit, bank 00h..FFh) (R)
CFGR 0x3037 Config Register (W)
SCBR 0x3038 Screen Base Register (8bit, in 1Kbyte units) (W)
CLSR 0x3039 Clock Select Register (W)
SCMR 0x303a Screen Mode Register (W)
VCR 0x303b Version Code Register (R)
RAMBR 0x303c Game Pak RAM Bank Register (1bit, bank 70h/71h) (R)
CBR 0x303e Cache Base Register (in upper 12bit; lower 4bit=unused) (R)
.sa1
; --------------------- SA-1 I/O Map (Write Only Registers)
CCNT 0x2200 SA-1 CPU Control (W)
SIE 0x2201 SNES CPU Int Enable (W)
SIC 0x2202 SNES CPU Int Clear (W)
CRV 0x2203 SA-1 CPU Reset Vector Lsb (W)
CNVL 0x2205 SA-1 CPU NMI Vector Lsb (W)
CNVH 0x2206 SA-1 CPU NMI Vector Msb (W)
CIVL 0x2207 SA-1 CPU IRQ Vector Lsb (W)
CIVH 0x2208 SA-1 CPU IRQ Vector Msb (W)
SCNT 0x2209 SNES CPU Control (W)
CIE 0x220a SA-1 CPU Int Enable (W)
CIC 0x220b SA-1 CPU Int Clear (W)
SNVL 0x220c SNES CPU NMI Vector Lsb (W)
SNVH 0x220d SNES CPU NMI Vector Msb (W)
SIVL 0x220e SNES CPU IRQ Vector Lsb (W)
SIVH 0x220f SNES CPU IRQ Vector Msb (W)
TMC 0x2210 H/V Timer Control (W)
CTR 0x2211 SA-1 CPU Timer Restart (W)
HCNTL 0x2212 Set H-Count Lsb (W)
HCNTH 0x2213 Set H-Count Msb (W)
VCNTL 0x2214 Set V-Count Lsb (W)
VCNTH 0x2215 Set V-Count Msb (W)
CXB 0x2220 MMC Bank C - Hirom C0h-CFh / LoRom 00h-1Fh (W)
DXB 0x2221 MMC Bank D - Hirom D0h-DFh / LoRom 20h-3Fh (W)
EXB 0x2222 MMC Bank E - Hirom E0h-EFh / LoRom 80h-9Fh (W)
FXB 0x2223 MMC Bank F - Hirom F0h-FFh / LoRom A0h-BFh (W)
BMAPS 0x2224 SNES CPU BW-RAM Mapping to 6000h-7FFFh (W)
BMAP 0x2225 SA-1 CPU BW-RAM Mapping to 6000h-7FFFh (W)
SBWE 0x2226 SNES CPU BW-RAM Write Enable (W)
CBWE 0x2227 SA-1 CPU BW-RAM Write Enable (W)
BWPA 0x2228 BW-RAM Write-Protected Area (W)
SIWP 0x2229 SNES I-RAM Write-Protection (W)
CIWP 0x222a SA-1 I-RAM Write-Protection (W)
DCNT 0x2230 DMA Control (W)
CDMA 0x2231 Character Conversion DMA Parameters (W)
SDAL 0x2232 DMA Source Device Start Address Lsb (W)
SDAM 0x2233 DMA Source Device Start Address Mid (W)
SDAH 0x2234 DMA Source Device Start Address Msb (W)
DDAL 0x2235 DMA Dest Device Start Address Lsb (W)
DDAM 0x2236 DMA Dest Device Start Address Mid (Start/I-RAM) (W)
DDAH 0x2237 DMA Dest Device Start Address Msb (Start/BW-RAM)(W)
DTCL 0x2238 DMA Terminal Counter Lsb (W)
DTCH 0x2239 DMA Terminal Counter Msb (W)
BBF 0x223f BW-RAM Bit Map Format for 600000h-6FFFFFh (W)
BRF0 0x2240 Bit Map Register File (W)
BRF1 0x2241 Bit Map Register File (W)
BRF2 0x2242 Bit Map Register File (W)
BRF3 0x2243 Bit Map Register File (W)
BRF4 0x2244 Bit Map Register File (W)
BRF5 0x2245 Bit Map Register File (W)
BRF6 0x2246 Bit Map Register File (W)
BRF7 0x2247 Bit Map Register File (W)
BRF8 0x2248 Bit Map Register File (W)
BRF9 0x2249 Bit Map Register File (W)
BRFA 0x224a Bit Map Register File (W)
BRFB 0x224b Bit Map Register File (W)
BRFC 0x224c Bit Map Register File (W)
BRFD 0x224d Bit Map Register File (W)
BRFE 0x224e Bit Map Register File (W)
BRFF 0x224f Bit Map Register File (W)
MCNT 0x2250 Arithmetic Control (W)
MAL 0x2251 Arithmetic Param A Lsb (Multiplicand/Dividend) (W)
MAH 0x2252 Arithmetic Param A Msb (Multiplicand/Dividend) (W)
MBL 0x2253 Arithmetic Param B Lsb (Multiplier/Divisor) (W)
MBH 0x2254 Arithmetic Param B Msb (Multiplier/Divisor)/Start (W)
VBD 0x2258 Variable-Length Bit Processing (W)
VDAL 0x2259 Var-Length Bit Game Pak ROM Start Address Lsb (W)
VDAM 0x225a Var-Length Bit Game Pak ROM Start Address Mid (W)
VDAH 0x225b Var-Length Bit Game Pak ROM Start Address Msb & Kick
; --------------------- SA-1 I/O Map (Read Only Registers)
SFR 0x2300 SNES CPU Flag Read (R)
CFR 0x2301 SA-1 CPU Flag Read (R)
HCRL 0x2302 H-Count Read Lsb / Do Latching (R)
HCRH 0x2303 H-Count Read Msb (R)
VCRL 0x2304 V-Count Read Lsb (R)
VCRH 0x2305 V-Count Read Msb (R)
MRAL 0x2306 Arithmetic Result, bit0-7 (Sum/Product/Quotient) (R)
MRAH 0x2307 Arithmetic Result, bit8-15 (Sum/Product/Quotient) (R)
MRBL 0x2308 Arithmetic Result, bit16-23 (Sum/Product/Remainder) (R)
MRBH 0x2309 Arithmetic Result, bit24-31 (Sum/Product/Remainder) (R)
MRC 0x230a Arithmetic Result, bit32-39 (Sum) (R)
OF 0x230b Arithmetic Overflow Flag (R)
VDPL 0x230c Variable-Length Data Read Port Lsb (R)
VDPH 0x230d Variable-Length Data Read Port Msb (R)
VC 0x230e Version Code Register (R)
.cx4
.spc7110
.sdd1
.sharprtc
.epsonrtc
.obc1
.dsp1
.dsp2
.dsp3
.dsp4
.st010
.st011
.st018