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|
Version:
9.0~240807-1.fc42 ▾
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; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;-------------------------
; SUPER10 SPECIFIC LINES
;-------------------------
;
; the processor definition may include the memory configuration.
; the line format is:
; area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
; START and END are addresses, the end address is not included
; Interrupt vectors are declared in the following way:
; entry NAME ADDRESS COMMENT
.default ST_SUPER10
.ST_SUPER10
; 8612.pdf
; for the M340 - M341 - M342 Super10
; MEMORY MAP
area DATA MEM_EXT 0x0000:0x8000 External Memory
area DATA MEM_DATA 0x8000:0xE000 On-chip Memory Data
area BSS RESERVED 0xE000:0xEC00
area DATA IO_INT 0xEC00:0xF000 Internal-IO Area
area DATA E_SFR 0xF000:0xF200 ESFR Area
area DATA DPRAM 0xF200:0xFE00
area DATA SFR 0xFE00:0x10000 SFR Area
; Interrupt and reset vector assignments
entry RESET 0x0000 RESET
entry NMITRAP 0x0008 Non-Maskable Interrupt
entry STOTRAP 0x0010 Stack Overflow
entry STUTRAP 0x0018 Stack Underflow
entry SBRKTRAP 0x0020 Software Break
entry BTRAP 0x0028 BTRAP
; INPUT/OUTPUT PORTS
; Interrupt and PEC Registers
FINT0CSP 0xEC00 Fast Interrupt 0 CSP Register
FINT0CSP.EN 15 Fast Interrupt Enable
FINT0CSP.ILVL_11 11 Interrupt Priority Level - bit 11
FINT0CSP.ILVL_10 10 Interrupt Priority Level - bit 10
FINT0CSP.GLVL_9 9 Group Priority Level - bit 9
FINT0CSP.GLVL_8 8 Group Priority Level - bit 8
FINT0CSP.SEG_7 7 Segment Number of Interrupt Service Routine - bit 7
FINT0CSP.SEG_6 6 Segment Number of Interrupt Service Routine - bit 6
FINT0CSP.SEG_5 5 Segment Number of Interrupt Service Routine - bit 5
FINT0CSP.SEG_4 4 Segment Number of Interrupt Service Routine - bit 4
FINT0CSP.SEG_3 3 Segment Number of Interrupt Service Routine - bit 3
FINT0CSP.SEG_2 2 Segment Number of Interrupt Service Routine - bit 2
FINT0CSP.SEG_1 1 Segment Number of Interrupt Service Routine - bit 1
FINT0CSP.SEG_0 0 Segment Number of Interrupt Service Routine - bit 0
FINT0ADDR 0xEC02 Fast Interrupt 0 Address Register
FINT0ADDR.ADDR_15 15 Address of Interrupt Service Routine - bit 15
FINT0ADDR.ADDR_14 14 Address of Interrupt Service Routine - bit 14
FINT0ADDR.ADDR_13 13 Address of Interrupt Service Routine - bit 13
FINT0ADDR.ADDR_12 12 Address of Interrupt Service Routine - bit 12
FINT0ADDR.ADDR_11 11 Address of Interrupt Service Routine - bit 11
FINT0ADDR.ADDR_10 10 Address of Interrupt Service Routine - bit 10
FINT0ADDR.ADDR_9 9 Address of Interrupt Service Routine - bit 9
FINT0ADDR.ADDR_8 8 Address of Interrupt Service Routine - bit 8
FINT0ADDR.ADDR_7 7 Address of Interrupt Service Routine - bit 7
FINT0ADDR.ADDR_6 6 Address of Interrupt Service Routine - bit 6
FINT0ADDR.ADDR_5 5 Address of Interrupt Service Routine - bit 5
FINT0ADDR.ADDR_4 4 Address of Interrupt Service Routine - bit 4
FINT0ADDR.ADDR_3 3 Address of Interrupt Service Routine - bit 3
FINT0ADDR.ADDR_2 2 Address of Interrupt Service Routine - bit 2
FINT0ADDR.ADDR_1 1 Address of Interrupt Service Routine - bit 1
FINT1CSP 0xEC04 Fast Interrupt 1 CSP Register
FINT1CSP.EN 15 Fast Interrupt Enable
FINT1CSP.ILVL_11 11 Interrupt Priority Level - bit 11
FINT1CSP.ILVL_10 10 Interrupt Priority Level - bit 10
FINT1CSP.GLVL_9 9 Group Priority Level - bit 9
FINT1CSP.GLVL_8 8 Group Priority Level - bit 8
FINT1CSP.SEG_7 7 Segment Number of Interrupt Service Routine - bit 7
FINT1CSP.SEG_6 6 Segment Number of Interrupt Service Routine - bit 6
FINT1CSP.SEG_5 5 Segment Number of Interrupt Service Routine - bit 5
FINT1CSP.SEG_4 4 Segment Number of Interrupt Service Routine - bit 4
FINT1CSP.SEG_3 3 Segment Number of Interrupt Service Routine - bit 3
FINT1CSP.SEG_2 2 Segment Number of Interrupt Service Routine - bit 2
FINT1CSP.SEG_1 1 Segment Number of Interrupt Service Routine - bit 1
FINT1CSP.SEG_0 0 Segment Number of Interrupt Service Routine - bit 0
FINT1ADDR 0xEC06 Fast Interrupt 1 Address Register
FINT1ADDR.ADDR_15 15 Address of Interrupt Service Routine - bit 15
FINT1ADDR.ADDR_14 14 Address of Interrupt Service Routine - bit 14
FINT1ADDR.ADDR_13 13 Address of Interrupt Service Routine - bit 13
FINT1ADDR.ADDR_12 12 Address of Interrupt Service Routine - bit 12
FINT1ADDR.ADDR_11 11 Address of Interrupt Service Routine - bit 11
FINT1ADDR.ADDR_10 10 Address of Interrupt Service Routine - bit 10
FINT1ADDR.ADDR_9 9 Address of Interrupt Service Routine - bit 9
FINT1ADDR.ADDR_8 8 Address of Interrupt Service Routine - bit 8
FINT1ADDR.ADDR_7 7 Address of Interrupt Service Routine - bit 7
FINT1ADDR.ADDR_6 6 Address of Interrupt Service Routine - bit 6
FINT1ADDR.ADDR_5 5 Address of Interrupt Service Routine - bit 5
FINT1ADDR.ADDR_4 4 Address of Interrupt Service Routine - bit 4
FINT1ADDR.ADDR_3 3 Address of Interrupt Service Routine - bit 3
FINT1ADDR.ADDR_2 2 Address of Interrupt Service Routine - bit 2
FINT1ADDR.ADDR_1 1 Address of Interrupt Service Routine - bit 1
BNKSEL0 0xEC20 Bank Selection Register 0
BNKSEL0.GPRSEL7_15 15 Register Bank Selection - bit 7_15
BNKSEL0.GPRSEL7_14 14 Register Bank Selection - bit 7_14
BNKSEL0.GPRSEL6_13 13 Register Bank Selection - bit 6_13
BNKSEL0.GPRSEL6_12 12 Register Bank Selection - bit 6_12
BNKSEL0.GPRSEL5_11 11 Register Bank Selection - bit 5_11
BNKSEL0.GPRSEL5_10 10 Register Bank Selection - bit 5_10
BNKSEL0.GPRSEL4_9 9 Register Bank Selection - bit 4_9
BNKSEL0.GPRSEL4_8 8 Register Bank Selection - bit 4_8
BNKSEL0.GPRSEL3_7 7 Register Bank Selection - bit 3_7
BNKSEL0.GPRSEL3_6 6 Register Bank Selection - bit 3_6
BNKSEL0.GPRSEL2_5 5 Register Bank Selection - bit 2_5
BNKSEL0.GPRSEL2_4 4 Register Bank Selection - bit 2_4
BNKSEL0.GPRSEL1_3 3 Register Bank Selection - bit 1_3
BNKSEL0.GPRSEL1_2 2 Register Bank Selection - bit 1_2
BNKSEL0.GPRSEL0_1 1 Register Bank Selection - bit 0_1
BNKSEL0.GPRSEL0_0 0 Register Bank Selection - bit 0_0
BNKSEL1 0xEC22 Bank Selection Register 1
BNKSEL1.GPRSEL15_15 15 Register Bank Selection - bit 15_15
BNKSEL1.GPRSEL15_14 14 Register Bank Selection - bit 15_14
BNKSEL1.GPRSEL14_13 13 Register Bank Selection - bit 14_13
BNKSEL1.GPRSEL14_12 12 Register Bank Selection - bit 14_12
BNKSEL1.GPRSEL13_11 11 Register Bank Selection - bit 13_11
BNKSEL1.GPRSEL13_10 10 Register Bank Selection - bit 13_10
BNKSEL1.GPRSEL12_9 9 Register Bank Selection - bit 12_9
BNKSEL1.GPRSEL12_8 8 Register Bank Selection - bit 12_8
BNKSEL1.GPRSEL11_7 7 Register Bank Selection - bit 11_7
BNKSEL1.GPRSEL11_6 6 Register Bank Selection - bit 11_6
BNKSEL1.GPRSEL10_5 5 Register Bank Selection - bit 10_5
BNKSEL1.GPRSEL10_4 4 Register Bank Selection - bit 10_4
BNKSEL1.GPRSEL9_3 3 Register Bank Selection - bit 9_3
BNKSEL1.GPRSEL9_2 2 Register Bank Selection - bit 9_2
BNKSEL1.GPRSEL8_1 1 Register Bank Selection - bit 8_1
BNKSEL1.GPRSEL8_0 0 Register Bank Selection - bit 8_0
SRCP0 0xEC40 PEC Channel 0 Source Pointer
SRCP0.SRCP0_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP0.SRCP0_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP0.SRCP0_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP0.SRCP0_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP0.SRCP0_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP0.SRCP0_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP0.SRCP0_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP0.SRCP0_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP0.SRCP0_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP0.SRCP0_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP0.SRCP0_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP0.SRCP0_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP0.SRCP0_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP0.SRCP0_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP0.SRCP0_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP0.SRCP0_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP0 0xEC42 PEC Channel 0 Destination Pointer
DSTP0.DSTP0_15 15 Destination Pointer Address of Channel 0 - bit 15
DSTP0.DSTP0_14 14 Destination Pointer Address of Channel 0 - bit 14
DSTP0.DSTP0_13 13 Destination Pointer Address of Channel 0 - bit 13
DSTP0.DSTP0_12 12 Destination Pointer Address of Channel 0 - bit 12
DSTP0.DSTP0_11 11 Destination Pointer Address of Channel 0 - bit 11
DSTP0.DSTP0_10 10 Destination Pointer Address of Channel 0 - bit 10
DSTP0.DSTP0_9 9 Destination Pointer Address of Channel 0 - bit 9
DSTP0.DSTP0_8 8 Destination Pointer Address of Channel 0 - bit 8
DSTP0.DSTP0_7 7 Destination Pointer Address of Channel 0 - bit 7
DSTP0.DSTP0_6 6 Destination Pointer Address of Channel 0 - bit 6
DSTP0.DSTP0_5 5 Destination Pointer Address of Channel 0 - bit 5
DSTP0.DSTP0_4 4 Destination Pointer Address of Channel 0 - bit 4
DSTP0.DSTP0_3 3 Destination Pointer Address of Channel 0 - bit 3
DSTP0.DSTP0_2 2 Destination Pointer Address of Channel 0 - bit 2
DSTP0.DSTP0_1 1 Destination Pointer Address of Channel 0 - bit 1
DSTP0.DSTP0_0 0 Destination Pointer Address of Channel 0 - bit 0
SRCP1 0xEC44 PEC Channel 1 Source Pointer
SRCP1.SRCP1_15 15 Source Pointer Address of Channel 1 - bit 15
SRCP1.SRCP1_14 14 Source Pointer Address of Channel 1 - bit 14
SRCP1.SRCP1_13 13 Source Pointer Address of Channel 1 - bit 13
SRCP1.SRCP1_12 12 Source Pointer Address of Channel 1 - bit 12
SRCP1.SRCP1_11 11 Source Pointer Address of Channel 1 - bit 11
SRCP1.SRCP1_10 10 Source Pointer Address of Channel 1 - bit 10
SRCP1.SRCP1_9 9 Source Pointer Address of Channel 1 - bit 9
SRCP1.SRCP1_8 8 Source Pointer Address of Channel 1 - bit 8
SRCP1.SRCP1_7 7 Source Pointer Address of Channel 1 - bit 7
SRCP1.SRCP1_6 6 Source Pointer Address of Channel 1 - bit 6
SRCP1.SRCP1_5 5 Source Pointer Address of Channel 1 - bit 5
SRCP1.SRCP1_4 4 Source Pointer Address of Channel 1 - bit 4
SRCP1.SRCP1_3 3 Source Pointer Address of Channel 1 - bit 3
SRCP1.SRCP1_2 2 Source Pointer Address of Channel 1 - bit 2
SRCP1.SRCP1_1 1 Source Pointer Address of Channel 1 - bit 1
SRCP1.SRCP1_0 0 Source Pointer Address of Channel 1 - bit 0
DSTP1 0xEC46 PEC Channel 1 Destination Pointer
DSTP1.DSTP1_15 15 Destination Pointer Address of Channel 1 - bit 15
DSTP1.DSTP1_14 14 Destination Pointer Address of Channel 1 - bit 14
DSTP1.DSTP1_13 13 Destination Pointer Address of Channel 1 - bit 13
DSTP1.DSTP1_12 12 Destination Pointer Address of Channel 1 - bit 12
DSTP1.DSTP1_11 11 Destination Pointer Address of Channel 1 - bit 11
DSTP1.DSTP1_10 10 Destination Pointer Address of Channel 1 - bit 10
DSTP1.DSTP1_9 9 Destination Pointer Address of Channel 1 - bit 9
DSTP1.DSTP1_8 8 Destination Pointer Address of Channel 1 - bit 8
DSTP1.DSTP1_7 7 Destination Pointer Address of Channel 1 - bit 7
DSTP1.DSTP1_6 6 Destination Pointer Address of Channel 1 - bit 6
DSTP1.DSTP1_5 5 Destination Pointer Address of Channel 1 - bit 5
DSTP1.DSTP1_4 4 Destination Pointer Address of Channel 1 - bit 4
DSTP1.DSTP1_3 3 Destination Pointer Address of Channel 1 - bit 3
DSTP1.DSTP1_2 2 Destination Pointer Address of Channel 1 - bit 2
DSTP1.DSTP1_1 1 Destination Pointer Address of Channel 1 - bit 1
DSTP1.DSTP1_0 0 Destination Pointer Address of Channel 1 - bit 0
SRCP2 0xEC48 PEC Channel 2 Source Pointer
SRCP2.SRCP2_15 15 Source Pointer Address of Channel 2 - bit 15
SRCP2.SRCP2_14 14 Source Pointer Address of Channel 2 - bit 14
SRCP2.SRCP2_13 13 Source Pointer Address of Channel 2 - bit 13
SRCP2.SRCP2_12 12 Source Pointer Address of Channel 2 - bit 12
SRCP2.SRCP2_11 11 Source Pointer Address of Channel 2 - bit 11
SRCP2.SRCP2_10 10 Source Pointer Address of Channel 2 - bit 10
SRCP2.SRCP2_9 9 Source Pointer Address of Channel 2 - bit 9
SRCP2.SRCP2_8 8 Source Pointer Address of Channel 2 - bit 8
SRCP2.SRCP2_7 7 Source Pointer Address of Channel 2 - bit 7
SRCP2.SRCP2_6 6 Source Pointer Address of Channel 2 - bit 6
SRCP2.SRCP2_5 5 Source Pointer Address of Channel 2 - bit 5
SRCP2.SRCP2_4 4 Source Pointer Address of Channel 2 - bit 4
SRCP2.SRCP2_3 3 Source Pointer Address of Channel 2 - bit 3
SRCP2.SRCP2_2 2 Source Pointer Address of Channel 2 - bit 2
SRCP2.SRCP2_1 1 Source Pointer Address of Channel 2 - bit 1
SRCP2.SRCP2_0 0 Source Pointer Address of Channel 2 - bit 0
DSTP2 0xEC4A PEC Channel 2 Destination Pointer
DSTP2.DSTP2_15 15 Destination Pointer Address of Channel 2 - bit 15
DSTP2.DSTP2_14 14 Destination Pointer Address of Channel 2 - bit 14
DSTP2.DSTP2_13 13 Destination Pointer Address of Channel 2 - bit 13
DSTP2.DSTP2_12 12 Destination Pointer Address of Channel 2 - bit 12
DSTP2.DSTP2_11 11 Destination Pointer Address of Channel 2 - bit 11
DSTP2.DSTP2_10 10 Destination Pointer Address of Channel 2 - bit 10
DSTP2.DSTP2_9 9 Destination Pointer Address of Channel 2 - bit 9
DSTP2.DSTP2_8 8 Destination Pointer Address of Channel 2 - bit 8
DSTP2.DSTP2_7 7 Destination Pointer Address of Channel 2 - bit 7
DSTP2.DSTP2_6 6 Destination Pointer Address of Channel 2 - bit 6
DSTP2.DSTP2_5 5 Destination Pointer Address of Channel 2 - bit 5
DSTP2.DSTP2_4 4 Destination Pointer Address of Channel 2 - bit 4
DSTP2.DSTP2_3 3 Destination Pointer Address of Channel 2 - bit 3
DSTP2.DSTP2_2 2 Destination Pointer Address of Channel 2 - bit 2
DSTP2.DSTP2_1 1 Destination Pointer Address of Channel 2 - bit 1
DSTP2.DSTP2_0 0 Destination Pointer Address of Channel 2 - bit 0
SRCP3 0xEC4C PEC Channel 3 Source Pointer
SRCP3.SRCP3_15 15 Source Pointer Address of Channel 3 - bit 15
SRCP3.SRCP3_14 14 Source Pointer Address of Channel 3 - bit 14
SRCP3.SRCP3_13 13 Source Pointer Address of Channel 3 - bit 13
SRCP3.SRCP3_12 12 Source Pointer Address of Channel 3 - bit 12
SRCP3.SRCP3_11 11 Source Pointer Address of Channel 3 - bit 11
SRCP3.SRCP3_10 10 Source Pointer Address of Channel 3 - bit 10
SRCP3.SRCP3_9 9 Source Pointer Address of Channel 3 - bit 9
SRCP3.SRCP3_8 8 Source Pointer Address of Channel 3 - bit 8
SRCP3.SRCP3_7 7 Source Pointer Address of Channel 3 - bit 7
SRCP3.SRCP3_6 6 Source Pointer Address of Channel 3 - bit 6
SRCP3.SRCP3_5 5 Source Pointer Address of Channel 3 - bit 5
SRCP3.SRCP3_4 4 Source Pointer Address of Channel 3 - bit 4
SRCP3.SRCP3_3 3 Source Pointer Address of Channel 3 - bit 3
SRCP3.SRCP3_2 2 Source Pointer Address of Channel 3 - bit 2
SRCP3.SRCP3_1 1 Source Pointer Address of Channel 3 - bit 1
SRCP3.SRCP3_0 0 Source Pointer Address of Channel 3 - bit 0
DSTP3 0xEC4E PEC Channel 3 Destination Pointer
DSTP3.DSTP3_15 15 Destination Pointer Address of Channel 3 - bit 15
DSTP3.DSTP3_14 14 Destination Pointer Address of Channel 3 - bit 14
DSTP3.DSTP3_13 13 Destination Pointer Address of Channel 3 - bit 13
DSTP3.DSTP3_12 12 Destination Pointer Address of Channel 3 - bit 12
DSTP3.DSTP3_11 11 Destination Pointer Address of Channel 3 - bit 11
DSTP3.DSTP3_10 10 Destination Pointer Address of Channel 3 - bit 10
DSTP3.DSTP3_9 9 Destination Pointer Address of Channel 3 - bit 9
DSTP3.DSTP3_8 8 Destination Pointer Address of Channel 3 - bit 8
DSTP3.DSTP3_7 7 Destination Pointer Address of Channel 3 - bit 7
DSTP3.DSTP3_6 6 Destination Pointer Address of Channel 3 - bit 6
DSTP3.DSTP3_5 5 Destination Pointer Address of Channel 3 - bit 5
DSTP3.DSTP3_4 4 Destination Pointer Address of Channel 3 - bit 4
DSTP3.DSTP3_3 3 Destination Pointer Address of Channel 3 - bit 3
DSTP3.DSTP3_2 2 Destination Pointer Address of Channel 3 - bit 2
DSTP3.DSTP3_1 1 Destination Pointer Address of Channel 3 - bit 1
DSTP3.DSTP3_0 0 Destination Pointer Address of Channel 3 - bit 0
SRCP4 0xEC50 PEC Channel 4 Source Pointer
SRCP4.SRCP4_15 15 Source Pointer Address of Channel 4 - bit 15
SRCP4.SRCP4_14 14 Source Pointer Address of Channel 4 - bit 14
SRCP4.SRCP4_13 13 Source Pointer Address of Channel 4 - bit 13
SRCP4.SRCP4_12 12 Source Pointer Address of Channel 4 - bit 12
SRCP4.SRCP4_11 11 Source Pointer Address of Channel 4 - bit 11
SRCP4.SRCP4_10 10 Source Pointer Address of Channel 4 - bit 10
SRCP4.SRCP4_9 9 Source Pointer Address of Channel 4 - bit 9
SRCP4.SRCP4_8 8 Source Pointer Address of Channel 4 - bit 8
SRCP4.SRCP4_7 7 Source Pointer Address of Channel 4 - bit 7
SRCP4.SRCP4_6 6 Source Pointer Address of Channel 4 - bit 6
SRCP4.SRCP4_5 5 Source Pointer Address of Channel 4 - bit 5
SRCP4.SRCP4_4 4 Source Pointer Address of Channel 4 - bit 4
SRCP4.SRCP4_3 3 Source Pointer Address of Channel 4 - bit 3
SRCP4.SRCP4_2 2 Source Pointer Address of Channel 4 - bit 2
SRCP4.SRCP4_1 1 Source Pointer Address of Channel 4 - bit 1
SRCP4.SRCP4_0 0 Source Pointer Address of Channel 4 - bit 0
DSTP4 0xEC52 PEC Channel 4 Destination Pointer
DSTP4.DSTP4_15 15 Destination Pointer Address of Channel 4 - bit 15
DSTP4.DSTP4_14 14 Destination Pointer Address of Channel 4 - bit 14
DSTP4.DSTP4_13 13 Destination Pointer Address of Channel 4 - bit 13
DSTP4.DSTP4_12 12 Destination Pointer Address of Channel 4 - bit 12
DSTP4.DSTP4_11 11 Destination Pointer Address of Channel 4 - bit 11
DSTP4.DSTP4_10 10 Destination Pointer Address of Channel 4 - bit 10
DSTP4.DSTP4_9 9 Destination Pointer Address of Channel 4 - bit 9
DSTP4.DSTP4_8 8 Destination Pointer Address of Channel 4 - bit 8
DSTP4.DSTP4_7 7 Destination Pointer Address of Channel 4 - bit 7
DSTP4.DSTP4_6 6 Destination Pointer Address of Channel 4 - bit 6
DSTP4.DSTP4_5 5 Destination Pointer Address of Channel 4 - bit 5
DSTP4.DSTP4_4 4 Destination Pointer Address of Channel 4 - bit 4
DSTP4.DSTP4_3 3 Destination Pointer Address of Channel 4 - bit 3
DSTP4.DSTP4_2 2 Destination Pointer Address of Channel 4 - bit 2
DSTP4.DSTP4_1 1 Destination Pointer Address of Channel 4 - bit 1
DSTP4.DSTP4_0 0 Destination Pointer Address of Channel 4 - bit 0
SRCP5 0xEC54 PEC Channel 5 Source Pointer
SRCP5.SRCP5_15 15 Source Pointer Address of Channel 5 - bit 15
SRCP5.SRCP5_14 14 Source Pointer Address of Channel 5 - bit 14
SRCP5.SRCP5_13 13 Source Pointer Address of Channel 5 - bit 13
SRCP5.SRCP5_12 12 Source Pointer Address of Channel 5 - bit 12
SRCP5.SRCP5_11 11 Source Pointer Address of Channel 5 - bit 11
SRCP5.SRCP5_10 10 Source Pointer Address of Channel 5 - bit 10
SRCP5.SRCP5_9 9 Source Pointer Address of Channel 5 - bit 9
SRCP5.SRCP5_8 8 Source Pointer Address of Channel 5 - bit 8
SRCP5.SRCP5_7 7 Source Pointer Address of Channel 5 - bit 7
SRCP5.SRCP5_6 6 Source Pointer Address of Channel 5 - bit 6
SRCP5.SRCP5_5 5 Source Pointer Address of Channel 5 - bit 5
SRCP5.SRCP5_4 4 Source Pointer Address of Channel 5 - bit 4
SRCP5.SRCP5_3 3 Source Pointer Address of Channel 5 - bit 3
SRCP5.SRCP5_2 2 Source Pointer Address of Channel 5 - bit 2
SRCP5.SRCP5_1 1 Source Pointer Address of Channel 5 - bit 1
SRCP5.SRCP5_0 0 Source Pointer Address of Channel 5 - bit 0
DSTP5 0xEC56 PEC Channel 5 Destination Pointer
DSTP5.DSTP5_15 15 Destination Pointer Address of Channel 5 - bit 15
DSTP5.DSTP5_14 14 Destination Pointer Address of Channel 5 - bit 14
DSTP5.DSTP5_13 13 Destination Pointer Address of Channel 5 - bit 13
DSTP5.DSTP5_12 12 Destination Pointer Address of Channel 5 - bit 12
DSTP5.DSTP5_11 11 Destination Pointer Address of Channel 5 - bit 11
DSTP5.DSTP5_10 10 Destination Pointer Address of Channel 5 - bit 10
DSTP5.DSTP5_9 9 Destination Pointer Address of Channel 5 - bit 9
DSTP5.DSTP5_8 8 Destination Pointer Address of Channel 5 - bit 8
DSTP5.DSTP5_7 7 Destination Pointer Address of Channel 5 - bit 7
DSTP5.DSTP5_6 6 Destination Pointer Address of Channel 5 - bit 6
DSTP5.DSTP5_5 5 Destination Pointer Address of Channel 5 - bit 5
DSTP5.DSTP5_4 4 Destination Pointer Address of Channel 5 - bit 4
DSTP5.DSTP5_3 3 Destination Pointer Address of Channel 5 - bit 3
DSTP5.DSTP5_2 2 Destination Pointer Address of Channel 5 - bit 2
DSTP5.DSTP5_1 1 Destination Pointer Address of Channel 5 - bit 1
DSTP5.DSTP5_0 0 Destination Pointer Address of Channel 5 - bit 0
SRCP6 0xEC58 PEC Channel 6 Source Pointer
SRCP6.SRCP6_15 15 Source Pointer Address of Channel 6 - bit 15
SRCP6.SRCP6_14 14 Source Pointer Address of Channel 6 - bit 14
SRCP6.SRCP6_13 13 Source Pointer Address of Channel 6 - bit 13
SRCP6.SRCP6_12 12 Source Pointer Address of Channel 6 - bit 12
SRCP6.SRCP6_11 11 Source Pointer Address of Channel 6 - bit 11
SRCP6.SRCP6_10 10 Source Pointer Address of Channel 6 - bit 10
SRCP6.SRCP6_9 9 Source Pointer Address of Channel 6 - bit 9
SRCP6.SRCP6_8 8 Source Pointer Address of Channel 6 - bit 8
SRCP6.SRCP6_7 7 Source Pointer Address of Channel 6 - bit 7
SRCP6.SRCP6_6 6 Source Pointer Address of Channel 6 - bit 6
SRCP6.SRCP6_5 5 Source Pointer Address of Channel 6 - bit 5
SRCP6.SRCP6_4 4 Source Pointer Address of Channel 6 - bit 4
SRCP6.SRCP6_3 3 Source Pointer Address of Channel 6 - bit 3
SRCP6.SRCP6_2 2 Source Pointer Address of Channel 6 - bit 2
SRCP6.SRCP6_1 1 Source Pointer Address of Channel 6 - bit 1
SRCP6.SRCP6_0 0 Source Pointer Address of Channel 6 - bit 0
DSTP6 0xEC5A PEC Channel 6 Destination Pointer
DSTP6.DSTP6_15 15 Destination Pointer Address of Channel 6 - bit 15
DSTP6.DSTP6_14 14 Destination Pointer Address of Channel 6 - bit 14
DSTP6.DSTP6_13 13 Destination Pointer Address of Channel 6 - bit 13
DSTP6.DSTP6_12 12 Destination Pointer Address of Channel 6 - bit 12
DSTP6.DSTP6_11 11 Destination Pointer Address of Channel 6 - bit 11
DSTP6.DSTP6_10 10 Destination Pointer Address of Channel 6 - bit 10
DSTP6.DSTP6_9 9 Destination Pointer Address of Channel 6 - bit 9
DSTP6.DSTP6_8 8 Destination Pointer Address of Channel 6 - bit 8
DSTP6.DSTP6_7 7 Destination Pointer Address of Channel 6 - bit 7
DSTP6.DSTP6_6 6 Destination Pointer Address of Channel 6 - bit 6
DSTP6.DSTP6_5 5 Destination Pointer Address of Channel 6 - bit 5
DSTP6.DSTP6_4 4 Destination Pointer Address of Channel 6 - bit 4
DSTP6.DSTP6_3 3 Destination Pointer Address of Channel 6 - bit 3
DSTP6.DSTP6_2 2 Destination Pointer Address of Channel 6 - bit 2
DSTP6.DSTP6_1 1 Destination Pointer Address of Channel 6 - bit 1
DSTP6.DSTP6_0 0 Destination Pointer Address of Channel 6 - bit 0
SRCP7 0xEC5C PEC Channel 7 Source Pointer
SRCP7.SRCP7_15 15 Source Pointer Address of Channel 7 - bit 15
SRCP7.SRCP7_14 14 Source Pointer Address of Channel 7 - bit 14
SRCP7.SRCP7_13 13 Source Pointer Address of Channel 7 - bit 13
SRCP7.SRCP7_12 12 Source Pointer Address of Channel 7 - bit 12
SRCP7.SRCP7_11 11 Source Pointer Address of Channel 7 - bit 11
SRCP7.SRCP7_10 10 Source Pointer Address of Channel 7 - bit 10
SRCP7.SRCP7_9 9 Source Pointer Address of Channel 7 - bit 9
SRCP7.SRCP7_8 8 Source Pointer Address of Channel 7 - bit 8
SRCP7.SRCP7_7 7 Source Pointer Address of Channel 7 - bit 7
SRCP7.SRCP7_6 6 Source Pointer Address of Channel 7 - bit 6
SRCP7.SRCP7_5 5 Source Pointer Address of Channel 7 - bit 5
SRCP7.SRCP7_4 4 Source Pointer Address of Channel 7 - bit 4
SRCP7.SRCP7_3 3 Source Pointer Address of Channel 7 - bit 3
SRCP7.SRCP7_2 2 Source Pointer Address of Channel 7 - bit 2
SRCP7.SRCP7_1 1 Source Pointer Address of Channel 7 - bit 1
SRCP7.SRCP7_0 0 Source Pointer Address of Channel 7 - bit 0
DSTP7 0xEC5E PEC Channel 7 Destination Pointer
DSTP7.DSTP7_15 15 Destination Pointer Address of Channel 7 - bit 15
DSTP7.DSTP7_14 14 Destination Pointer Address of Channel 7 - bit 14
DSTP7.DSTP7_13 13 Destination Pointer Address of Channel 7 - bit 13
DSTP7.DSTP7_12 12 Destination Pointer Address of Channel 7 - bit 12
DSTP7.DSTP7_11 11 Destination Pointer Address of Channel 7 - bit 11
DSTP7.DSTP7_10 10 Destination Pointer Address of Channel 7 - bit 10
DSTP7.DSTP7_9 9 Destination Pointer Address of Channel 7 - bit 9
DSTP7.DSTP7_8 8 Destination Pointer Address of Channel 7 - bit 8
DSTP7.DSTP7_7 7 Destination Pointer Address of Channel 7 - bit 7
DSTP7.DSTP7_6 6 Destination Pointer Address of Channel 7 - bit 6
DSTP7.DSTP7_5 5 Destination Pointer Address of Channel 7 - bit 5
DSTP7.DSTP7_4 4 Destination Pointer Address of Channel 7 - bit 4
DSTP7.DSTP7_3 3 Destination Pointer Address of Channel 7 - bit 3
DSTP7.DSTP7_2 2 Destination Pointer Address of Channel 7 - bit 2
DSTP7.DSTP7_1 1 Destination Pointer Address of Channel 7 - bit 1
DSTP7.DSTP7_0 0 Destination Pointer Address of Channel 7 - bit 0
PECSEG0 0xEC80 PEC Pointer 0 Segment Address Reg.
PECSEG0.SRCSEG0_15 15 Source Pointer Segment Address of Channel 0 - bit 15
PECSEG0.SRCSEG0_14 14 Source Pointer Segment Address of Channel 0 - bit 14
PECSEG0.SRCSEG0_13 13 Source Pointer Segment Address of Channel 0 - bit 13
PECSEG0.SRCSEG0_12 12 Source Pointer Segment Address of Channel 0 - bit 12
PECSEG0.SRCSEG0_11 11 Source Pointer Segment Address of Channel 0 - bit 11
PECSEG0.SRCSEG0_10 10 Source Pointer Segment Address of Channel 0 - bit 10
PECSEG0.SRCSEG0_9 9 Source Pointer Segment Address of Channel 0 - bit 9
PECSEG0.SRCSEG0_8 8 Source Pointer Segment Address of Channel 0 - bit 8
PECSEG0.DSTSEG0_7 7 Destination Pointer Segment Address of Channel 0 - bit 7
PECSEG0.DSTSEG0_6 6 Destination Pointer Segment Address of Channel 0 - bit 6
PECSEG0.DSTSEG0_5 5 Destination Pointer Segment Address of Channel 0 - bit 5
PECSEG0.DSTSEG0_4 4 Destination Pointer Segment Address of Channel 0 - bit 4
PECSEG0.DSTSEG0_3 3 Destination Pointer Segment Address of Channel 0 - bit 3
PECSEG0.DSTSEG0_2 2 Destination Pointer Segment Address of Channel 0 - bit 2
PECSEG0.DSTSEG0_1 1 Destination Pointer Segment Address of Channel 0 - bit 1
PECSEG0.DSTSEG0_0 0 Destination Pointer Segment Address of Channel 0 - bit 0
PECSEG1 0xEC82 PEC Pointer 0 Segment Address Reg.
PECSEG1.SRCSEG1_15 15 Source Pointer Segment Address of Channel 1 - bit 15
PECSEG1.SRCSEG1_14 14 Source Pointer Segment Address of Channel 1 - bit 14
PECSEG1.SRCSEG1_13 13 Source Pointer Segment Address of Channel 1 - bit 13
PECSEG1.SRCSEG1_12 12 Source Pointer Segment Address of Channel 1 - bit 12
PECSEG1.SRCSEG1_11 11 Source Pointer Segment Address of Channel 1 - bit 11
PECSEG1.SRCSEG1_10 10 Source Pointer Segment Address of Channel 1 - bit 10
PECSEG1.SRCSEG1_9 9 Source Pointer Segment Address of Channel 1 - bit 9
PECSEG1.SRCSEG1_8 8 Source Pointer Segment Address of Channel 1 - bit 8
PECSEG1.DSTSEG1_7 7 Destination Pointer Segment Address of Channel 1 - bit 7
PECSEG1.DSTSEG1_6 6 Destination Pointer Segment Address of Channel 1 - bit 6
PECSEG1.DSTSEG1_5 5 Destination Pointer Segment Address of Channel 1 - bit 5
PECSEG1.DSTSEG1_4 4 Destination Pointer Segment Address of Channel 1 - bit 4
PECSEG1.DSTSEG1_3 3 Destination Pointer Segment Address of Channel 1 - bit 3
PECSEG1.DSTSEG1_2 2 Destination Pointer Segment Address of Channel 1 - bit 2
PECSEG1.DSTSEG1_1 1 Destination Pointer Segment Address of Channel 1 - bit 1
PECSEG1.DSTSEG1_0 0 Destination Pointer Segment Address of Channel 1 - bit 0
PECSEG2 0xEC84 PEC Pointer 0 Segment Address Reg.
PECSEG2.SRCSEG2_15 15 Source Pointer Segment Address of Channel 2 - bit 15
PECSEG2.SRCSEG2_14 14 Source Pointer Segment Address of Channel 2 - bit 14
PECSEG2.SRCSEG2_13 13 Source Pointer Segment Address of Channel 2 - bit 13
PECSEG2.SRCSEG2_12 12 Source Pointer Segment Address of Channel 2 - bit 12
PECSEG2.SRCSEG2_11 11 Source Pointer Segment Address of Channel 2 - bit 11
PECSEG2.SRCSEG2_10 10 Source Pointer Segment Address of Channel 2 - bit 10
PECSEG2.SRCSEG2_9 9 Source Pointer Segment Address of Channel 2 - bit 9
PECSEG2.SRCSEG2_8 8 Source Pointer Segment Address of Channel 2 - bit 8
PECSEG2.DSTSEG2_7 7 Destination Pointer Segment Address of Channel 2 - bit 7
PECSEG2.DSTSEG2_6 6 Destination Pointer Segment Address of Channel 2 - bit 6
PECSEG2.DSTSEG2_5 5 Destination Pointer Segment Address of Channel 2 - bit 5
PECSEG2.DSTSEG2_4 4 Destination Pointer Segment Address of Channel 2 - bit 4
PECSEG2.DSTSEG2_3 3 Destination Pointer Segment Address of Channel 2 - bit 3
PECSEG2.DSTSEG2_2 2 Destination Pointer Segment Address of Channel 2 - bit 2
PECSEG2.DSTSEG2_1 1 Destination Pointer Segment Address of Channel 2 - bit 1
PECSEG2.DSTSEG2_0 0 Destination Pointer Segment Address of Channel 2 - bit 0
PECSEG3 0xEC86 PEC Pointer 0 Segment Address Reg.
PECSEG3.SRCSEG3_15 15 Source Pointer Segment Address of Channel 3 - bit 15
PECSEG3.SRCSEG3_14 14 Source Pointer Segment Address of Channel 3 - bit 14
PECSEG3.SRCSEG3_13 13 Source Pointer Segment Address of Channel 3 - bit 13
PECSEG3.SRCSEG3_12 12 Source Pointer Segment Address of Channel 3 - bit 12
PECSEG3.SRCSEG3_11 11 Source Pointer Segment Address of Channel 3 - bit 11
PECSEG3.SRCSEG3_10 10 Source Pointer Segment Address of Channel 3 - bit 10
PECSEG3.SRCSEG3_9 9 Source Pointer Segment Address of Channel 3 - bit 9
PECSEG3.SRCSEG3_8 8 Source Pointer Segment Address of Channel 3 - bit 8
PECSEG3.DSTSEG3_7 7 Destination Pointer Segment Address of Channel 3 - bit 7
PECSEG3.DSTSEG3_6 6 Destination Pointer Segment Address of Channel 3 - bit 6
PECSEG3.DSTSEG3_5 5 Destination Pointer Segment Address of Channel 3 - bit 5
PECSEG3.DSTSEG3_4 4 Destination Pointer Segment Address of Channel 3 - bit 4
PECSEG3.DSTSEG3_3 3 Destination Pointer Segment Address of Channel 3 - bit 3
PECSEG3.DSTSEG3_2 2 Destination Pointer Segment Address of Channel 3 - bit 2
PECSEG3.DSTSEG3_1 1 Destination Pointer Segment Address of Channel 3 - bit 1
PECSEG3.DSTSEG3_0 0 Destination Pointer Segment Address of Channel 3 - bit 0
PECSEG4 0xEC88 PEC Pointer 0 Segment Address Reg.
PECSEG4.SRCSEG4_15 15 Source Pointer Segment Address of Channel 4 - bit 15
PECSEG4.SRCSEG4_14 14 Source Pointer Segment Address of Channel 4 - bit 14
PECSEG4.SRCSEG4_13 13 Source Pointer Segment Address of Channel 4 - bit 13
PECSEG4.SRCSEG4_12 12 Source Pointer Segment Address of Channel 4 - bit 12
PECSEG4.SRCSEG4_11 11 Source Pointer Segment Address of Channel 4 - bit 11
PECSEG4.SRCSEG4_10 10 Source Pointer Segment Address of Channel 4 - bit 10
PECSEG4.SRCSEG4_9 9 Source Pointer Segment Address of Channel 4 - bit 9
PECSEG4.SRCSEG4_8 8 Source Pointer Segment Address of Channel 4 - bit 8
PECSEG4.DSTSEG4_7 7 Destination Pointer Segment Address of Channel 4 - bit 7
PECSEG4.DSTSEG4_6 6 Destination Pointer Segment Address of Channel 4 - bit 6
PECSEG4.DSTSEG4_5 5 Destination Pointer Segment Address of Channel 4 - bit 5
PECSEG4.DSTSEG4_4 4 Destination Pointer Segment Address of Channel 4 - bit 4
PECSEG4.DSTSEG4_3 3 Destination Pointer Segment Address of Channel 4 - bit 3
PECSEG4.DSTSEG4_2 2 Destination Pointer Segment Address of Channel 4 - bit 2
PECSEG4.DSTSEG4_1 1 Destination Pointer Segment Address of Channel 4 - bit 1
PECSEG4.DSTSEG4_0 0 Destination Pointer Segment Address of Channel 4 - bit 0
PECSEG5 0xEC8A PEC Pointer 0 Segment Address Reg.
PECSEG5.SRCSEG5_15 15 Source Pointer Segment Address of Channel 5 - bit 15
PECSEG5.SRCSEG5_14 14 Source Pointer Segment Address of Channel 5 - bit 14
PECSEG5.SRCSEG5_13 13 Source Pointer Segment Address of Channel 5 - bit 13
PECSEG5.SRCSEG5_12 12 Source Pointer Segment Address of Channel 5 - bit 12
PECSEG5.SRCSEG5_11 11 Source Pointer Segment Address of Channel 5 - bit 11
PECSEG5.SRCSEG5_10 10 Source Pointer Segment Address of Channel 5 - bit 10
PECSEG5.SRCSEG5_9 9 Source Pointer Segment Address of Channel 5 - bit 9
PECSEG5.SRCSEG5_8 8 Source Pointer Segment Address of Channel 5 - bit 8
PECSEG5.DSTSEG5_7 7 Destination Pointer Segment Address of Channel 5 - bit 7
PECSEG5.DSTSEG5_6 6 Destination Pointer Segment Address of Channel 5 - bit 6
PECSEG5.DSTSEG5_5 5 Destination Pointer Segment Address of Channel 5 - bit 5
PECSEG5.DSTSEG5_4 4 Destination Pointer Segment Address of Channel 5 - bit 4
PECSEG5.DSTSEG5_3 3 Destination Pointer Segment Address of Channel 5 - bit 3
PECSEG5.DSTSEG5_2 2 Destination Pointer Segment Address of Channel 5 - bit 2
PECSEG5.DSTSEG5_1 1 Destination Pointer Segment Address of Channel 5 - bit 1
PECSEG5.DSTSEG5_0 0 Destination Pointer Segment Address of Channel 5 - bit 0
PECSEG6 0xEC8C PEC Pointer 0 Segment Address Reg.
PECSEG6.SRCSEG6_15 15 Source Pointer Segment Address of Channel 6 - bit 15
PECSEG6.SRCSEG6_14 14 Source Pointer Segment Address of Channel 6 - bit 14
PECSEG6.SRCSEG6_13 13 Source Pointer Segment Address of Channel 6 - bit 13
PECSEG6.SRCSEG6_12 12 Source Pointer Segment Address of Channel 6 - bit 12
PECSEG6.SRCSEG6_11 11 Source Pointer Segment Address of Channel 6 - bit 11
PECSEG6.SRCSEG6_10 10 Source Pointer Segment Address of Channel 6 - bit 10
PECSEG6.SRCSEG6_9 9 Source Pointer Segment Address of Channel 6 - bit 9
PECSEG6.SRCSEG6_8 8 Source Pointer Segment Address of Channel 6 - bit 8
PECSEG6.DSTSEG6_7 7 Destination Pointer Segment Address of Channel 6 - bit 7
PECSEG6.DSTSEG6_6 6 Destination Pointer Segment Address of Channel 6 - bit 6
PECSEG6.DSTSEG6_5 5 Destination Pointer Segment Address of Channel 6 - bit 5
PECSEG6.DSTSEG6_4 4 Destination Pointer Segment Address of Channel 6 - bit 4
PECSEG6.DSTSEG6_3 3 Destination Pointer Segment Address of Channel 6 - bit 3
PECSEG6.DSTSEG6_2 2 Destination Pointer Segment Address of Channel 6 - bit 2
PECSEG6.DSTSEG6_1 1 Destination Pointer Segment Address of Channel 6 - bit 1
PECSEG6.DSTSEG6_0 0 Destination Pointer Segment Address of Channel 6 - bit 0
PECSEG7 0xEC8E PEC Pointer 0 Segment Address Reg.
PECSEG7.SRCSEG7_15 15 Source Pointer Segment Address of Channel 7 - bit 15
PECSEG7.SRCSEG7_14 14 Source Pointer Segment Address of Channel 7 - bit 14
PECSEG7.SRCSEG7_13 13 Source Pointer Segment Address of Channel 7 - bit 13
PECSEG7.SRCSEG7_12 12 Source Pointer Segment Address of Channel 7 - bit 12
PECSEG7.SRCSEG7_11 11 Source Pointer Segment Address of Channel 7 - bit 11
PECSEG7.SRCSEG7_10 10 Source Pointer Segment Address of Channel 7 - bit 10
PECSEG7.SRCSEG7_9 9 Source Pointer Segment Address of Channel 7 - bit 9
PECSEG7.SRCSEG7_8 8 Source Pointer Segment Address of Channel 7 - bit 8
PECSEG7.DSTSEG7_7 7 Destination Pointer Segment Address of Channel 7 - bit 7
PECSEG7.DSTSEG7_6 6 Destination Pointer Segment Address of Channel 7 - bit 6
PECSEG7.DSTSEG7_5 5 Destination Pointer Segment Address of Channel 7 - bit 5
PECSEG7.DSTSEG7_4 4 Destination Pointer Segment Address of Channel 7 - bit 4
PECSEG7.DSTSEG7_3 3 Destination Pointer Segment Address of Channel 7 - bit 3
PECSEG7.DSTSEG7_2 2 Destination Pointer Segment Address of Channel 7 - bit 2
PECSEG7.DSTSEG7_1 1 Destination Pointer Segment Address of Channel 7 - bit 1
PECSEG7.DSTSEG7_0 0 Destination Pointer Segment Address of Channel 7 - bit 0
; EBC Registers
EBCMOD0 0xEE00 LEBC Mode Register 0
EBCMOD0.RDYPOL 15 READY pin Polarity
EBCMOD0.RDYDIS 14 READY pin Disable
EBCMOD0.ALEDIS 13 ALE pin Disable
EBCMOD0.BYTDIS 12 BHE pin Disable
EBCMOD0.WRCFG 11 Configuration for pins WR/WRL, BHE/WRH
EBCMOD0.EBCDIS 10 EBC pins Disable
EBCMOD0.SLAVE 9 SLAVE mode enable
EBCMOD0.ARBEN 8 BUS Arbitration Pins enable
EBCMOD0.CSPEN_7 7 CS Pins Enable - bit 7
EBCMOD0.CSPEN_6 6 CS Pins Enable - bit 6
EBCMOD0.CSPEN_5 5 CS Pins Enable - bit 5
EBCMOD0.CSPEN_4 4 CS Pins Enable - bit 4
EBCMOD0.APEN_3 3 Address Pin Enable - bit 3
EBCMOD0.APEN_2 2 Address Pin Enable - bit 2
EBCMOD0.APEN_1 1 Address Pin Enable - bit 1
EBCMOD0.APEN_0 0 Address Pin Enable - bit 0
TCONCS0 0xEE10 CS0 Timing Configuration Register
TCONCS0.WRPHF0_14 14 Write Phase F - bit 14
TCONCS0.WRPHF0_13 13 Write Phase F - bit 13
TCONCS0.RDPHF0_12 12 Read Phase F - bit 12
TCONCS0.RDPHF0_11 11 Read Phase F - bit 11
TCONCS0.PHE0_10 10 Phase E bit - 10
TCONCS0.PHE0_9 9 Phase E bit - 9
TCONCS0.PHE0_8 8 Phase E bit - 8
TCONCS0.PHE0_7 7 Phase E bit - 7
TCONCS0.PHE0_6 6 Phase E bit - 6
TCONCS0.PHD0 5 Phase D
TCONCS0.PHC0_4 4 Phase C bit - 4
TCONCS0.PHC0_3 3 Phase C bit - 3
TCONCS0.PHB0 2 Phase B
TCONCS0.PHA0_1 1 Phase A bit - 1
TCONCS0.PHA0_0 0 Phase A bit - 0
FCONCS0 0xEE12 CS0 Function Configuration Register
FCONCS0.BTYP0_5 5 External Bus Type Selection bit 5
FCONCS0.BTYP0_4 4 External Bus Type Selection bit 4
FCONCS0.RDYMOD0 2 Ready Mode
FCONCS0.RDYEN0 1 Ready enable
FCONCS0.ENCS0 0 Enable Chip Select
TCONCS1 0xEE18 CS1 Timing Configuration Register
TCONCS1.WRPHF1_14 14 Write Phase F - bit 14
TCONCS1.WRPHF1_13 13 Write Phase F - bit 13
TCONCS1.RDPHF1_12 12 Read Phase F - bit 12
TCONCS1.RDPHF1_11 11 Read Phase F - bit 11
TCONCS1.PHE1_10 10 Phase E - bit 10
TCONCS1.PHE1_9 9 Phase E - bit 9
TCONCS1.PHE1_8 8 Phase E - bit 8
TCONCS1.PHE1_7 7 Phase E - bit 7
TCONCS1.PHE1_6 6 Phase E - bit 6
TCONCS1.PHD1 5 Phase D
TCONCS1.PHC1_4 4 Phase C - bit 4
TCONCS1.PHC1_3 3 Phase C - bit 3
TCONCS1.PHB1 2 Phase B
TCONCS1.PHA1_1 1 Phase A - bit 1
TCONCS1.PHA1_0 0 Phase A - bit 0
FCONCS1 0xEE1A CS1 Function Configuration Register
FCONCS1.BTYP1_5 5 External Bus Type Selection bit 5
FCONCS1.BTYP1_4 4 External Bus Type Selection bit 4
FCONCS1.RDYMOD1 2 Ready Mode
FCONCS1.RDYEN1 1 Ready enable
FCONCS1.ENCS1 0 Enable Chip Select
ADDRSEL1 0xEE1E CS1 Address Size and Range Register
ADDRSEL1.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL1.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL1.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL1.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL1.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL1.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL1.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL1.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL1.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL1.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL1.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL1.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL1.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL1.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL1.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL1.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS2 0xEE20 CS2 Timing Configuration Register
TCONCS2.WRPHF2_14 14 Write Phase F - bit 14
TCONCS2.WRPHF2_13 13 Write Phase F - bit 13
TCONCS2.RDPHF2_12 12 Read Phase F - bit 12
TCONCS2.RDPHF2_11 11 Read Phase F - bit 11
TCONCS2.PHE2_10 10 Phase E - bit 10
TCONCS2.PHE2_9 9 Phase E - bit 9
TCONCS2.PHE2_8 8 Phase E - bit 8
TCONCS2.PHE2_7 7 Phase E - bit 7
TCONCS2.PHE2_6 6 Phase E - bit 6
TCONCS2.PHD2 5 Phase D
TCONCS2.PHC2_4 4 Phase C - bit 4
TCONCS2.PHC2_3 3 Phase C - bit 3
TCONCS2.PHB2 2 Phase B
TCONCS2.PHA2_1 1 Phase A - bit 1
TCONCS2.PHA2_0 0 Phase A - bit 0
FCONCS2 0xEE22 CS2 Function Configuration Register
FCONCS2.BTYP2_5 5 External Bus Type Selection - bit 5
FCONCS2.BTYP2_4 4 External Bus Type Selection - bit 4
FCONCS2.RDYMOD2 2 Ready Mode
FCONCS2.RDYEN2 1 Ready enable
FCONCS2.ENCS2 0 Enable Chip Select
ADDRSEL2 0xEE26 CS2 Address Size and Range Register
ADDRSEL2.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL2.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL2.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL2.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL2.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL2.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL2.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL2.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL2.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL2.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL2.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL2.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL2.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL2.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL2.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL2.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS3 0xEE28 CS3 Timing Configuration Register
TCONCS3.WRPHF3_14 14 Write Phase F - bit 14
TCONCS3.WRPHF3_13 13 Write Phase F - bit 13
TCONCS3.RDPHF3_12 12 Read Phase F - bit 12
TCONCS3.RDPHF3_11 11 Read Phase F - bit 11
TCONCS3.PHE3_10 10 Phase E - bit 10
TCONCS3.PHE3_9 9 Phase E - bit 9
TCONCS3.PHE3_8 8 Phase E - bit 8
TCONCS3.PHE3_7 7 Phase E - bit 7
TCONCS3.PHE3_6 6 Phase E - bit 6
TCONCS3.PHD3 5 Phase D
TCONCS3.PHC3_4 4 Phase C - bit 4
TCONCS3.PHC3_3 3 Phase C - bit 3
TCONCS3.PHB3 2 Phase B
TCONCS3.PHA3_1 1 Phase A - bit 1
TCONCS3.PHA3_0 0 Phase A - bit 0
FCONCS3 0xEE2A CS3 Function Configuration Register
FCONCS3.BTYP3_5 5 External Bus Type Selection - bit 5
FCONCS3.BTYP3_4 4 External Bus Type Selection - bit 4
FCONCS3.RDYMOD3 2 Ready Mode
FCONCS3.RDYEN3 1 Ready enable
FCONCS3.ENCS3 0 Enable Chip Select
ADDRSEL3 0xEE2E CS3 Address Size and Range Register
ADDRSEL3.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL3.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL3.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL3.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL3.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL3.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL3.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL3.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL3.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL3.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL3.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL3.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL3.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL3.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL3.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL3.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS4 0xEE30 CS4 Timing Configuration Register
TCONCS4.WRPHF4_14 14 Write Phase F - bit 14
TCONCS4.WRPHF4_13 13 Write Phase F - bit 13
TCONCS4.RDPHF4_12 12 Read Phase F - bit 12
TCONCS4.RDPHF4_11 11 Read Phase F - bit 11
TCONCS4.PHE4_10 10 Phase E - bit 10
TCONCS4.PHE4_9 9 Phase E - bit 9
TCONCS4.PHE4_8 8 Phase E - bit 8
TCONCS4.PHE4_7 7 Phase E - bit 7
TCONCS4.PHE4_6 6 Phase E - bit 6
TCONCS4.PHD4 5 Phase D
TCONCS4.PHC4_4 4 Phase C - bit 4
TCONCS4.PHC4_3 3 Phase C - bit 3
TCONCS4.PHB4 2 Phase B
TCONCS4.PHA4_1 1 Phase A - bit 1
TCONCS4.PHA4_0 0 Phase A - bit 0
FCONCS4 0xEE32 CS4 Function Configuration Register
FCONCS4.BTYP4_5 5 External Bus Type Selection - bit 5
FCONCS4.BTYP4_4 4 External Bus Type Selection - bit 4
FCONCS4.RDYMOD4 2 Ready Mode
FCONCS4.RDYEN4 1 Ready enable
FCONCS4.ENCS4 0 Enable Chip Select
ADDRSEL4 0xEE36 CS4 Address Size and Range Register
ADDRSEL4.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL4.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL4.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL4.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL4.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL4.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL4.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL4.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL4.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL4.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL4.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL4.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL4.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL4.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL4.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL4.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS5 0xEE38 CS5 Timing Configuration Register
TCONCS5.WRPHF5_14 14 Write Phase F - bit 14
TCONCS5.WRPHF5_13 13 Write Phase F - bit 13
TCONCS5.RDPHF5_12 12 Read Phase F - bit 12
TCONCS5.RDPHF5_11 11 Read Phase F - bit 11
TCONCS5.PHE5_10 10 Phase E - bit 10
TCONCS5.PHE5_9 9 Phase E - bit 9
TCONCS5.PHE5_8 8 Phase E - bit 8
TCONCS5.PHE5_7 7 Phase E - bit 7
TCONCS5.PHE5_6 6 Phase E - bit 6
TCONCS5.PHD5 5 Phase D
TCONCS5.PHC5_4 4 Phase C - bit 4
TCONCS5.PHC5_3 3 Phase C - bit 3
TCONCS5.PHB5 2 Phase B
TCONCS5.PHA5_1 1 Phase A - bit 1
TCONCS5.PHA5_0 0 Phase A - bit 0
FCONCS5 0xEE3A CS5 Function Configuration Register
FCONCS5.BTYP5_5 5 External Bus Type Selection - bit 5
FCONCS5.BTYP5_4 4 External Bus Type Selection - bit 4
FCONCS5.RDYMOD5 2 Ready Mode
FCONCS5.RDYEN5 1 Ready enable
FCONCS5.ENCS5 0 Enable Chip Select
ADDRSEL5 0xEE3E CS5 Address Size and Range Register
ADDRSEL5.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL5.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL5.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL5.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL5.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL5.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL5.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL5.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL5.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL5.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL5.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL5.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL5.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL5.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL5.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL5.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS6 0xEE40 CS6 Timing Configuration Register
TCONCS6.WRPHF6_14 14 Write Phase F - bit 14
TCONCS6.WRPHF6_13 13 Write Phase F - bit 13
TCONCS6.RDPHF6_12 12 Read Phase F - bit 12
TCONCS6.RDPHF6_11 11 Read Phase F - bit 11
TCONCS6.PHE6_10 10 Phase E - bit 10
TCONCS6.PHE6_9 9 Phase E - bit 9
TCONCS6.PHE6_8 8 Phase E - bit 8
TCONCS6.PHE6_7 7 Phase E - bit 7
TCONCS6.PHE6_6 6 Phase E - bit 6
TCONCS6.PHD6 5 Phase D
TCONCS6.PHC6_4 4 Phase C - bit 4
TCONCS6.PHC6_3 3 Phase C - bit 3
TCONCS6.PHB6 2 Phase B
TCONCS6.PHA6_1 1 Phase A - bit 1
TCONCS6.PHA6_0 0 Phase A - bit 0
FCONCS6 0xEE42 CS6 Function Configuration Register
FCONCS6.BTYP6_5 5 External Bus Type Selection - bit 5
FCONCS6.BTYP6_4 4 External Bus Type Selection - bit 4
FCONCS6.RDYMOD6 2 Ready Mode
FCONCS6.RDYEN6 1 Ready enable
FCONCS6.ENCS6 0 Enable Chip Select
ADDRSEL6 0xEE46 CS6 Address Size and Range Register
ADDRSEL6.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL6.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL6.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL6.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL6.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL6.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL6.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL6.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL6.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL6.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL6.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL6.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL6.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL6.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL6.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL6.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS7 0xEE48 CS7 Timing Configuration Register
TCONCS7.WRPHF7_14 14 Write Phase F - bit 14
TCONCS7.WRPHF7_13 13 Write Phase F - bit 13
TCONCS7.RDPHF7_12 12 Read Phase F - bit 12
TCONCS7.RDPHF7_11 11 Read Phase F - bit 11
TCONCS7.PHE7_10 10 Phase E - bit 10
TCONCS7.PHE7_9 9 Phase E - bit 9
TCONCS7.PHE7_8 8 Phase E - bit 8
TCONCS7.PHE7_7 7 Phase E - bit 7
TCONCS7.PHE7_6 6 Phase E - bit 6
TCONCS7.PHD7 5 Phase D
TCONCS7.PHC7_4 4 Phase C - bit 4
TCONCS7.PHC7_3 3 Phase C - bit 3
TCONCS7.PHB7 2 Phase B
TCONCS7.PHA7_1 1 Phase A - bit 1
TCONCS7.PHA7_0 0 Phase A - bit 0
FCONCS7 0xEE4A CS7 Function Configuration Register
FCONCS7.BTYP7_5 5 External Bus Type Selection - bit 5
FCONCS7.BTYP7_4 4 External Bus Type Selection - bit 4
FCONCS7.RDYMOD7 2 Ready Mode
FCONCS7.RDYEN7 1 Ready enable
FCONCS7.ENCS7 0 Enable Chip Select
ADDRSEL7 0xEE4E CS7 Address Size and Range Register
ADDRSEL7.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL7.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL7.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL7.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL7.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL7.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL7.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL7.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL7.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL7.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL7.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL7.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL7.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL7.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL7.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL7.RGSZ_0 0 Address Range Size Selection - bit 0
; SFR/ESFR Registers
QX0 0xF000 MAC Unit Offset Register
QX0.QX_15 15 Modifiable portion of register QX0 - bit 15
QX0.QX_14 14 Modifiable portion of register QX0 - bit 14
QX0.QX_13 13 Modifiable portion of register QX0 - bit 13
QX0.QX_12 12 Modifiable portion of register QX0 - bit 12
QX0.QX_11 11 Modifiable portion of register QX0 - bit 11
QX0.QX_10 10 Modifiable portion of register QX0 - bit 10
QX0.QX_9 9 Modifiable portion of register QX0 - bit 9
QX0.QX_8 8 Modifiable portion of register QX0 - bit 8
QX0.QX_7 7 Modifiable portion of register QX0 - bit 7
QX0.QX_6 6 Modifiable portion of register QX0 - bit 6
QX0.QX_5 5 Modifiable portion of register QX0 - bit 5
QX0.QX_4 4 Modifiable portion of register QX0 - bit 4
QX0.QX_3 3 Modifiable portion of register QX0 - bit 3
QX0.QX_2 2 Modifiable portion of register QX0 - bit 2
QX0.QX_1 1 Modifiable portion of register QX0 - bit 1
QX1 0xF002 MAC Unit Offset Register
QX1.QX_15 15 Modifiable portion of register QX1 - bit 15
QX1.QX_14 14 Modifiable portion of register QX1 - bit 14
QX1.QX_13 13 Modifiable portion of register QX1 - bit 13
QX1.QX_12 12 Modifiable portion of register QX1 - bit 12
QX1.QX_11 11 Modifiable portion of register QX1 - bit 11
QX1.QX_10 10 Modifiable portion of register QX1 - bit 10
QX1.QX_9 9 Modifiable portion of register QX1 - bit 9
QX1.QX_8 8 Modifiable portion of register QX1 - bit 8
QX1.QX_7 7 Modifiable portion of register QX1 - bit 7
QX1.QX_6 6 Modifiable portion of register QX1 - bit 6
QX1.QX_5 5 Modifiable portion of register QX1 - bit 5
QX1.QX_4 4 Modifiable portion of register QX1 - bit 4
QX1.QX_3 3 Modifiable portion of register QX1 - bit 3
QX1.QX_2 2 Modifiable portion of register QX1 - bit 2
QX1.QX_1 1 Modifiable portion of register QX1 - bit 1
QR0 0xF004 MAC Unit Offset Register
QR0.QR0_15 15 Modifiable portion of register QR0 - bit 15
QR0.QR0_14 14 Modifiable portion of register QR0 - bit 14
QR0.QR0_13 13 Modifiable portion of register QR0 - bit 13
QR0.QR0_12 12 Modifiable portion of register QR0 - bit 12
QR0.QR0_11 11 Modifiable portion of register QR0 - bit 11
QR0.QR0_10 10 Modifiable portion of register QR0 - bit 10
QR0.QR0_9 9 Modifiable portion of register QR0 - bit 9
QR0.QR0_8 8 Modifiable portion of register QR0 - bit 8
QR0.QR0_7 7 Modifiable portion of register QR0 - bit 7
QR0.QR0_6 6 Modifiable portion of register QR0 - bit 6
QR0.QR0_5 5 Modifiable portion of register QR0 - bit 5
QR0.QR0_4 4 Modifiable portion of register QR0 - bit 4
QR0.QR0_3 3 Modifiable portion of register QR0 - bit 3
QR0.QR0_2 2 Modifiable portion of register QR0 - bit 2
QR0.QR0_1 1 Modifiable portion of register QR0 - bit 1
QR1 0xF006 MAC Unit Offset Register
QR1.QR1_15 15 Modifiable portion of register QR1 - bit 15
QR1.QR1_14 14 Modifiable portion of register QR1 - bit 14
QR1.QR1_13 13 Modifiable portion of register QR1 - bit 13
QR1.QR1_12 12 Modifiable portion of register QR1 - bit 12
QR1.QR1_11 11 Modifiable portion of register QR1 - bit 11
QR1.QR1_10 10 Modifiable portion of register QR1 - bit 10
QR1.QR1_9 9 Modifiable portion of register QR1 - bit 9
QR1.QR1_8 8 Modifiable portion of register QR1 - bit 8
QR1.QR1_7 7 Modifiable portion of register QR1 - bit 7
QR1.QR1_6 6 Modifiable portion of register QR1 - bit 6
QR1.QR1_5 5 Modifiable portion of register QR1 - bit 5
QR1.QR1_4 4 Modifiable portion of register QR1 - bit 4
QR1.QR1_3 3 Modifiable portion of register QR1 - bit 3
QR1.QR1_2 2 Modifiable portion of register QR1 - bit 2
QR1.QR1_1 1 Modifiable portion of register QR1 - bit 1
PT0 0xF030 PWM Module Up/Down Counter 0
PT1 0xF032 PWM Module Up/Down Counter 1
PP0 0xF038 PWM Module Period Register 0
PP1 0xF03A PWM Module Period Register 1
IDCHIP 0xF07C Identifier Chip (n is the device revision)
IDCHIP.IDCHIP_15 15 Device Identifier - bit 15 (206h: Super10 - M340/M341 Megacell)
IDCHIP.IDCHIP_14 14 Device Identifier - bit 14
IDCHIP.IDCHIP_13 13 Device Identifier - bit 13
IDCHIP.IDCHIP_12 12 Device Identifier - bit 12
IDCHIP.IDCHIP_11 11 Device Identifier - bit 11
IDCHIP.IDCHIP_10 10 Device Identifier - bit 10
IDCHIP.IDCHIP_9 9 Device Identifier - bit 9
IDCHIP.IDCHIP_8 8 Device Identifier - bit 8
IDCHIP.IDCHIP_7 7 Device Identifier - bit 7
IDCHIP.IDCHIP_6 6 Device Identifier - bit 6
IDCHIP.IDCHIP_5 5 Device Identifier - bit 5
IDCHIP.IDCHIP_4 4 Device Identifier - bit 4
IDCHIP.REVID_3 3 Device Revision Identifier - bit 3 (nh: According to revision number)
IDCHIP.REVID_2 2 Device Revision Identifier - bit 2
IDCHIP.REVID_1 1 Device Revision Identifier - bit 1
IDCHIP.REVID_0 0 Device Revision Identifier - bit 0
IDMANUF 0xF07E Identifier Manufacturer (0414h: STMicroelectronics manufacturer)
IDMANUF.MANUF_15 15 Manufacturer Identifier - bit 15
IDMANUF.MANUF_14 14 Manufacturer Identifier - bit 14
IDMANUF.MANUF_13 13 Manufacturer Identifier - bit 13
IDMANUF.MANUF_12 12 Manufacturer Identifier - bit 12
IDMANUF.MANUF_11 11 Manufacturer Identifier - bit 11
IDMANUF.MANUF_10 10 Manufacturer Identifier - bit 10
IDMANUF.MANUF_9 9 Manufacturer Identifier - bit 9
IDMANUF.MANUF_8 8 Manufacturer Identifier - bit 8
IDMANUF.MANUF_7 7 Manufacturer Identifier - bit 7
IDMANUF.MANUF_6 6 Manufacturer Identifier - bit 6
IDMANUF.MANUF_5 5 Manufacturer Identifier - bit 5
IDMANUF.MANUF_4 4 Manufacturer Identifier - bit 4
IDMANUF.MANUF_3 3 Manufacturer Identifier - bit 3
IDMANUF.MANUF_2 2 Manufacturer Identifier - bit 2
IDMANUF.MANUF_1 1 Manufacturer Identifier - bit 1
IDMANUF.MANUF_0 0 Manufacturer Identifier - bit 0
SSCTB 0xF0B0 SSC0 Transmit Buffer (WO)
SSCRB 0xF0B2 SSC0 Receive Buffer (RO)
SSCBR 0xF0B4 SSC0 Baud Rate Register
SCUSLC 0xF0C0 Security Level Control Register
SCUSLS 0xF0C2 Security Level Status Register
SCUSLS.STATE_15 15 Security State Indication - bit 15
SCUSLS.STATE_14 14 Security State Indication - bit 14
SCUSLS.STATE_13 13 Security State Indication - bit 13
SCUSLS.SL_12 12 Security Level Indication - bit 12
SCUSLS.SL_11 11 Security Level Indication - bit 11
SCUSLS.PASSWORD_7 7 Security Password Indication - bit 7
SCUSLS.PASSWORD_6 6 Security Password Indication - bit 6
SCUSLS.PASSWORD_5 5 Security Password Indication - bit 5
SCUSLS.PASSWORD_4 4 Security Password Indication - bit 4
SCUSLS.PASSWORD_3 3 Security Password Indication - bit 3
SCUSLS.PASSWORD_2 2 Security Password Indication - bit 2
SCUSLS.PASSWORD_1 1 Security Password Indication - bit 1
SCUSLS.PASSWORD_0 0 Security Password Indication - bit 0
RSTCFG 0xF108 System Startup Configuration Register
RSTCFG.CLKCFG_15 15 Clock Generation Mode Configuration - bit 15
RSTCFG.CLKCFG_14 14 Clock Generation Mode Configuration - bit 14
RSTCFG.CLKCFG_13 13 Clock Generation Mode Configuration - bit 13
RSTCFG.CLKCFG_12 12 Clock Generation Mode Configuration - bit 12
RSTCFG.CLKCFG_11 11 Clock Generation Mode Configuration - bit 11
RSTCFG.BUSTYP_7 7 External Bus Type - bit 7
RSTCFG.BUSTYP_6 6 External Bus Type - bit 6
RSTCFG.SALSEL_5 5 Segment Select Line Selection - bit 5
RSTCFG.SALSEL_4 4 Segment Select Line Selection - bit 4
RSTCFG.WRC 3 Write Configuration
RSTCFG.BSL 2 Bootstrap Loader Mode
RSTCFG.ADP 1 Adapt Mode
RES0IC 0xF160 Reserved Interrupt 0 Control Register
RES0IC.RES0ICIR 7 Interrupt Request Flag
RES0IC.RES0ICIE 6 Interrupt Enable Control Bit
RES0IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES0IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES0IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES0IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES0IC.GLVL_1 1 Group Priority Level - bit 1
RES0IC.GLVL_0 0 Group Priority Level - bit 0
RES1IC 0xF162 Reserved Interrupt 1 Control Register
RES1IC.RES1ICIR 7 Interrupt Request Flag
RES1IC.RES1ICIE 6 Interrupt Enable Control Bit
RES1IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES1IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES1IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES1IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES1IC.GLVL_1 1 Group Priority Level - bit 1
RES1IC.GLVL_0 0 Group Priority Level - bit 0
RES2IC 0xF164 Reserved Interrupt 2 Control Register
RES2IC.RES2ICIR 7 Interrupt Request Flag
RES2IC.RES2ICIE 6 Interrupt Enable Control Bit
RES2IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES2IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES2IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES2IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES2IC.GLVL_1 1 Group Priority Level - bit 1
RES2IC.GLVL_0 0 Group Priority Level - bit 0
RES3IC 0xF166 Reserved Interrupt 3 Control Register
RES3IC.RES3ICIR 7 Interrupt Request Flag
RES3IC.RES3ICIE 6 Interrupt Enable Control Bit
RES3IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES3IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES3IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES3IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES3IC.GLVL_1 1 Group Priority Level - bit 1
RES3IC.GLVL_0 0 Group Priority Level - bit 0
RES4IC 0xF168 Reserved Interrupt 4 Control Register
RES4IC.RES4ICIR 7 Interrupt Request Flag
RES4IC.RES4ICIE 6 Interrupt Enable Control Bit
RES4IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES4IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES4IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES4IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES4IC.GLVL_1 1 Group Priority Level - bit 1
RES4IC.GLVL_0 0 Group Priority Level - bit 0
RES5IC 0xF16A Reserved Interrupt 5 Control Register
RES5IC.RES5ICIR 7 Interrupt Request Flag
RES5IC.RES5ICIE 6 Interrupt Enable Control Bit
RES5IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES5IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES5IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES5IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES5IC.GLVL_1 1 Group Priority Level - bit 1
RES5IC.GLVL_0 0 Group Priority Level - bit 0
RES6IC 0xF16C Reserved Interrupt 6 Control Register
RES6IC.RES6ICIR 7 Interrupt Request Flag
RES6IC.RES6ICIE 6 Interrupt Enable Control Bit
RES6IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES6IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES6IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES6IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES6IC.GLVL_1 1 Group Priority Level - bit 1
RES6IC.GLVL_0 0 Group Priority Level - bit 0
PWMIC 0xF17E PWM Module Interrupt Control Register
PWMIC.PWMICIR 7 Interrupt Request Flag
PWMIC.PWMICIE 6 Interrupt Enable Control Bit
PWMIC.ILVL_5 5 Interrupt Priority Level - bit 5
PWMIC.ILVL_4 4 Interrupt Priority Level - bit 4
PWMIC.ILVL_3 3 Interrupt Priority Level - bit 3
PWMIC.ILVL_2 2 Interrupt Priority Level - bit 2
PWMIC.GLVL_1 1 Group Priority Level - bit 1
PWMIC.GLVL_0 0 Group Priority Level - bit 0
EOPIC 0xF180 End of PEC
EOPIC.EOPIR 7 Interrupt Request Flag
EOPIC.EOPIE 6 Interrupt Enable Control Bit
EOPIC.ILVL_5 5 Interrupt Priority Level - bit 5
EOPIC.ILVL_4 4 Interrupt Priority Level - bit 4
EOPIC.ILVL_3 3 Interrupt Priority Level - bit 3
EOPIC.ILVL_2 2 Interrupt Priority Level - bit 2
EOPIC.GLVL_1 1 Group Priority Level - bit 1
EOPIC.GLVL_0 0 Group Priority Level - bit 0
S0TBIC 0xF19C Serial Channel 0 Transmit Buffer IC Register
PLLIC 0xF19E PLL Interrupt Control Register
PLLIC.PLLICIR 7 Interrupt Request Flag
PLLIC.PLLICIE 6 Interrupt Enable Control Bit
PLLIC.ILVL_5 5 Interrupt Priority Level - bit 5
PLLIC.ILVL_4 4 Interrupt Priority Level - bit 4
PLLIC.ILVL_3 3 Interrupt Priority Level - bit 3
PLLIC.ILVL_2 2 Interrupt Priority Level - bit 2
PLLIC.GLVL_1 1 Group Priority Level - bit 1
PLLIC.GLVL_0 0 Group Priority Level - bit 0
RES7IC 0xF1B0 Reserved Interrupt 7 Control Register
RES7IC.RES7ICIR 7 Interrupt Request Flag
RES7IC.RES7ICIE 6 Interrupt Enable Control Bit
RES7IC.ILVL_5 5 Interrupt Priority Level - bit 5
RES7IC.ILVL_4 4 Interrupt Priority Level - bit 4
RES7IC.ILVL_3 3 Interrupt Priority Level - bit 3
RES7IC.ILVL_2 2 Interrupt Priority Level - bit 2
RES7IC.GLVL_1 1 Group Priority Level - bit 1
RES7IC.GLVL_0 0 Group Priority Level - bit 0
EXICON 0xF1C0 External Interrupt Signal Control Register
EXICON.EXI7ES_15 15 External Interrupt 7 Edge Selection Field - bit 15
EXICON.EXI7ES_14 14 External Interrupt 7 Edge Selection Field - bit 14
EXICON.EXI6ES_13 13 External Interrupt 6 Edge Selection Field - bit 13
EXICON.EXI6ES_12 12 External Interrupt 6 Edge Selection Field - bit 12
EXICON.EXI5ES_11 11 External Interrupt 5 Edge Selection Field - bit 11
EXICON.EXI5ES_10 10 External Interrupt 5 Edge Selection Field - bit 10
EXICON.EXI4ES_9 9 External Interrupt 4 Edge Selection Field - bit 9
EXICON.EXI4ES_8 8 External Interrupt 4 Edge Selection Field - bit 8
EXICON.EXI3ES_7 7 External Interrupt 3 Edge Selection Field - bit 7
EXICON.EXI3ES_6 6 External Interrupt 3 Edge Selection Field - bit 6
EXICON.EXI2ES_5 5 External Interrupt 2 Edge Selection Field - bit 5
EXICON.EXI2ES_4 4 External Interrupt 2 Edge Selection Field - bit 4
EXICON.EXI1ES_3 3 External Interrupt 1 Edge Selection Field - bit 3
EXICON.EXI1ES_2 2 External Interrupt 1 Edge Selection Field - bit 2
EXICON.EXI0ES_1 1 External Interrupt 0 Edge Selection Field - bit 1
EXICON.EXI0ES_0 0 External Interrupt 0 Edge Selection Field - bit 0
ODP2 0xF1C2 Port 2 Open Drain Control Register
ODP3 0xF1C6 Port 3 Open Drain Control Register
SYSCON2 0xF1D0 System Configuration Register 2/Clock Control
SYSCON2.CLKLOCK 15 Clock Status Flag
SYSCON2.DRVOFF 4 Port output driver off control (in sleep and power down mode)
SYSCON3 0xF1D4 System Configuration Register 3 (Peripheral Management)
SYSCON3.PWMDIS 9 PWMx disable control
SYSCON3.GPTDIS 3 GPTx disable control
SYSCON3.SSC0DIS 2 SSCx disable control
SYSCON3.ASC0DIS 1 ASCx disable control
EXISEL 0xF1DA External Interrupt Input Select Register
EXISEL.EXI7SS_15 15 External Interrupt Source Selection Field - bit 15
EXISEL.EXI7SS_14 14 External Interrupt Source Selection Field - bit 14
EXISEL.EXI6SS_13 13 External Interrupt Source Selection Field - bit 13
EXISEL.EXI6SS_12 12 External Interrupt Source Selection Field - bit 12
EXISEL.EXI5SS_11 11 External Interrupt Source Selection Field - bit 11
EXISEL.EXI5SS_10 10 External Interrupt Source Selection Field - bit 10
EXISEL.EXI4SS_9 9 External Interrupt Source Selection Field - bit 9
EXISEL.EXI4SS_8 8 External Interrupt Source Selection Field - bit 8
EXISEL.EXI3SS_7 7 External Interrupt Source Selection Field - bit 7
EXISEL.EXI3SS_6 6 External Interrupt Source Selection Field - bit 6
EXISEL.EXI2SS_5 5 External Interrupt Source Selection Field - bit 5
EXISEL.EXI2SS_4 4 External Interrupt Source Selection Field - bit 4
EXISEL.EXI1SS_3 3 External Interrupt Source Selection Field - bit 3
EXISEL.EXI1SS_2 2 External Interrupt Source Selection Field - bit 2
EXISEL.EXI0SS_1 1 External Interrupt Source Selection Field - bit 1
EXISEL.EXI0SS_0 0 External Interrupt Source Selection Field - bit 0
SYSCON1 0xF1DC System Configuration Register 1/Sleep Mode
SYSCON1.BCLKCON_11 11 Bus Clock Control - bit 11
SYSCON1.BCLKCON_10 10 Bus Clock Control - bit 10
SYSCON1.BCLKCON_9 9 Bus Clock Control - bit 9
SYSCON1.BCLKCON_8 8 Bus Clock Control - bit 8
SYSCON1.SLEEPCON_1 1 SLEEP Mode Configuration - bit 1
SYSCON1.SLEEPCON_0 0 SLEEP Mode Configuration - bit 0
RSTCON 0xF1E0 Reset Control Register
RSTCON.RSTOUT2_DIS 7 RSTOUT2 Disable Control
RSTCON.RSTLEN_2 2 Reset Length Control - bit 2
RSTCON.RSTLEN_1 1 Reset Length Control - bit 1
RSTCON.RSTLEN_0 0 Reset Length Control - bit 0
SYSSTAT 0xF1E4 System Status Register
SYSSTAT.HWR 2 Hardware Reset Indication Flag
SYSSTAT.SWR 1 Software Reset Indication Flag
SYSSTAT.WDTR 0 Watchdog Timer Reset Indication Flag
DPP0 0xFE00 CPU Data Page Pointer 0 Register
DPP0.PN_9 9 Data Page Number of DPP - bit 9
DPP0.PN_8 8 Data Page Number of DPP - bit 8
DPP0.PN_7 7 Data Page Number of DPP - bit 7
DPP0.PN_6 6 Data Page Number of DPP - bit 6
DPP0.PN_5 5 Data Page Number of DPP - bit 5
DPP0.PN_4 4 Data Page Number of DPP - bit 4
DPP0.PN_3 3 Data Page Number of DPP - bit 3
DPP0.PN_2 2 Data Page Number of DPP - bit 2
DPP0.PN_1 1 Data Page Number of DPP - bit 1
DPP0.PN_0 0 Data Page Number of DPP - bit 0
DPP1 0xFE02 CPU Data Page Pointer 1 Register
DPP1.PN_9 9 Data Page Number of DPP - bit 9
DPP1.PN_8 8 Data Page Number of DPP - bit 8
DPP1.PN_7 7 Data Page Number of DPP - bit 7
DPP1.PN_6 6 Data Page Number of DPP - bit 6
DPP1.PN_5 5 Data Page Number of DPP - bit 5
DPP1.PN_4 4 Data Page Number of DPP - bit 4
DPP1.PN_3 3 Data Page Number of DPP - bit 3
DPP1.PN_2 2 Data Page Number of DPP - bit 2
DPP1.PN_1 1 Data Page Number of DPP - bit 1
DPP1.PN_0 0 Data Page Number of DPP - bit 0
DPP2 0xFE04 CPU Data Page Pointer 2 Register
DPP2.PN_9 9 Data Page Number of DPP - bit 9
DPP2.PN_8 8 Data Page Number of DPP - bit 8
DPP2.PN_7 7 Data Page Number of DPP - bit 7
DPP2.PN_6 6 Data Page Number of DPP - bit 6
DPP2.PN_5 5 Data Page Number of DPP - bit 5
DPP2.PN_4 4 Data Page Number of DPP - bit 4
DPP2.PN_3 3 Data Page Number of DPP - bit 3
DPP2.PN_2 2 Data Page Number of DPP - bit 2
DPP2.PN_1 1 Data Page Number of DPP - bit 1
DPP2.PN_0 0 Data Page Number of DPP - bit 0
DPP3 0xFE06 CPU Data Page Pointer 3 Register
DPP3.PN_9 9 Data Page Number of DPP - bit 9
DPP3.PN_8 8 Data Page Number of DPP - bit 8
DPP3.PN_7 7 Data Page Number of DPP - bit 7
DPP3.PN_6 6 Data Page Number of DPP - bit 6
DPP3.PN_5 5 Data Page Number of DPP - bit 5
DPP3.PN_4 4 Data Page Number of DPP - bit 4
DPP3.PN_3 3 Data Page Number of DPP - bit 3
DPP3.PN_2 2 Data Page Number of DPP - bit 2
DPP3.PN_1 1 Data Page Number of DPP - bit 1
DPP3.PN_0 0 Data Page Number of DPP - bit 0
CSP 0xFE08 CPU Code Segment Pointer Register (8 bits)
CSP.SEGNR_7 7 Specifies the code segment, from where the current instruction is to be fetched - bit 7
CSP.SEGNR_6 6 Specifies the code segment, from where the current instruction is to be fetched - bit 6
CSP.SEGNR_5 5 Specifies the code segment, from where the current instruction is to be fetched - bit 5
CSP.SEGNR_4 4 Specifies the code segment, from where the current instruction is to be fetched - bit 4
CSP.SEGNR_3 3 Specifies the code segment, from where the current instruction is to be fetched - bit 3
CSP.SEGNR_2 2 Specifies the code segment, from where the current instruction is to be fetched - bit 2
CSP.SEGNR_1 1 Specifies the code segment, from where the current instruction is to be fetched - bit 1
CSP.SEGNR_0 0 Specifies the code segment, from where the current instruction is to be fetched - bit 0
MDH 0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH_15 15 High part of MD - bit 15
MDH.MDH_14 14 High part of MD - bit 14
MDH.MDH_13 13 High part of MD - bit 13
MDH.MDH_12 12 High part of MD - bit 12
MDH.MDH_11 11 High part of MD - bit 11
MDH.MDH_10 10 High part of MD - bit 10
MDH.MDH_9 9 High part of MD - bit 9
MDH.MDH_8 8 High part of MD - bit 8
MDH.MDH_7 7 High part of MD - bit 7
MDH.MDH_6 6 High part of MD - bit 6
MDH.MDH_5 5 High part of MD - bit 5
MDH.MDH_4 4 High part of MD - bit 4
MDH.MDH_3 3 High part of MD - bit 3
MDH.MDH_2 2 High part of MD - bit 2
MDH.MDH_1 1 High part of MD - bit 1
MDH.MDH_0 0 High part of MD - bit 0
MDL 0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL_15 15 Low part of MD - bit 15
MDL.MDL_14 14 Low part of MD - bit 14
MDL.MDL_13 13 Low part of MD - bit 13
MDL.MDL_12 12 Low part of MD - bit 12
MDL.MDL_11 11 Low part of MD - bit 11
MDL.MDL_10 10 Low part of MD - bit 10
MDL.MDL_9 9 Low part of MD - bit 9
MDL.MDL_8 8 Low part of MD - bit 8
MDL.MDL_7 7 Low part of MD - bit 7
MDL.MDL_6 6 Low part of MD - bit 6
MDL.MDL_5 5 Low part of MD - bit 5
MDL.MDL_4 4 Low part of MD - bit 4
MDL.MDL_3 3 Low part of MD - bit 3
MDL.MDL_2 2 Low part of MD - bit 2
MDL.MDL_1 1 Low part of MD - bit 1
MDL.MDL_0 0 Low part of MD - bit 0
CP 0xFE10 CPU Context Pointer Register
CP.CONTEXT_POINTER_11 11 Modifiable portion of register CP - bit 11
CP.CONTEXT_POINTER_10 10 Modifiable portion of register CP - bit 10
CP.CONTEXT_POINTER_9 9 Modifiable portion of register CP - bit 9
CP.CONTEXT_POINTER_8 8 Modifiable portion of register CP - bit 8
CP.CONTEXT_POINTER_7 7 Modifiable portion of register CP - bit 7
CP.CONTEXT_POINTER_6 6 Modifiable portion of register CP - bit 6
CP.CONTEXT_POINTER_5 5 Modifiable portion of register CP - bit 5
CP.CONTEXT_POINTER_4 4 Modifiable portion of register CP - bit 4
CP.CONTEXT_POINTER_3 3 Modifiable portion of register CP - bit 3
CP.CONTEXT_POINTER_2 2 Modifiable portion of register CP - bit 2
CP.CONTEXT_POINTER_1 1 Modifiable portion of register CP - bit 1
SP 0xFE12 CPU System Stack Pointer Register
SP.SP_15 15 Modifiable portion of register SP - bit 15
SP.SP_14 14 Modifiable portion of register SP - bit 14
SP.SP_13 13 Modifiable portion of register SP - bit 13
SP.SP_12 12 Modifiable portion of register SP - bit 12
SP.SP_11 11 Modifiable portion of register SP - bit 11
SP.SP_10 10 Modifiable portion of register SP - bit 10
SP.SP_9 9 Modifiable portion of register SP - bit 9
SP.SP_8 8 Modifiable portion of register SP - bit 8
SP.SP_7 7 Modifiable portion of register SP - bit 7
SP.SP_6 6 Modifiable portion of register SP - bit 6
SP.SP_5 5 Modifiable portion of register SP - bit 5
SP.SP_4 4 Modifiable portion of register SP - bit 4
SP.SP_3 3 Modifiable portion of register SP - bit 3
SP.SP_2 2 Modifiable portion of register SP - bit 2
SP.SP_1 1 Modifiable portion of register SP - bit 1
STKOV 0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV_15 15 Modifiable portion of register STKOV - bit 15
STKOV.STKOV_14 14 Modifiable portion of register STKOV - bit 14
STKOV.STKOV_13 13 Modifiable portion of register STKOV - bit 13
STKOV.STKOV_12 12 Modifiable portion of register STKOV - bit 12
STKOV.STKOV_11 11 Modifiable portion of register STKOV - bit 11
STKOV.STKOV_10 10 Modifiable portion of register STKOV - bit 10
STKOV.STKOV_9 9 Modifiable portion of register STKOV - bit 9
STKOV.STKOV_8 8 Modifiable portion of register STKOV - bit 8
STKOV.STKOV_7 7 Modifiable portion of register STKOV - bit 7
STKOV.STKOV_6 6 Modifiable portion of register STKOV - bit 6
STKOV.STKOV_5 5 Modifiable portion of register STKOV - bit 5
STKOV.STKOV_4 4 Modifiable portion of register STKOV - bit 4
STKOV.STKOV_3 3 Modifiable portion of register STKOV - bit 3
STKOV.STKOV_2 2 Modifiable portion of register STKOV - bit 2
STKOV.STKOV_1 1 Modifiable portion of register STKOV - bit 1
STKUN 0xFE16 CPU Stack Underflow Pointer Register
STKUN.SP_15 15 Modifiable portion of register SP - bit 15
STKUN.SP_14 14 Modifiable portion of register SP - bit 14
STKUN.SP_13 13 Modifiable portion of register SP - bit 13
STKUN.SP_12 12 Modifiable portion of register SP - bit 12
STKUN.SP_11 11 Modifiable portion of register SP - bit 11
STKUN.SP_10 10 Modifiable portion of register SP - bit 10
STKUN.SP_9 9 Modifiable portion of register SP - bit 9
STKUN.SP_8 8 Modifiable portion of register SP - bit 8
STKUN.SP_7 7 Modifiable portion of register SP - bit 7
STKUN.SP_6 6 Modifiable portion of register SP - bit 6
STKUN.SP_5 5 Modifiable portion of register SP - bit 5
STKUN.SP_4 4 Modifiable portion of register SP - bit 4
STKUN.SP_3 3 Modifiable portion of register SP - bit 3
STKUN.SP_2 2 Modifiable portion of register SP - bit 2
STKUN.SP_1 1 Modifiable portion of register SP - bit 1
CPUCON1 0xFE18 Core Control Register
CPUCON1.VECSC_6 6
CPUCON1.VECSC_5 5
CPUCON1.WDTCTL 4
CPUCON1.SGTDIS 3 Segmentation Disable/Enable Control
CPUCON1.INTSCXT 2
CPUCON1.BP 1
CPUCON1.ZCJ 0
CPUCON2 0xFE1A Core Control Register
PW0 0xFE30 PWM Module Pulse Width Register 0
PW1 0xFE32 PWM Module Pulse Width Register 1
T2 0xFE40 GPT12E Timer 2 Register
T3 0xFE42 GPT12E Timer 3 Register
T4 0xFE44 GPT12E Timer 4 Register
T5 0xFE46 GPT12E Timer 5 Register
T6 0xFE48 GPT12E Timer 6 Register
CAPREL 0xFE4A GPT12E Capture/Reload Register
MAL 0xFE5C MAC Unit Accumulator Low
MAL.MAL_15 15 Low part of Accumulator - bit 15
MAL.MAL_14 14 Low part of Accumulator - bit 14
MAL.MAL_13 13 Low part of Accumulator - bit 13
MAL.MAL_12 12 Low part of Accumulator - bit 12
MAL.MAL_11 11 Low part of Accumulator - bit 11
MAL.MAL_10 10 Low part of Accumulator - bit 10
MAL.MAL_9 9 Low part of Accumulator - bit 9
MAL.MAL_8 8 Low part of Accumulator - bit 8
MAL.MAL_7 7 Low part of Accumulator - bit 7
MAL.MAL_6 6 Low part of Accumulator - bit 6
MAL.MAL_5 5 Low part of Accumulator - bit 5
MAL.MAL_4 4 Low part of Accumulator - bit 4
MAL.MAL_3 3 Low part of Accumulator - bit 3
MAL.MAL_2 2 Low part of Accumulator - bit 2
MAL.MAL_1 1 Low part of Accumulator - bit 1
MAL.MAL_0 0 Low part of Accumulator - bit 0
MAH 0xFE5E MAC Unit Accumulator High
MAH.MAH_15 15 High part of Accumulator - bit 15
MAH.MAH_14 14 High part of Accumulator - bit 14
MAH.MAH_13 13 High part of Accumulator - bit 13
MAH.MAH_12 12 High part of Accumulator - bit 12
MAH.MAH_11 11 High part of Accumulator - bit 11
MAH.MAH_10 10 High part of Accumulator - bit 10
MAH.MAH_9 9 High part of Accumulator - bit 9
MAH.MAH_8 8 High part of Accumulator - bit 8
MAH.MAH_7 7 High part of Accumulator - bit 7
MAH.MAH_6 6 High part of Accumulator - bit 6
MAH.MAH_5 5 High part of Accumulator - bit 5
MAH.MAH_4 4 High part of Accumulator - bit 4
MAH.MAH_3 3 High part of Accumulator - bit 3
MAH.MAH_2 2 High part of Accumulator - bit 2
MAH.MAH_1 1 High part of Accumulator - bit 1
MAH.MAH_0 0 High part of Accumulator - bit 0
WDT 0xFEAE Watchdog Timer Register (RO)
WDT.WDT_15 15 Watchdog Timer - bit 15
WDT.WDT_14 14 Watchdog Timer - bit 14
WDT.WDT_13 13 Watchdog Timer - bit 13
WDT.WDT_12 12 Watchdog Timer - bit 12
WDT.WDT_11 11 Watchdog Timer - bit 11
WDT.WDT_10 10 Watchdog Timer - bit 10
WDT.WDT_9 9 Watchdog Timer - bit 9
WDT.WDT_8 8 Watchdog Timer - bit 8
WDT.WDT_7 7 Watchdog Timer - bit 7
WDT.WDT_6 6 Watchdog Timer - bit 6
WDT.WDT_5 5 Watchdog Timer - bit 5
WDT.WDT_4 4 Watchdog Timer - bit 4
WDT.WDT_3 3 Watchdog Timer - bit 3
WDT.WDT_2 2 Watchdog Timer - bit 2
WDT.WDT_1 1 Watchdog Timer - bit 1
WDT.WDT_0 0 Watchdog Timer - bit 0
S0TBUF 0xFEB0 Serial Channel 0 Transmit Buffer Register (WO)
S0RBUF 0xFEB2 Serial Channel 0 Receive Buffer Register (RO)
S0BG 0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
S0FDV 0xFEB6 Serial Channel 0 Fractional Divider Register
PECC0 0xFEC0 PEC Channel 0 Control Register
PECC0.EOPINT 14 End of PEC Interrupt Selection
PECC0.PLEV_13 13 PEC Level Selection - bit 13
PECC0.PLEV_12 12 PEC Level Selection - bit 12
PECC0.INC_10 10 Increment Control - bit 10
PECC0.INC_9 9 Increment Control - bit 9
PECC0.BWT 8 Byte / Word Transfer Selection
PECC0.COUNT_7 7 PEC Transfer Count - bit 7
PECC0.COUNT_6 6 PEC Transfer Count - bit 6
PECC0.COUNT_5 5 PEC Transfer Count - bit 5
PECC0.COUNT_4 4 PEC Transfer Count - bit 4
PECC0.COUNT_3 3 PEC Transfer Count - bit 3
PECC0.COUNT_2 2 PEC Transfer Count - bit 2
PECC0.COUNT_1 1 PEC Transfer Count - bit 1
PECC0.COUNT_0 0 PEC Transfer Count - bit 0
PECC1 0xFEC2 PEC Channel 1 Control Register
PECC1.EOPINT 14 End of PEC Interrupt Selection
PECC1.PLEV_13 13 PEC Level Selection - bit 13
PECC1.PLEV_12 12 PEC Level Selection - bit 12
PECC1.INC_10 10 Increment Control - bit 10
PECC1.INC_9 9 Increment Control - bit 9
PECC1.BWT 8 Byte / Word Transfer Selection
PECC1.COUNT_7 7 PEC Transfer Count - bit 7
PECC1.COUNT_6 6 PEC Transfer Count - bit 6
PECC1.COUNT_5 5 PEC Transfer Count - bit 5
PECC1.COUNT_4 4 PEC Transfer Count - bit 4
PECC1.COUNT_3 3 PEC Transfer Count - bit 3
PECC1.COUNT_2 2 PEC Transfer Count - bit 2
PECC1.COUNT_1 1 PEC Transfer Count - bit 1
PECC1.COUNT_0 0 PEC Transfer Count - bit 0
PECC2 0xFEC4 PEC Channel 2 Control Register
PECC2.EOPINT 14 End of PEC Interrupt Selection
PECC2.PLEV_13 13 PEC Level Selection - bit 13
PECC2.PLEV_12 12 PEC Level Selection - bit 12
PECC2.INC_10 10 Increment Control - bit 10
PECC2.INC_9 9 Increment Control - bit 9
PECC2.BWT 8 Byte / Word Transfer Selection
PECC2.COUNT_7 7 PEC Transfer Count - bit 7
PECC2.COUNT_6 6 PEC Transfer Count - bit 6
PECC2.COUNT_5 5 PEC Transfer Count - bit 5
PECC2.COUNT_4 4 PEC Transfer Count - bit 4
PECC2.COUNT_3 3 PEC Transfer Count - bit 3
PECC2.COUNT_2 2 PEC Transfer Count - bit 2
PECC2.COUNT_1 1 PEC Transfer Count - bit 1
PECC2.COUNT_0 0 PEC Transfer Count - bit 0
PECC3 0xFEC6 PEC Channel 3 Control Register
PECC3.EOPINT 14 End of PEC Interrupt Selection
PECC3.PLEV_13 13 PEC Level Selection - bit 13
PECC3.PLEV_12 12 PEC Level Selection - bit 12
PECC3.INC_10 10 Increment Control - bit 10
PECC3.INC_9 9 Increment Control - bit 9
PECC3.BWT 8 Byte / Word Transfer Selection
PECC3.COUNT_7 7 PEC Transfer Count - bit 7
PECC3.COUNT_6 6 PEC Transfer Count - bit 6
PECC3.COUNT_5 5 PEC Transfer Count - bit 5
PECC3.COUNT_4 4 PEC Transfer Count - bit 4
PECC3.COUNT_3 3 PEC Transfer Count - bit 3
PECC3.COUNT_2 2 PEC Transfer Count - bit 2
PECC3.COUNT_1 1 PEC Transfer Count - bit 1
PECC3.COUNT_0 0 PEC Transfer Count - bit 0
PECC4 0xFEC8 PEC Channel 4 Control Register
PECC4.EOPINT 14 End of PEC Interrupt Selection
PECC4.PLEV_13 13 PEC Level Selection - bit 13
PECC4.PLEV_12 12 PEC Level Selection - bit 12
PECC4.INC_10 10 Increment Control - bit 10
PECC4.INC_9 9 Increment Control - bit 9
PECC4.BWT 8 Byte / Word Transfer Selection
PECC4.COUNT_7 7 PEC Transfer Count - bit 7
PECC4.COUNT_6 6 PEC Transfer Count - bit 6
PECC4.COUNT_5 5 PEC Transfer Count - bit 5
PECC4.COUNT_4 4 PEC Transfer Count - bit 4
PECC4.COUNT_3 3 PEC Transfer Count - bit 3
PECC4.COUNT_2 2 PEC Transfer Count - bit 2
PECC4.COUNT_1 1 PEC Transfer Count - bit 1
PECC4.COUNT_0 0 PEC Transfer Count - bit 0
PECC5 0xFECA PEC Channel 5 Control Register
PECC5.EOPINT 14 End of PEC Interrupt Selection
PECC5.PLEV_13 13 PEC Level Selection - bit 13
PECC5.PLEV_12 12 PEC Level Selection - bit 12
PECC5.INC_10 10 Increment Control - bit 10
PECC5.INC_9 9 Increment Control - bit 9
PECC5.BWT 8 Byte / Word Transfer Selection
PECC5.COUNT_7 7 PEC Transfer Count - bit 7
PECC5.COUNT_6 6 PEC Transfer Count - bit 6
PECC5.COUNT_5 5 PEC Transfer Count - bit 5
PECC5.COUNT_4 4 PEC Transfer Count - bit 4
PECC5.COUNT_3 3 PEC Transfer Count - bit 3
PECC5.COUNT_2 2 PEC Transfer Count - bit 2
PECC5.COUNT_1 1 PEC Transfer Count - bit 1
PECC5.COUNT_0 0 PEC Transfer Count - bit 0
PECC6 0xFECC PEC Channel 6 Control Register
PECC6.EOPINT 14 End of PEC Interrupt Selection
PECC6.PLEV_13 13 PEC Level Selection - bit 13
PECC6.PLEV_12 12 PEC Level Selection - bit 12
PECC6.INC_10 10 Increment Control - bit 10
PECC6.INC_9 9 Increment Control - bit 9
PECC6.BWT 8 Byte / Word Transfer Selection
PECC6.COUNT_7 7 PEC Transfer Count - bit 7
PECC6.COUNT_6 6 PEC Transfer Count - bit 6
PECC6.COUNT_5 5 PEC Transfer Count - bit 5
PECC6.COUNT_4 4 PEC Transfer Count - bit 4
PECC6.COUNT_3 3 PEC Transfer Count - bit 3
PECC6.COUNT_2 2 PEC Transfer Count - bit 2
PECC6.COUNT_1 1 PEC Transfer Count - bit 1
PECC6.COUNT_0 0 PEC Transfer Count - bit 0
PECC7 0xFECE PEC Channel 7 Control Register
PECC7.EOPINT 14 End of PEC Interrupt Selection
PECC7.PLEV_13 13 PEC Level Selection - bit 13
PECC7.PLEV_12 12 PEC Level Selection - bit 12
PECC7.INC_10 10 Increment Control - bit 10
PECC7.INC_9 9 Increment Control - bit 9
PECC7.BWT 8 Byte / Word Transfer Selection
PECC7.COUNT_7 7 PEC Transfer Count - bit 7
PECC7.COUNT_6 6 PEC Transfer Count - bit 6
PECC7.COUNT_5 5 PEC Transfer Count - bit 5
PECC7.COUNT_4 4 PEC Transfer Count - bit 4
PECC7.COUNT_3 3 PEC Transfer Count - bit 3
PECC7.COUNT_2 2 PEC Transfer Count - bit 2
PECC7.COUNT_1 1 PEC Transfer Count - bit 1
PECC7.COUNT_0 0 PEC Transfer Count - bit 0
IDX0 0xFF08 MAC Unit Address Pointer
IDX0.IDX0_15 15 Modifiable portion of register IDX0 - bit 15
IDX0.IDX0_14 14 Modifiable portion of register IDX0 - bit 14
IDX0.IDX0_13 13 Modifiable portion of register IDX0 - bit 13
IDX0.IDX0_12 12 Modifiable portion of register IDX0 - bit 12
IDX0.IDX0_11 11 Modifiable portion of register IDX0 - bit 11
IDX0.IDX0_10 10 Modifiable portion of register IDX0 - bit 10
IDX0.IDX0_9 9 Modifiable portion of register IDX0 - bit 9
IDX0.IDX0_8 8 Modifiable portion of register IDX0 - bit 8
IDX0.IDX0_7 7 Modifiable portion of register IDX0 - bit 7
IDX0.IDX0_6 6 Modifiable portion of register IDX0 - bit 6
IDX0.IDX0_5 5 Modifiable portion of register IDX0 - bit 5
IDX0.IDX0_4 4 Modifiable portion of register IDX0 - bit 4
IDX0.IDX0_3 3 Modifiable portion of register IDX0 - bit 3
IDX0.IDX0_2 2 Modifiable portion of register IDX0 - bit 2
IDX0.IDX0_1 1 Modifiable portion of register IDX0 - bit 1
IDX1 0xFF0A MAC Unit Address Pointer
IDX1.IDX1_15 15 Modifiable portion of register IDX1 - bit 15
IDX1.IDX1_14 14 Modifiable portion of register IDX1 - bit 14
IDX1.IDX1_13 13 Modifiable portion of register IDX1 - bit 13
IDX1.IDX1_12 12 Modifiable portion of register IDX1 - bit 12
IDX1.IDX1_11 11 Modifiable portion of register IDX1 - bit 11
IDX1.IDX1_10 10 Modifiable portion of register IDX1 - bit 10
IDX1.IDX1_9 9 Modifiable portion of register IDX1 - bit 9
IDX1.IDX1_8 8 Modifiable portion of register IDX1 - bit 8
IDX1.IDX1_7 7 Modifiable portion of register IDX1 - bit 7
IDX1.IDX1_6 6 Modifiable portion of register IDX1 - bit 6
IDX1.IDX1_5 5 Modifiable portion of register IDX1 - bit 5
IDX1.IDX1_4 4 Modifiable portion of register IDX1 - bit 4
IDX1.IDX1_3 3 Modifiable portion of register IDX1 - bit 3
IDX1.IDX1_2 2 Modifiable portion of register IDX1 - bit 2
IDX1.IDX1_1 1 Modifiable portion of register IDX1 - bit 1
SPSEG 0xFF0C Stack Pointer Segment Register
SPSEG.SPSEGNR_7 7 Stack Pointer Segment Number - bit 7
SPSEG.SPSEGNR_6 6 Stack Pointer Segment Number - bit 6
SPSEG.SPSEGNR_5 5 Stack Pointer Segment Number - bit 5
SPSEG.SPSEGNR_4 4 Stack Pointer Segment Number - bit 4
SPSEG.SPSEGNR_3 3 Stack Pointer Segment Number - bit 3
SPSEG.SPSEGNR_2 2 Stack Pointer Segment Number - bit 2
SPSEG.SPSEGNR_1 1 Stack Pointer Segment Number - bit 1
SPSEG.SPSEGNR_0 0 Stack Pointer Segment Number - bit 0
MDC 0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU 4 Multiply/Divide Register In Use
PSW 0xFF10 CPU Program Status Word
PSW.ILVL_15 15 CPU Priority Level - bit 15
PSW.ILVL_14 14 CPU Priority Level - bit 14
PSW.ILVL_13 13 CPU Priority Level - bit 13
PSW.ILVL_12 12 CPU Priority Level - bit 12
PSW.IEN 11 Global Interrupt/PEC Enable Bit
PSW.HLDEN 10 HOLD Enable Bit
PSW.BANK_9 9 Reserved for register file bank selection - bit 8
PSW.BANK_8 8 Reserved for register file bank selection - bit 8
PSW.USR1 7 User Flag
PSW.USR0 6 User Flag
PSW.MULIP 5 Multiplication/Division in progress
PSW.E 4 End of table Flag
PSW.Z 3 Zero Flag
PSW.V 2 Overflow Flag
PSW.C 1 Carry Flag
PSW.N 0 Negative Result
VECSEG 0xFF12 Vector Table Segment Register
VECSEG.VECSEG_7 7 Segment number of the Vector Table - bit 7
VECSEG.VECSEG_6 6 Segment number of the Vector Table - bit 6
VECSEG.VECSEG_5 5 Segment number of the Vector Table - bit 5
VECSEG.VECSEG_4 4 Segment number of the Vector Table - bit 4
VECSEG.VECSEG_3 3 Segment number of the Vector Table - bit 3
VECSEG.VECSEG_2 2 Segment number of the Vector Table - bit 2
VECSEG.VECSEG_1 1 Segment number of the Vector Table - bit 1
VECSEG.VECSEG_0 0 Segment number of the Vector Table - bit 0
ZEROS 0xFF1C Constant Value 0's Register (read only)
ONES 0xFF1E Constant Value 1's Register (read only)
PWMCON0 0xFF30 PWM Module Control Register 0
PWMCON0.PIR1 13
PWMCON0.PIR0 12
PWMCON0.PIE1 9
PWMCON0.PIE0 8
PWMCON0.PTI1 5
PWMCON0.PTI0 4
PWMCON0.PTR1 1
PWMCON0.PTR0 0
PWMCON1 0xFF32 PWM Module Control Register 1
T2CON 0xFF40 GPT12E Timer 2 Control Register
T3CON 0xFF42 GPT12E Timer 3 Control Register
T4CON 0xFF44 GPT12E Timer 4 Control Register
T5CON 0xFF46 GPT12E Timer 5 Control Register
T6CON 0xFF48 GPT12E Timer 6 Control Register
T2IC 0xFF60 GPT12E Timer 2 Interrupt Control Register
T2IC.T2ICIR 7 Interrupt Request Flag
T2IC.T2ICIE 6 Interrupt Enable Control Bit
T2IC.ILVL_5 5 Interrupt Priority Level - bit 5
T2IC.ILVL_4 4 Interrupt Priority Level - bit 4
T2IC.ILVL_3 3 Interrupt Priority Level - bit 3
T2IC.ILVL_2 2 Interrupt Priority Level - bit 2
T2IC.GLVL_1 1 Group Priority Level - bit 1
T2IC.GLVL_0 0 Group Priority Level - bit 0
T3IC 0xFF62 GPT12E Timer 3 Interrupt Control Register
T3IC.T3ICIR 7 Interrupt Request Flag
T3IC.T3ICIE 6 Interrupt Enable Control Bit
T3IC.ILVL_5 5 Interrupt Priority Level - bit 5
T3IC.ILVL_4 4 Interrupt Priority Level - bit 4
T3IC.ILVL_3 3 Interrupt Priority Level - bit 3
T3IC.ILVL_2 2 Interrupt Priority Level - bit 2
T3IC.GLVL_1 1 Group Priority Level - bit 1
T3IC.GLVL_0 0 Group Priority Level - bit 0
T4IC 0xFF64 GPT12E Timer 4 Interrupt Control Register
T4IC.T4ICIR 7 Interrupt Request Flag
T4IC.T4ICIE 6 Interrupt Enable Control Bit
T4IC.ILVL_5 5 Interrupt Priority Level - bit 5
T4IC.ILVL_4 4 Interrupt Priority Level - bit 4
T4IC.ILVL_3 3 Interrupt Priority Level - bit 3
T4IC.ILVL_2 2 Interrupt Priority Level - bit 2
T4IC.GLVL_1 1 Group Priority Level - bit 1
T4IC.GLVL_0 0 Group Priority Level - bit 0
T5IC 0xFF66 GPT12E Timer 5 Interrupt Control Register
T5IC.T5ICIR 7 Interrupt Request Flag
T5IC.T5ICIE 6 Interrupt Enable Control Bit
T5IC.ILVL_5 5 Interrupt Priority Level - bit 5
T5IC.ILVL_4 4 Interrupt Priority Level - bit 4
T5IC.ILVL_3 3 Interrupt Priority Level - bit 3
T5IC.ILVL_2 2 Interrupt Priority Level - bit 2
T5IC.GLVL_1 1 Group Priority Level - bit 1
T5IC.GLVL_0 0 Group Priority Level - bit 0
T6IC 0xFF68 GPT12E Timer 6 Interrupt Control Register
T6IC.T6ICIR 7 Interrupt Request Flag
T6IC.T6ICIE 6 Interrupt Enable Control Bit
T6IC.ILVL_5 5 Interrupt Priority Level - bit 5
T6IC.ILVL_4 4 Interrupt Priority Level - bit 4
T6IC.ILVL_3 3 Interrupt Priority Level - bit 3
T6IC.ILVL_2 2 Interrupt Priority Level - bit 2
T6IC.GLVL_1 1 Group Priority Level - bit 1
T6IC.GLVL_0 0 Group Priority Level - bit 0
CRIC 0xFF6A GPT12E CAPREL Interrupt Control Register
CRIC.CRICIR 7 Interrupt Request Flag
CRIC.CRICIE 6 Interrupt Enable Control Bit
CRIC.ILVL_5 5 Interrupt Priority Level - bit 5
CRIC.ILVL_4 4 Interrupt Priority Level - bit 4
CRIC.ILVL_3 3 Interrupt Priority Level - bit 3
CRIC.ILVL_2 2 Interrupt Priority Level - bit 2
CRIC.GLVL_1 1 Group Priority Level - bit 1
CRIC.GLVL_0 0 Group Priority Level - bit 0
S0TIC 0xFF6C Serial Channel 0 Transmit Interrupt Control Register
S0TIC.S0TICIR 7 Interrupt Request Flag
S0TIC.S0TICIE 6 Interrupt Enable Control Bit
S0TIC.ILVL_5 5 Interrupt Priority Level - bit 5
S0TIC.ILVL_4 4 Interrupt Priority Level - bit 4
S0TIC.ILVL_3 3 Interrupt Priority Level - bit 3
S0TIC.ILVL_2 2 Interrupt Priority Level - bit 2
S0TIC.GLVL_1 1 Group Priority Level - bit 1
S0TIC.GLVL_0 0 Group Priority Level - bit 0
S0RIC 0xFF6E Serial Channel 0 Receive Interrupt Control Register
S0RIC.S0RICIR 7 Interrupt Request Flag
S0RIC.S0RICIE 6 Interrupt Enable Control Bit
S0RIC.ILVL_5 5 Interrupt Priority Level - bit 5
S0RIC.ILVL_4 4 Interrupt Priority Level - bit 4
S0RIC.ILVL_3 3 Interrupt Priority Level - bit 3
S0RIC.ILVL_2 2 Interrupt Priority Level - bit 2
S0RIC.GLVL_1 1 Group Priority Level - bit 1
S0RIC.GLVL_0 0 Group Priority Level - bit 0
S0EIC 0xFF70 Serial Channel 0 Error Interrupt Control Register
S0EIC.S0EICIR 7 Interrupt Request Flag
S0EIC.S0EICIE 6 Interrupt Enable Control Bit
S0EIC.ILVL_5 5 Interrupt Priority Level - bit 5
S0EIC.ILVL_4 4 Interrupt Priority Level - bit 4
S0EIC.ILVL_3 3 Interrupt Priority Level - bit 3
S0EIC.ILVL_2 2 Interrupt Priority Level - bit 2
S0EIC.GLVL_1 1 Group Priority Level - bit 1
S0EIC.GLVL_0 0 Group Priority Level - bit 0
SSCTIC 0xFF72 SSC0 Transmit Interrupt Control Register
SSCTIC.SSCTICIR 7 Interrupt Request Flag
SSCTIC.SSCTICIE 6 Interrupt Enable Control Bit
SSCTIC.ILVL_5 5 Interrupt Priority Level - bit 5
SSCTIC.ILVL_4 4 Interrupt Priority Level - bit 4
SSCTIC.ILVL_3 3 Interrupt Priority Level - bit 3
SSCTIC.ILVL_2 2 Interrupt Priority Level - bit 2
SSCTIC.GLVL_1 1 Group Priority Level - bit 1
SSCTIC.GLVL_0 0 Group Priority Level - bit 0
SSCRIC 0xFF74 SSC0 Receive Interrupt Control Register
SSCRIC.SSCRICIR 7 Interrupt Request Flag
SSCRIC.SSCRICIE 6 Interrupt Enable Control Bit
SSCRIC.ILVL_5 5 Interrupt Priority Level - bit 5
SSCRIC.ILVL_4 4 Interrupt Priority Level - bit 4
SSCRIC.ILVL_3 3 Interrupt Priority Level - bit 3
SSCRIC.ILVL_2 2 Interrupt Priority Level - bit 2
SSCRIC.GLVL_1 1 Group Priority Level - bit 1
SSCRIC.GLVL_0 0 Group Priority Level - bit 0
SSCEIC 0xFF76 SSC0 Error Interrupt Control Register
SSCEIC.SSCEICIR 7 Interrupt Request Flag
SSCEIC.SSCEICIE 6 Interrupt Enable Control Bit
SSCEIC.ILVL_5 5 Interrupt Priority Level - bit 5
SSCEIC.ILVL_4 4 Interrupt Priority Level - bit 4
SSCEIC.ILVL_3 3 Interrupt Priority Level - bit 3
SSCEIC.ILVL_2 2 Interrupt Priority Level - bit 2
SSCEIC.GLVL_1 1 Group Priority Level - bit 1
SSCEIC.GLVL_0 0 Group Priority Level - bit 0
FEI0IC 0xFF88 Fast External Interrupt 0 Control Register
FEI0IC.FEI0ICIR 7 Interrupt Request Flag
FEI0IC.FEI0ICIE 6 Interrupt Enable Control Bit
FEI0IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI0IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI0IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI0IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI0IC.GLVL_1 1 Group Priority Level - bit 1
FEI0IC.GLVL_0 0 Group Priority Level - bit 0
FEI1IC 0xFF8A Fast External Interrupt 1 Control Register
FEI1IC.FEI1ICIR 7 Interrupt Request Flag
FEI1IC.FEI1ICIE 6 Interrupt Enable Control Bit
FEI1IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI1IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI1IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI1IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI1IC.GLVL_1 1 Group Priority Level - bit 1
FEI1IC.GLVL_0 0 Group Priority Level - bit 0
FEI2IC 0xFF8C Fast External Interrupt 2 Control Register
FEI2IC.FEI2ICIR 7 Interrupt Request Flag
FEI2IC.FEI2ICIE 6 Interrupt Enable Control Bit
FEI2IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI2IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI2IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI2IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI2IC.GLVL_1 1 Group Priority Level - bit 1
FEI2IC.GLVL_0 0 Group Priority Level - bit 0
FEI3IC 0xFF8E Fast External Interrupt 3 Control Register
FEI3IC.FEI3ICIR 7 Interrupt Request Flag
FEI3IC.FEI3ICIE 6 Interrupt Enable Control Bit
FEI3IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI3IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI3IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI3IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI3IC.GLVL_1 1 Group Priority Level - bit 1
FEI3IC.GLVL_0 0 Group Priority Level - bit 0
FEI4IC 0xFF90 Fast External Interrupt 4 Control Register
FEI4IC.FEI4ICIR 7 Interrupt Request Flag
FEI4IC.FEI4ICIE 6 Interrupt Enable Control Bit
FEI4IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI4IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI4IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI4IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI4IC.GLVL_1 1 Group Priority Level - bit 1
FEI4IC.GLVL_0 0 Group Priority Level - bit 0
FEI5IC 0xFF92 Fast External Interrupt 5 Control Register
FEI5IC.FEI5ICIR 7 Interrupt Request Flag
FEI5IC.FEI5ICIE 6 Interrupt Enable Control Bit
FEI5IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI5IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI5IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI5IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI5IC.GLVL_1 1 Group Priority Level - bit 1
FEI5IC.GLVL_0 0 Group Priority Level - bit 0
FEI6IC 0xFF94 Fast External Interrupt 6 Control Register
FEI6IC.FEI6ICIR 7 Interrupt Request Flag
FEI6IC.FEI6ICIE 6 Interrupt Enable Control Bit
FEI6IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI6IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI6IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI6IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI6IC.GLVL_1 1 Group Priority Level - bit 1
FEI6IC.GLVL_0 0 Group Priority Level - bit 0
FEI7IC 0xFF96 Fast External Interrupt 7 Control Register
FEI7IC.FEI7ICIR 7 Interrupt Request Flag
FEI7IC.FEI7ICIE 6 Interrupt Enable Control Bit
FEI7IC.ILVL_5 5 Interrupt Priority Level - bit 5
FEI7IC.ILVL_4 4 Interrupt Priority Level - bit 4
FEI7IC.ILVL_3 3 Interrupt Priority Level - bit 3
FEI7IC.ILVL_2 2 Interrupt Priority Level - bit 2
FEI7IC.GLVL_1 1 Group Priority Level - bit 1
FEI7IC.GLVL_0 0 Group Priority Level - bit 0
P5 0xFFA2 Port 5 Register (read only)
PECISNC 0xFFA8 PEC Interrupt Subnode Control Register
PECISNC.C7IR 15 Interrupt Sub-node Request Flag of PEC Channel 7
PECISNC.C7IE 14 Interrupt Sub-node Enable Control Bit of PEC Channel 7
PECISNC.C6IR 13 Interrupt Sub-node Request Flag of PEC Channel 6
PECISNC.C6IE 12 Interrupt Sub-node Enable Control Bit of PEC Channel 6
PECISNC.C5IR 11 Interrupt Sub-node Request Flag of PEC Channel 5
PECISNC.C5IE 10 Interrupt Sub-node Enable Control Bit of PEC Channel 5
PECISNC.C4IR 9 Interrupt Sub-node Request Flag of PEC Channel 4
PECISNC.C4IE 8 Interrupt Sub-node Enable Control Bit of PEC Channel 4
PECISNC.C3IR 7 Interrupt Sub-node Request Flag of PEC Channel 3
PECISNC.C3IE 6 Interrupt Sub-node Enable Control Bit of PEC Channel 3
PECISNC.C2IR 5 Interrupt Sub-node Request Flag of PEC Channel 2
PECISNC.C2IE 4 Interrupt Sub-node Enable Control Bit of PEC Channel 2
PECISNC.C1IR 3 Interrupt Sub-node Request Flag of PEC Channel 1
PECISNC.C1IE 2 Interrupt Sub-node Enable Control Bit of PEC Channel 1
PECISNC.C0IR 1 Interrupt Sub-node Request Flag of PEC Channel 0
PECISNC.C0IE 0 Interrupt Sub-node Enable Control Bit of PEC Channel 0
TFR 0xFFAC Trap Flag Register
TFR.NMI 15 Non maskable interrupt flag
TFR.STKOF 14 Stack overflow flag
TFR.STKUF 13 Stack underflow flag
TFR.SOFTBRK 12 Software Break
TFR.UNDOPC 7 Undefined Opcode
TFR.PARFLT 4 Parity Fault
TFR.PRTFLT 3 Protection Fault
TFR.ILLOPA 2 Illegal word operand access
WDTCON 0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL_15 15 Watchdog Timer Reload value (for high byte of WDT) - bit 15
WDTCON.WDTREL_14 14 Watchdog Timer Reload value (for high byte of WDT) - bit 14
WDTCON.WDTREL_13 13 Watchdog Timer Reload value (for high byte of WDT) - bit 13
WDTCON.WDTREL_12 12 Watchdog Timer Reload value (for high byte of WDT) - bit 12
WDTCON.WDTREL_11 11 Watchdog Timer Reload value (for high byte of WDT) - bit 11
WDTCON.WDTREL_10 10 Watchdog Timer Reload value (for high byte of WDT) - bit 10
WDTCON.WDTREL_9 9 Watchdog Timer Reload value (for high byte of WDT) - bit 9
WDTCON.WDTREL_8 8 Watchdog Timer Reload value (for high byte of WDT) - bit 8
WDTCON.WDTIN_1 1 Watchdog Timer Input Frequency Selection - bit 1
WDTCON.WDTIN_0 0 Watchdog Timer Input Frequency Selection - bit 0
S0CON 0xFFB0 Serial Channel 0 Control Register
SSCCON 0xFFB2 SSC0 Control Register
P2 0xFFC0 Port 2 Register
DP2 0xFFC2 Port 2 Direction Control Register
P3 0xFFC4 Port 3 Register
DP3 0xFFC6 Port 3 Direction Control Register
MRW 0xFFDA MAC Unit Repeat Word
MRW.MRW_15 15 16-bit loop counter - bit 15
MRW.MRW_14 14 16-bit loop counter - bit 14
MRW.MRW_13 13 16-bit loop counter - bit 13
MRW.MRW_12 12 16-bit loop counter - bit 12
MRW.MRW_11 11 16-bit loop counter - bit 11
MRW.MRW_10 10 16-bit loop counter - bit 10
MRW.MRW_9 9 16-bit loop counter - bit 9
MRW.MRW_8 8 16-bit loop counter - bit 8
MRW.MRW_7 7 16-bit loop counter - bit 7
MRW.MRW_6 6 16-bit loop counter - bit 6
MRW.MRW_5 5 16-bit loop counter - bit 5
MRW.MRW_4 4 16-bit loop counter - bit 4
MRW.MRW_3 3 16-bit loop counter - bit 3
MRW.MRW_2 2 16-bit loop counter - bit 2
MRW.MRW_1 1 16-bit loop counter - bit 1
MRW.MRW_0 0 16-bit loop counter - bit 0
MCW 0xFFDC MAC Unit Control Word
MCW.MS 10 Saturation mode control
MCW.MP 9 One-bit scaler control
MSW 0xFFDE MAC Unit Status Word
MSW.MAE_7 7 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 7
MSW.MAE_6 6 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 6
MSW.MAE_5 5 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 5
MSW.MAE_4 4 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 4
MSW.MAE_3 3 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 3
MSW.MAE_2 2 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 2
MSW.MAE_1 1 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 1
MSW.MAE_0 0 The most significant byte (bits 39 to 32) of the 40-bit Accumulator - bit 0