; The format of the input file:
; each device definition begins with a line like this:
;
;       .devicename
;
;  after it go the port definitions in this format:
;
;       portname        address
;
;  the bit definitions (optional) are represented like this:
;
;       portname.bitname  bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
;       .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; NSC CompactRISC CR16 SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:

;       area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
;       START and END are addresses, the end address is not included

; Interrupt vectors are declared in the following way:

; entry NAME ADDRESS COMMENT

.default SC14402


.SC14402

; MEMORY MAP
area DATA SRAM  0xEA00:0xEC00   Sequencer RAM
area DATA IRAM  0xEC00:0xF400   Internal RAM
area DATA DRAM  0xF400:0xFBFE   Data RAM
area DATA FSR   0xFBFE:0x10000  Special Function Register

; Interrupt and reset vector assignments
interrupt RESET_        0x0000  RESET
interrupt NMI_          0x0004  NMI
interrupt TRAP_SVC_     0x000A  Trap SVC
interrupt TRAP_DVZ_     0x000C  Trap DVZ
interrupt TRAP_FLG_     0x000E  Trap FLG
interrupt TRAP_BPT_     0x0010  Trap BPT
interrupt TRAP_TRC_     0x0012  Trap TRC
interrupt TRAP_UND_     0x0014  Trap UND
interrupt ISE_          0x001E  ISE
interrupt IRQ0_         0x0020  SW INT
interrupt IRQ1_         0x0022  Keyboard IRQ
interrupt IRQ2_         0x0024  UART IRQ
interrupt IRQ3_         0x0026  Timer 0 IRQ
interrupt IRQ4_         0x0028  Timer 1 IRQ
interrupt IRQ5_         0x002A  Clk 100 IRQ
interrupt IRQ6_         0x002C  DIP IRQ

; INPUT/OUTPUT
DIPPC           0xFBFE  DIP Programm Counter
DIPCTRL         0xFBFF  DIP Controll
INTRESET        0xFF02  Reset Interrupt
INTSET          0xFF03  Set Interrupt
SWINTPRI        0xFF04  SW INT Priority
KBINTPRI        0xFF05  KB INT Priority
UARTINTPRI      0xFF06  UART INT Priority
T0INTPRI        0xFF07  T0 INT Priority
T1INTPRI        0xFF08  T1 INT Priority
CLKINTPRI       0xFF09  CLK100 INT Priority
DIPINTPRI       0xFF0A  DIP INT Priority
P0DATA          0xFF10  Port 0
P0SET           0xFF11  Port 0 Set Bit
P0RESET         0xFF12  Port 0 Reset Bit
P0DIR           0xFF13  Port 0 Direction
P0UARTCTL       0xFF14  Port 0 UART Controll
P0UARTDATA      0xFF15  Port 0 UART Data Register
P0ENV           0xFF16  Port 0 Environ
P0TEST          0xFF17  Port 0 ADPCM/CODEC Testpoints
P1DATA          0xFF20  Port 1
P1SET           0xFF21  Port 1 Set Bit
P1RESET         0xFF22  Port 1 Reset Bit
P1DIR           0xFF23  Port 1 Direction
P1INTENABLE     0xFF24  Port 1 Interrupt Enable
P1FILTER        0xFF25  Port 1 debounce filter
P2DATA          0xFF30  Port 2
P2DIR           0xFF33  Port 2 Direction
P2MODE          0xFF34  Port 2 Mode
P2ADCCONTROLL   0xFF35  Port 2 ADC Controll
P2ADCVALUE      0xFF36  Port 2 ADC Value
P2DACVALUE      0xFF37  Port 2 DAC Value
WTDG_RELOAD     0xFF40  Watchdog Reload
T0RELOADMLO     0xFF42  Timer 0 Reload M Low
T0RELOADMHI     0xFF43  Timer 0 Reload M Low
T0RELOADNLO     0xFF44  Timer 0 Reload N Low
T0RELOADNHI     0xFF45  Timer 0 Reload N Low
T1RELOADMLO     0xFF46  Timer 1 Reload M Low
T1RELOADMHI     0xFF47  Timer 1 Reload M Low
T1RELOADNLO     0xFF48  Timer 1 Reload N Low
T1RELOADNHI     0xFF49  Timer 1 Reload N Low
TIMERCONTROLL   0xFF4A  Timer Controll
SBICLK          0xFF50  SBI Clock
SBIBANK         0xFF51  SBI Bank
SBIAUXCSLOW     0xFF52  SBI Aux chipselect controll low
SBIAUXCSHIGH    0xFF53  SBI Aux chipselect controll high
SBIAUXWAIT      0xFF54  SBI AUX Wait
SBISETFREEZE    0xFF55  SBI Set Freeze
SBIRESETFREEZE  0xFF56  SBI Reset Freeze
DEBUGSFR        0xFF57  DEBUG Register

.CR16MCS9

; MEMORY MAP
area CODE FLASH   0x0000:0xC000   Flash Program Memory
area DATA SRAM    0xC000:0xCC00   Static RAM
area DATA ISP     0xE000:0xE600   ISP Memory
area DATA EEPROM  0xE800:0xF000   EEPROM
area DATA EEPROM  0xF000:0xF080   EEPROM
area DATA FSR     0xF400:0x10000  Peripherals

; Interrupt and reset vector assignments
interrupt RESET_        0x0000  RESET
;interrupt NMI_          0x0004  NMI
;interrupt TRAP_SVC_     0x000A  Trap SVC
;interrupt TRAP_DVZ_     0x000C  Trap DVZ
;interrupt TRAP_FLG_     0x000E  Trap FLG
;interrupt TRAP_BPT_     0x0010  Trap BPT
;interrupt TRAP_TRC_     0x0012  Trap TRC
;interrupt TRAP_UND_     0x0014  Trap UND
;interrupt ISE_          0x001E  ISE
;interrupt IRQ0_         0x0020  SW INT
;interrupt IRQ1_         0x0022  Keyboard IRQ
;interrupt IRQ2_         0x0024  UART IRQ
;interrupt IRQ3_         0x0026  Timer 0 IRQ
;interrupt IRQ4_         0x0028  Timer 1 IRQ
;interrupt IRQ5_         0x002A  Clk 100 IRQ
;interrupt IRQ6_         0x002C  DIP IRQ

; INPUT/OUTPUT
BCFG        0xf900
IOCFG       0xf902
SZCFG0      0xf904
SZCFG1      0xf906
SZCFG2      0xf908
MCFG        0xf910
DBGCFG      0xf912
MSTAT       0xf914
TMODE       0xf920
FLCTRL1     0xf930
FLSEC       0xf932
ISPKEY      0xf934
FLCTRL2     0xf936
DMCSR       0xf940
DMPSLR      0xf942
DMSTART     0xf944
DMTRAN      0xf946
DMPROG      0xf948
DMERASE     0xf94a
DMEND       0xf94c
DMPCNT      0xf94e
DMCNT       0xf950
DMISTAT     0xf952
DMKEY       0xf954
FLCSR       0xf960
FLPSLR      0xf962
FLSTART     0xf964
FLTRAN      0xf966
FLPROG      0xf968
FLERASE     0xf96a
FLEND       0xf96c
FLPCNT      0xf96e
FLCNT1      0xf970
FLCNT2      0xf972
PGMKEY      0xf974
PBDIR       0xfb00
PBDIN       0xfb02
PBDOUT      0xfb04
PBWKPU      0xfb06
PCDIR       0xfb10
PCDIN       0xfb12
PCDOUT      0xfb14
PCWKPU      0xfb16
PFALT       0xfd20
PFDIR       0xfd22
PFDIN       0xfd24
PFDOUT      0xfd26
PFWKPU      0xfd28
PFSCHEN     0xfd2a
PGALT       0xfca0
PGDIR       0xfca2
PGDIN       0xfca4
PGDOUT      0xfca6
PGWKPU      0xfca8
PGSCHEN     0xfcaa
PHALT       0xfcc0
PHDIR       0xfcc2
PHDIN       0xfcc4
PHDOUT      0xfcc6
PHWKPU      0xfcc8
PIALT       0xfee0
PIDIR       0xfee2
PIDIN       0xfee4
PIDOUT      0xfee6
PIWKPU      0xfee8
PISCHEN     0xfeea
PLALT       0xff00
PLDIR       0xff02
PLDIN       0xff04
PLDOUT      0xff06
PLWKPU      0xff08
PLSCHEN     0xff0a
CRCTRL      0xfc40
PRSSC       0xfc42
PRSSC1      0xfc44
PMCSR       0xfc60
WKEDG       0xfc80
WKENA       0xfc82
WKICTL      0xfc84
WKICTL2     0xfc86
WKPND       0xfc88
WKPCL       0xfc8a
IVCT        0xfe00
NMISTAT     0xfe02
EXNMI       0xfe04
NMIIMNTR    0xfe06
ISTAT0      0xfe0a
ISTAT1      0xfe0c
IENAM0      0xfe0e
IENAM1      0xfe10
IDBG        0xfe1a
ITEST0      0xfe1c
ITEST1      0xfe1e
U1TBUF      0xfe40
U1RBUF      0xfe42
U1ICTRL     0xfe44
U1STAT      0xfe46
U1FRS       0xfe48
U1MDSL      0xfe4a
U1BAUD      0xfe4c
U1PSR       0xfe4e
U2TBUF      0xfe80
U2RBUF      0xfe82
U2ICTRL     0xfe84
U2STAT      0xfe86
U2FRS       0xfe88
U2MDSL      0xfe8a
U2BAUD      0xfe8c
U2PSR       0xfe8e
ACBSDA      0xfec0
ACBST       0xfec2
ACBCST      0xfec4
ACBCTL1     0xfec6
ACBADDR     0xfec8
ACBCTL2     0xfeca
MWDAT       0xfe60
MWCTL       0xfe62
MWSTAT      0xfe64
MWTEST      0xfe66
TWCFG       0xff20
TWCP        0xff22
TWMT0       0xff24
T0CSR       0xff26
WDCNT       0xff28
WDSDM       0xff2a
T1CNT1      0xff40
T1CRA       0xff42
T1CRB       0xff44
T1CNT2      0xff46
T1PRSC      0xff48
T1CKC       0xff4A
T1CTRL      0xff4C
T1ICTL      0xff4E
T1ICLR      0xff50
T2CNT1      0xff60
T2CRA       0xff62
T2CRB       0xff64
T2CNT2      0xff66
T2PRSC      0xff68
T2CKC       0xff6A
T2CTRL      0xff6C
T2ICTL      0xff6E
T2ICLR      0xff70
MODE        0xff80
IO1CTL      0xff82
IO2CTL      0xff84
INTCTL      0xff86
INTPND      0xff88
CLK1PS      0xff8a
COUNT1      0xff8c
PERCAP1     0xff8e
DTYCAP1     0xff90
COUNT2      0xff92
PERCAP2     0xff94
DTYCAP2     0xff96
CLK2PS      0xff98
COUNT3      0xff9a
PERCAP3     0xff9c
DTYCAP3     0xff9e
COUNT4      0xffa0
PERCAP4     0xffa2
DTYCAP4     0xffa4
ADCST       0xffC0
ADCCNT1     0xffC2
ADCCNT2     0xffC4
ADCCNT3     0xffC6
ADCENG      0xffC8
ADDATA0     0xffCA
ADDATA1     0xffCC
ADDATA2     0xffCE
ADDATA3     0xffD0
ACMP        0xffe0
CMB0_CNTSTAT    0xf400
CMB0_TSTP       0xf402
CMB0_DATA3      0xf404
CMB0_DATA2      0xf406
CMB0_DATA1      0xf408
CMB0_DATA0      0xf40a
CMB0_ID0        0xf40c
CMB0_ID1        0xf40e
CMB1        0xf410
CMB2        0xf420
CMB3        0xf430
CMB4        0xf440
CMB5        0xf450
CMB6        0xf460
CMB7        0xf470
CMB8        0xf480
CMB9        0xf490
CMB10       0xf4a0
CMB11       0xf4b0
CMB12       0xf4c0
CMB13       0xf4d0
CMB14       0xf4e0
CMB15       0xf4f0
CGCR        0xf500
CTIM        0xf502
GMSKX       0xf504
GMSKB       0xf506
BMSKX       0xf508
BMSKB       0xf50a
CIEN        0xf50c
CIPND       0xf50e
CICLR       0xf510
CICEN       0xf512
CSTPND      0xf514
CANEC       0xf516
CEDIAG      0xf518
CTMR        0xf51a
BSPD        0xf51c
RTDIAG      0xf51e