Why Gemfury?
Push, build, and install
RubyGems
npm packages
Python packages
Maven artifacts
PHP packages
Go Modules
Debian packages
RPM packages
NuGet packages
Repository URL to install this package:
|
Version:
9.0~240925-3.fc42 ▾
|
;; Copied from m7900.cfg
; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
.default m16c
.m16c
; SFR area
pm0 0x4 Processor mode register 0
pm0.pm00 0 Processor mode bit
pm0.pm01 1 Processor mode bit
pm0.pm02 2 R/W mode select bit
pm0.pm03 3 Software reset bit
pm0.pm04 4 Multiplexed bus space select bit
pm0.pm05 5 Multiplexed bus space select bit
pm0.pm06 6 Port P40 to P43 function select bit
pm0.pm07 7 BCLK output disable bit
pm1 0x5 Processor mode register 1
pm1.pm13 3 Internal reserved area expansion bit
pm1.pm17 7 Wait bit
cm0 0x6 System clock control register 0
cm0.cm00 0 Clock output function select bit
cm0.cm01 1 Clock output function select bit
cm0.cm02 2 WAIT peripheral function clock stop bit
cm0.cm03 3 Xcin-Xcout drive capacity select bit
cm0.cm04 4 Port Xc select bit
cm0.cm05 5 Main clock stop bit
cm0.cm06 6 Main clock division select bit 0
cm0.cm07 7 System clock select bit
cm1 0x7 System clock control register 1
cm1.cm10 0 All clock stop control bit
cm1.cm15 5 Xin-Xout drive capacity select bit
cm1.cm16 6 Main clock division select bit 1
cm1.cm17 7 Main clock division select bit 1
csr 0x8 Chip select control register
csr.cs0 0 CS0~ output enable bit
csr.cs1 1 CS1~ output enable bit
csr.cs2 2 CS2~ output enable bit
csr.cs3 3 CS3~ output enable bit
csr.cs0w 4 CS0~ wait bit
csr.cs1w 5 CS1~ wait bit
csr.cs2w 6 CS2~ wait bit
csr.cs3w 7 CS3~ wait bit
aier 0x9 Address match interrupt enable register
aier.aier0 0 Address match interrupt 0 enable bit
aier.aier1 1 Address match interrupt 1 enable bit
prcr 0xa Protect register
prcr.prc0 0 Enable writting to system clock control registers 0 and 1
prcr.prc1 1 Enable writting to processor mode registers 0 and 1
prcr.prc2 2 Enable writting to port P9 direction register and SI/Oi control register(i=3,4)
wdts 0xe Watchdog timer start register
wdc 0xf Watchdog timer control register
wdc.wdc7 7 Prescaler select bit
rmad0 0x10 Address match interrupt register 0 L
rmad0m 0x11 Address match interrupt register 0 M
rmad0h 0x12 Address match interrupt register 0 H
rmad1 0x14 Address match interrupt register 1 L
rmad1m 0x15 Address match interrupt register 1 M
rmad1h 0x16 Address match interrupt register 1 H
sar0 0x20 DMA0 source pointer L
sar0m 0x21 DMA0 source pointer M
sar0h 0x22 DMA0 source pointer H
dar0 0x24 DMA0 destination pointer L
dar0m 0x25 DMA0 destination pointer M
dar0h 0x26 DMA0 destination pointer H
tcr0 0x28 DMA0 transfer counter L
tcr0h 0x29 DMA0 transfer counter H
dm0con 0x2c DMA0 control register
dm0con.dmbit_dm0con 0 Transfer unit bit select bit
dm0con.dmasl_dm0con 1 Repeat transfer mode select bit
dm0con.dmas_dm0con 2 DMA request bit
dm0con.dmae_dm0con 3 DMA enable bit
dm0con.dsd_dm0con 4 Source address direction select bit
dm0con.dad_dm0con 5 Destination address direction select bit
sar1 0x30 DMA1 source pointer L
sar1m 0x31 DMA1 source pointer M
sar1h 0x32 DMA1 source pointer H
dar1 0x34 DMA1 destination pointer L
dar1m 0x35 DMA1 destination pointer M
dar1h 0x36 DMA1 destination pointer H
tcr1 0x38 DMA1 transfer counter L
tcr1h 0x39 DMA1 transfer counter H
dm1con 0x3c DMA1 control register
dm1con.dmbit_dm1con 0 Transfer unit bit select bit
dm1con.dmasl_dm1con 1 Repeat transfer mode select bit
dm1con.dmas_dm1con 2 DMA request bit
dm1con.dmae_dm1con 3 DMA enable bit
dm1con.dsd_dm1con 4 Source address direction select bit
dm1con.dad_dm1con 5 Destination address direction select bit
int3ic 0x44 INT3~
int3ic.ilvl0_int3ic 0 Interrupt priority level select bit
int3ic.ilvl1_int3ic 1
int3ic.ilvl2_int3ic 2
int3ic.ir_int3ic 3 Interrupt request bit
int3ic.pol_int3ic 4 Polarity select bit
tb5ic 0x45 Timer B5
tb5ic.ilvl0_tb5ic 0 Interrupt priority level select bit
tb5ic.ilvl1_tb5ic 1
tb5ic.ilvl2_tb5ic 2
tb5ic.ir_tb5ic 3 Interrupt request bit
tb4ic 0x46 Timer B4
tb4ic.ilvl0_tb4ic 0 Interrupt priority level select bit
tb4ic.ilvl1_tb4ic 1
tb4ic.ilvl2_tb4ic 2
tb4ic.ir_tb4ic 3 Interrupt request bit
tb3ic 0x47 Timer B3
tb3ic.ilvl0_tb3ic 0 Interrupt priority level select bit
tb3ic.ilvl1_tb3ic 1
tb3ic.ilvl2_tb3ic 2
tb3ic.ir_tb3ic 3 Interrupt request bit
int5ic 0x48 INT5~
int5ic.ilvl0_int5ic 0 Interrupt priority level select bit
int5ic.ilvl1_int5ic 1
int5ic.ilvl2_int5ic 2
int5ic.ir_int5ic 3 Interrupt request bit
int5ic.pol_int5ic 4 Polarity select bit
int4ic 0x49 INT4~
int4ic.ilvl0_int4ic 0 Interrupt priority level select bit
int4ic.ilvl1_int4ic 1
int4ic.ilvl2_int4ic 2
int4ic.ir_int4ic 3 Interrupt request bit
int4ic.pol_int4ic 4 Polarity select bit
bcnic 0x4a Bus collision detection interrupt control register
bcnic.ilvl0_bcnic 0 Interrupt priority level select bit
bcnic.ilvl1_bcnic 1
bcnic.ilvl2_bcnic 2
bcnic.ir_bcnic 3 Interrupt request bit
dm0ic 0x4b DMA0 interrupt control register
dm0ic.ilvl0_dm0ic 0 Interrupt priority level select bit
dm0ic.ilvl1_dm0ic 1
dm0ic.ilvl2_dm0ic 2
dm0ic.ir_dm0ic 3 Interrupt request bit
dm1ic 0x4c DMA1 interrupt control register
dm1ic.ilvl0_dm1ic 0 Interrupt priority level select bit
dm1ic.ilvl1_dm1ic 1
dm1ic.ilvl2_dm1ic 2
dm1ic.ir_dm1ic 3 Interrupt request bit
kupic 0x4d Key input interrupt control register
kupic.ilvl0_kupic 0 Interrupt priority level select bit
kupic.ilvl1_kupic 1
kupic.ilvl2_kupic 2
kupic.ir_kupic 3 Interrupt request bit
adic 0x4e A/D interrupt control register
adic.ilvl0_adic 0 Interrupt priority level select bit
adic.ilvl1_adic 1
adic.ilvl2_adic 2
adic.ir_adic 3 Interrupt request bit
s2tic 0x4f UART2 transmit interrupt control register
s2tic.ilvl0_s2tic 0 Interrupt priority level select bit
s2tic.ilvl1_s2tic 1
s2tic.ilvl2_s2tic 2
s2tic.ir_s2tic 3 Interrupt request bit
s2ric 0x50 UART2 receive interrupt control register
s2ric.ilvl0_s2ric 0 Interrupt priority level select bit
s2ric.ilvl1_s2ric 1
s2ric.ilvl2_s2ric 2
s2ric.ir_s2ric 3 Interrupt request bit
s0tic 0x51 UART0 transmit interrupt control register
s0tic.ilvl0_s0tic 0 Interrupt priority level select bit
s0tic.ilvl1_s0tic 1
s0tic.ilvl2_s0tic 2
s0tic.ir_s0tic 3 Interrupt request bit
s0ric 0x52 UART0 receive interrupt control register
s0ric.ilvl0_s0ric 0 Interrupt priority level select bit
s0ric.ilvl1_s0ric 1
s0ric.ilvl2_s0ric 2
s0ric.ir_s0ric 3 Interrupt request bit
s1tic 0x53 UART1 transmit interrupt control register
s1tic.ilvl0_s1tic 0 Interrupt priority level select bit
s1tic.ilvl1_s1tic 1
s1tic.ilvl2_s1tic 2
s1tic.ir_s1tic 3 Interrupt request bit
s1ric 0x54 UART1 receive interrupt control register
s1ric.ilvl0_s1ric 0 Interrupt priority level select bit
s1ric.ilvl1_s1ric 1
s1ric.ilvl2_s1ric 2
s1ric.ir_s1ric 3 Interrupt request bit
ta0ic 0x55 Timer A0
ta0ic.ilvl0_ta0ic 0 Interrupt priority level select bit
ta0ic.ilvl1_ta0ic 1
ta0ic.ilvl2_ta0ic 2
ta0ic.ir_ta0ic 3 Interrupt request bit
ta1ic 0x56 Timer A1
ta1ic.ilvl0_ta1ic 0 Interrupt priority level select bit
ta1ic.ilvl1_ta1ic 1
ta1ic.ilvl2_ta1ic 2
ta1ic.ir_ta1ic 3 Interrupt request bit
ta2ic 0x57 Timer A2
ta2ic.ilvl0_ta2ic 0 Interrupt priority level select bit
ta2ic.ilvl1_ta2ic 1
ta2ic.ilvl2_ta2ic 2
ta2ic.ir_ta2ic 3 Interrupt request bit
ta3ic 0x58 Timer A3
ta3ic.ilvl0_ta3ic 0 Interrupt priority level select bit
ta3ic.ilvl1_ta3ic 1
ta3ic.ilvl2_ta3ic 2
ta3ic.ir_ta3ic 3 Interrupt request bit
ta4ic 0x59 Timer A4
ta4ic.ilvl0_ta4ic 0 Interrupt priority level select bit
ta4ic.ilvl1_ta4ic 1
ta4ic.ilvl2_ta4ic 2
ta4ic.ir_ta4ic 3 Interrupt request bit
tb0ic 0x5a Timer B0
tb0ic.ilvl0_tb0ic 0 Interrupt priority level select bit
tb0ic.ilvl1_tb0ic 1
tb0ic.ilvl2_tb0ic 2
tb0ic.ir_tb0ic 3 Interrupt request bit
tb1ic 0x5b Timer B1
tb1ic.ilvl0_tb1ic 0 Interrupt priority level select bit
tb1ic.ilvl1_tb1ic 1
tb1ic.ilvl2_tb1ic 2
tb1ic.ir_tb1ic 3 Interrupt request bit
tb2ic 0x5c Timer B2
tb2ic.ilvl0_tb2ic 0 Interrupt priority level select bit
tb2ic.ilvl1_tb2ic 1
tb2ic.ilvl2_tb2ic 2
tb2ic.ir_tb2ic 3 Interrupt request bit
int0ic 0x5d INT0~
int0ic.ilvl0_int0ic 0 Interrupt priority level select bit
int0ic.ilvl1_int0ic 1
int0ic.ilvl2_int0ic 2
int0ic.ir_int0ic 3 Interrupt request bit
int0ic.pol_int0ic 4 Polarity select bit
int1ic 0x5e INT1~
int1ic.ilvl0_int1ic 0 Interrupt priority level select bit
int1ic.ilvl1_int1ic 1
int1ic.ilvl2_int1ic 2
int1ic.ir_int1ic 3 Interrupt request bit
int1ic.pol_int1ic 4 Polarity select bit
int2ic 0x5f INT2~
int2ic.ilvl0_int2ic 0 Interrupt priority level select bit
int2ic.ilvl1_int2ic 1
int2ic.ilvl2_int2ic 2
int2ic.ir_int2ic 3 Interrupt request bit
int2ic.pol_int2ic 4 Polarity select bit
tbsr 0x340 Timer B3,B4,B5 count start flag
tbsr.tb3s 5
tbsr.tb4s 6
tbsr.tb5s 7
ta11 0x342 Timer A1-1
ta21 0x344 Timer A2-1
ta41 0x346 Timer A4-1
invc0 0x348 Three-phase PWM control register 0
invc0.inv00 0 Effective interrupt output polarity select bit
invc0.inv01 1 Effective interrupt output specification bit
invc0.inv02 2 Mode select bit
invc0.inv03 3 Output control bit
invc0.inv04 4 Positive and negative phases concurrent L output disable function enable bit
invc0.inv05 5 Positive and negative phases concurrent L output detect flag
invc0.inv06 6 Modulation mode select bit
invc0.inv07 7 Software trigger bit
invc1 0x349 Three-phase PWM control register 1
invc1.inv10 0 Timer Ai start trigger signal select bit
invc1.inv11 1 Timer A1-1,A2-1,A4-1 control bit
invc1.inv12 2 Short circuit timer count source select bit
idb0 0x34a Three-phase output buffer register 0
idb0.du0 0 U phase output buffer 0
idb0.dub0 1 U~ phase output buffer 0
idb0.dv0 2 V phase output buffer 0
idb0.dvb0 3 V~ phase output buffer 0
idb0.dw0 4 W phase output buffer 0
idb0.dwb0 5 W~ phase output buffer 0
idb1 0x34b Three-phase output buffer register 1
idb1.du1 0 U phase output buffer 1
idb1.dub1 1 U~ phase output buffer 1
idb1.dv1 2 V phase output buffer 1
idb1.dvb1 3 V~ phase output buffer 1
idb1.dw1 4 W phase output buffer 1
idb1.dwb1 5 W~ phase output buffer 1
dtt 0x34c Dead time timer
ictb2 0x34d Timer B2 interrupt occurrences frequency set counter
tb3 0x350 Timer B3
tb4 0x352 Timer B4
tb5 0x354 Timer B5
tb3mr 0x35b Timer mode registers B3
tb3mr.tmod0_tb3mr 0 Operation mode select bit
tb3mr.tmod1_tb3mr 1 Operation mode select bit
tb3mr.mr0_tb3mr 2
tb3mr.mr1_tb3mr 3
tb3mr.mr2_tb3mr 4
tb3mr.mr3_tb3mr 5
tb3mr.tck0_tb3mr 6 Count source select bit
tb3mr.tck1_tb3mr 7 Count source select bit
tb4mr 0x35c Timer mode registers B4
tb4mr.tmod0_tb4mr 0 Operation mode select bit
tb4mr.tmod1_tb4mr 1 Operation mode select bit
tb4mr.mr0_tb4mr 2
tb4mr.mr1_tb4mr 3
tb4mr.mr3_tb4mr 5
tb4mr.tck0_tb4mr 6 Count source select bit
tb4mr.tck1_tb4mr 7 Count source select bit
tb5mr 0x35d Timer mode registers B5
tb5mr.tmod0_tb5mr 0 Operation mode select bit
tb5mr.tmod1_tb5mr 1 Operation mode select bit
tb5mr.mr0_tb5mr 2
tb5mr.mr1_tb5mr 3
tb5mr.mr3_tb5mr 5
tb5mr.tck0_tb5mr 6 Count source select bit
tb5mr.tck1_tb5mr 7 Count source select bit
ifsr 0x35f Interrupt request cause select register
ifsr.ifsr0 0 INT0~ interrupt polarity switching bit
ifsr.ifsr1 1 INT1~ interrupt polarity switching bit
ifsr.ifsr2 2 INT2~ interrupt polarity switching bit
ifsr.ifsr3 3 INT3~ interrupt polarity switching bit
ifsr.ifsr4 4 INT4~ interrupt polarity switching bit
ifsr.ifsr5 5 INT5~ interrupt polarity switching bit
ifsr.ifsr6 6 Interrupt request cause select bit
ifsr.ifsr7 7 Interrupt request cause select bit
s3trr 0x360 SI/O3 transmit/receive register
s3c 0x362 SI/O3 control register
s3c.sm30 0 Internal synchronous clock select bit
s3c.sm31 1 Internal synchronous clock select bit
s3c.sm32 2 Sout3 output disable bit
s3c.sm33 3 SI/O3 port select bit
s3c.sm35 5 Transfer direction select bit
s3c.sm36 6 Synchronous clock select bit
s3c.sm37 7 Sout3 initial value set bit
s3brg 0x363 SI/O3 bit rate generator
s4trr 0x364 SI/O4 transmit/receive register
s4c 0x366 SI/O4 control register
s4c.sm40 0 Internal synchronous clock select bit
s4c.sm41 1 Internal synchronous clock select bit
s4c.sm42 2 Sout4 output disable bit
s4c.sm43 3 SI/O4 port select bit
s4c.sm45 5 Transfer direction select bit
s4c.sm46 6 Synchronous clock select bit
s4c.sm47 7 Sout4 initial value set bit
s4brg 0x367 SI/O4 bit rate generator
u2smr3 0x375 UART2 special mode register 3
u2smr3.dl0_u2smr3 5 SDA digital delay setup bit
u2smr3.dl1_u2smr3 6
u2smr3.dl2_u2smr3 7
u2smr2 0x376 UART2 special mode register 2
u2smr2.iicm2_u2smr2 0 IIC mode selection bit 2
u2smr2.csc_u2smr2 1 Clock-synchronous bit
u2smr2.swc_u2smr2 2 SCL wait output bit
u2smr2.als_u2smr2 3 SDA output stop bit
u2smr2.stac_u2smr2 4 UART2 initialization bit
u2smr2.swc2_u2smr2 5 SCL wait output bit 2
u2smr2.sdhi_u2smr2 6 SDA output disable bit
u2smr2.shtc_u2smr2 7 Start/stop condition control bit
u2smr 0x377 UART2 special mode register
u2smr.iicm_u2smr 0 IIC mode selection bit
u2smr.abc_u2smr 1 Arbitration lost detecting flag control bit
u2smr.bbs_u2smr 2 Bus busy flag
u2smr.lsyn_u2smr 3 SCLL sync output enable bit
u2smr.abscs_u2smr 4 Bus collision detect sampring clock select bit
u2smr.acse_u2smr 5 Auto clear function select bit of transmit enable bit
u2smr.sss_u2smr 6 Transmit start condition select bit
u2smr.sdds_u2smr 7 SDA digital delay select bit
u2mr 0x378 UART2 transmit/receive mode register
u2mr.smd0_u2mr 0 Serial I/O mode select bit
u2mr.smd1_u2mr 1
u2mr.smd2_u2mr 2
u2mr.ckdir_u2mr 3 Internal/external clock select bit
u2mr.stps_u2mr 4 Stop bit length select bit
u2mr.pry_u2mr 5 Odd/even parity select bit
u2mr.prye_u2mr 6 Parity enable bit
u2mr.iopol_u2mr 7 TxD,RxD I/O polarity reverse bit
u2brg 0x379 UART2 bit rate generator
u2tb 0x37a UART2 transmit buffer register L
u2tbh 0x37b UART2 transmit buffer register H
u2c0 0x37c UART2 transmit/receive control register 0
u2c0.clk0_u2c0 0 BRG count source select bit
u2c0.clk1_u2c0 1
u2c0.crs_u2c0 2 CTS~/RTS~ function select bit
u2c0.txept_u2c0 3 Transmit register empty flag
u2c0.crd_u2c0 4 CTS~/RTS~ disable bit
u2c0.ckpol_u2c0 6 CLK polarity select bit
u2c0.uform_u2c0 7 Transfer format select bit
u2c1 0x37d UART2 transmit/receive control register 1
u2c1.te_u2c1 0 Transmit enable bit
u2c1.ti_u2c1 1 Transmit buffer empty flag
u2c1.re_u2c1 2 Receive enable bit
u2c1.ri_u2c1 3 Receive complete flag
u2c1.u2irs 4 UART2 transmit interrupt cause select bit
u2c1.u2rrm 5 UART2 continuous receive mode enable bit
u2c1.u2lch 6 Data logic select bit
u2c1.u2ere 7 Error signal output enable bit
u2rb 0x37e UART2 receive buffer register L
u2rbh 0x37f UART2 receive buffer register H
u2rbh.abt_u2rb 3 Arbitrastion lost detecting flag
u2rbh.oer_u2rb 4 Overrun error flag
u2rbh.fer_u2rb 5 Framing error flag
u2rbh.per_u2rb 6 Parity error flag
u2rbh.sum_u2rb 7 Error sum flag
tabsr 0x380 Count start flag
tabsr.ta0s 0 Timer A0 count start flag
tabsr.ta1s 1 Timer A1 count start flag
tabsr.ta2s 2 Timer A2 count start flag
tabsr.ta3s 3 Timer A3 count start flag
tabsr.ta4s 4 Timer A4 count start flag
tabsr.tb0s 5 Timer B0 count start flag
tabsr.tb1s 6 Timer B1 count start flag
tabsr.tb2s 7 Timer B2 count start flag
cpsrf 0x381 Clock prescaler reset flag
cpsrf.cpsr 7 Clock prescaler reset flag
onsf 0x382 One-shot start flag
onsf.ta0os 0 Timer A0 one-shot start flag
onsf.ta1os 1 Timer A1 one-shot start flag
onsf.ta2os 2 Timer A2 one-shot start flag
onsf.ta3os 3 Timer A3 one-shot start flag
onsf.ta4os 4 Timer A4 one-shot start flag
onsf.ta0tgl 6 Timer A0 event/trigger select bit
onsf.ta0tgh 7
trgsr 0x383 Trigger select register
trgsr.ta1tgl 0 Timer A1 event/trigger select bit
trgsr.ta1tgh 1
trgsr.ta2tgl 2 Timer A2 event/trigger select bit
trgsr.ta2tgh 3
trgsr.ta3tgl 4 Timer A3 event/trigger select bit
trgsr.ta3tgh 5
trgsr.ta4tgl 6 Timer A4 event/trigger select bit
trgsr.ta4tgh 7
udf 0x384 Up/down flag
ta0 0x386 Timer A0
ta1 0x388 Timer A1
ta2 0x38a Timer A2
ta3 0x38c Timer A3
ta4 0x38e Timer A4
tb0 0x390 Timer B0
tb1 0x392 Timer B1
tb2 0x394 Timer B2
ta0mr 0x396 Timer A0 mode register
ta0mr.tmod0_ta0mr 0 Operation mode select bit
ta0mr.tmod1_ta0mr 1 Operation mode select bit
ta0mr.mr0_ta0mr 2
ta0mr.mr1_ta0mr 3
ta0mr.mr2_ta0mr 4
ta0mr.mr3_ta0mr 5
ta0mr.tck0_ta0mr 6 Count source select bit
ta0mr.tck1_ta0mr 7 Count source select bit
ta1mr 0x397 Timer A1 mode register
ta1mr.tmod0_ta1mr 0 Operation mode select bit
ta1mr.tmod1_ta1mr 1 Operation mode select bit
ta1mr.mr0_ta1mr 2
ta1mr.mr1_ta1mr 3
ta1mr.mr2_ta1mr 4
ta1mr.mr3_ta1mr 5
ta1mr.tck0_ta1mr 6 Count source select bit
ta1mr.tck1_ta1mr 7 Count source select bit
ta2mr 0x398 Timer A2 mode register
ta2mr.tmod0_ta2mr 0 Operation mode select bit
ta2mr.tmod1_ta2mr 1 Operation mode select bit
ta2mr.mr0_ta2mr 2
ta2mr.mr1_ta2mr 3
ta2mr.mr2_ta2mr 4
ta2mr.mr3_ta2mr 5
ta2mr.tck0_ta2mr 6 Count source select bit
ta2mr.tck1_ta2mr 7 Count source select bit
ta3mr 0x399 Timer A3 mode register
ta3mr.tmod0_ta3mr 0 Operation mode select bit
ta3mr.tmod1_ta3mr 1 Operation mode select bit
ta3mr.mr0_ta3mr 2
ta3mr.mr1_ta3mr 3
ta3mr.mr2_ta3mr 4
ta3mr.mr3_ta3mr 5
ta3mr.tck0_ta3mr 6 Count source select bit
ta3mr.tck1_ta3mr 7 Count source select bit
ta4mr 0x39a Timer A4 mode register
ta4mr.tmod0_ta4mr 0 Operation mode select bit
ta4mr.tmod1_ta4mr 1 Operation mode select bit
ta4mr.mr0_ta4mr 2
ta4mr.mr1_ta4mr 3
ta4mr.mr2_ta4mr 4
ta4mr.mr3_ta4mr 5
ta4mr.tck0_ta4mr 6 Count source select bit
ta4mr.tck1_ta4mr 7 Count source select bit
tb0mr 0x39b Timer B0 mode register
tb0mr.tmod0_tb0mr 0 Operation mode select bit
tb0mr.tmod1_tb0mr 1 Operation mode select bit
tb0mr.mr0_tb0mr 2
tb0mr.mr1_tb0mr 3
tb0mr.mr2_tb0mr 4
tb0mr.mr3_tb0mr 5
tb0mr.tck0_tb0mr 6 Count source select bit
tb0mr.tck1_tb0mr 7 Count source select bit
tb1mr 0x39c Timer B1 mode register
tb1mr.tmod0_tb1mr 0 Operation mode select bit
tb1mr.tmod1_tb1mr 1 Operation mode select bit
tb1mr.mr0_tb1mr 2
tb1mr.mr1_tb1mr 3
tb1mr.mr3_tb1mr 5
tb1mr.tck0_tb1mr 6 Count source select bit
tb1mr.tck1_tb1mr 7 Count source select bit
tb2mr 0x39d Timer B2 mode register
tb2mr.tmod0_tb2mr 0 Operation mode select bit
tb2mr.tmod1_tb2mr 1 Operation mode select bit
tb2mr.mr0_tb2mr 2
tb2mr.mr1_tb2mr 3
tb2mr.mr3_tb2mr 5
tb2mr.tck0_tb2mr 6 Count source select bit
tb2mr.tck1_tb2mr 7 Count source select bit
u0mr 0x3a0 UART0 transmit/receive mode register
u0mr.smd0_u0mr 0 Serial I/O mode select bit
u0mr.smd1_u0mr 1
u0mr.smd2_u0mr 2
u0mr.ckdir_u0mr 3 Internal/external clock select bit
u0mr.stps_u0mr 4 Stop bit length select bit
u0mr.pry_u0mr 5 Odd/even parity select bit
u0mr.prye_u0mr 6 Parity enable bit
u0mr.slep_u0mr 7 Sleep select bit
u0brg 0x3a1 UART0 bit rate generator
u0tb 0x3a2 UART0 transmit buffer register L
u0tbh 0x3a3 UART0 transmit buffer register H
u0c0 0x3a4 UART0 transmit/receive control register 0
u0c0.clk0_u0c0 0 BRG count source select bit
u0c0.clk1_u0c0 1
u0c0.crs_u0c0 2 CTS~/RTS~ function select bit
u0c0.txept_u0c0 3 Transmit register empty flag
u0c0.crd_u0c0 4 CTS~/RTS~ disable bit
u0c0.nch_u0c0 5 Data output select bit
u0c0.ckpol_u0c0 6 CLK polarity select bit
u0c0.uform_u0c0 7 Transfer format select bit
u0c1 0x3a5 UART0 transmit/receive control register 1
u0c1.te_u0c1 0 Transmit enable bit
u0c1.ti_u0c1 1 Transmit buffer empty flag
u0c1.re_u0c1 2 Receive enable bit
u0c1.ri_u0c1 3 Receive complete flag
u0rb 0x3a6 UART0 receive buffer register L
u0rbh 0x3a7 UART0 receive buffer register H
u0rbh.oer_u0rb 4 Overrun error flag
u0rbh.fer_u0rb 5 Framing error flag
u0rbh.per_u0rb 6 Parity error flag
u0rbh.sum_u0rb 7 Error sum flag
u1mr 0x3a8 UART1 transmit/receive mode register
u1mr.smd0_u1mr 0 Serial I/O mode select bit
u1mr.smd1_u1mr 1
u1mr.smd2_u1mr 2
u1mr.ckdir_u1mr 3 Internal/external clock select bit
u1mr.stps_u1mr 4 Stop bit length select bit
u1mr.pry_u1mr 5 Odd/even parity select bit
u1mr.prye_u1mr 6 Parity enable bit
u1mr.slep_u1mr 7 Sleep select bit
u1brg 0x3a9 UART1 bit rate generator
u1tb 0x3aa UART1 transmit buffer register L
u1tbh 0x3ab UART1 transmit buffer register H
u1c0 0x3ac UART1 transmit/receive control register 0
u1c0.clk0_u1c0 0 BRG count source select bit
u1c0.clk1_u1c0 1
u1c0.crs_u1c0 2 CTS~/RTS~ function select bit
u1c0.txept_u1c0 3 Transmit register empty flag
u1c0.crd_u1c0 4 CTS~/RTS~ disable bit
u1c0.nch_u1c0 5 Data output select bit
u1c0.ckpol_u1c0 6 CLK polarity select bit
u1c0.uform_u1c0 7 Transfer format select bit
u1c1 0x3ad UART1 transmit/receive control register 1
u1c1.te_u1c1 0 Transmit enable bit
u1c1.ti_u1c1 1 Transmit buffer empty flag
u1c1.re_u1c1 2 Receive enable bit
u1c1.ri_u1c1 3 Receive complete flag
u1rb 0x3ae UART1 receive register L
u1rbh 0x3af UART1 receive register H
u1rbh.oer_u1rb 4 Overrun error flag
u1rbh.fer_u1rb 5 Framing error flag
u1rbh.per_u1rb 6 Parity error flag
u1rbh.sum_u1rb 7 Error sum flag
ucon 0x3b0 UART transmit/receive control register 2
ucon.u0irs 0 UART0 transmit interrupt cause select bit
ucon.u1irs 1 UART1 transmit interrupt cause select bit
ucon.u0rrm 2 UART0 continuous receive mode enable bit
ucon.u1rrm 3 UART1 continuous receive mode enable bit
ucon.clkmd0 4 CLK/CLKS select bit 0
ucon.clkmd1 5 CLK/CLKS select bit 1
fmr1 0x3b6 Flash memory control register 1
fmr1.fmr13 3 Flash memory power supply-OFF bit
fmr0 0x3b7 Flash memory control register 0
fmr0.fmr00 0 RY/BY~ status bit
fmr0.fmr01 1 CPU rewrite mode select bit
fmr0.fmr02 2 Lock bit disable bit
fmr0.fmr03 3 Flash memory reset bit
fmr0.fmr05 5 User ROM area select bit
dm0sl 0x3b8 DMA0 request cause select register
dm0sl.dsel0_dm0sl 0 DMA request cause select bit
dm0sl.dsel1_dm0sl 1
dm0sl.dsel2_dm0sl 2
dm0sl.dsel3_dm0sl 3
dm0sl.dms_dm0sl 6 DMA request cause expansion bit
dm0sl.dsr_dm0sl 7 Software DMA request bit
dm1sl 0x3ba DMA1 request cause select register
dm1sl.dsel0_dm1sl 0 DMA request cause select bit
dm1sl.dsel1_dm1sl 1
dm1sl.dsel2_dm1sl 2
dm1sl.dsel3_dm1sl 3
dm1sl.dms_dm1sl 6 DMA request cause expansion bit
dm1sl.dsr_dm1sl 7 Software DMA request bit
crcd 0x3bc CRC data register L
crcdh 0x3bd CRC data register H
crcin 0x3be CRC input register
ad0 0x3c0 A/D register 0 L
ad0h 0x3c1 A/D register 0 H
ad1 0x3c2 A/D register 1 L
ad1h 0x3c3 A/D register 1 H
ad2 0x3c4 A/D register 2 L
ad2h 0x3c5 A/D register 2 H
ad3 0x3c6 A/D register 3 L
ad3h 0x3c7 A/D register 3 H
ad4 0x3c8 A/D register 4 L
ad4h 0x3c9 A/D register 4 H
ad5 0x3ca A/D register 5 L
ad5h 0x3cb A/D register 5 H
ad6 0x3cc A/D register 6 L
ad6h 0x3cd A/D register 6 H
ad7 0x3ce A/D register 7 L
ad7h 0x3cf A/D register 7 H
adcon2 0x3d4 A/D control register 2
adcon2.smp 0 A/D conversion method select bit
adcon0 0x3d6 A/D control register 0
adcon0.ch0 0 Analog input pin select bit
adcon0.ch1 1
adcon0.ch2 2
adcon0.md0 3 A/D operation mode select bit 0
adcon0.md1 4
adcon0.trg 5 Trigger select bit
adcon0.adst 6 A/D conversion start flag
adcon0.cks0 7 Frequency select bit 0
adcon1 0x3d7 A/D control register 1
adcon1.scan0 0 A/D sweep pin select bit
adcon1.scan1 1
adcon1.md2 2 A/D operation mode select bit 1
adcon1.bits 3 8/10-bit mode select bit
adcon1.cks1 4 Frequency select bit 1
adcon1.vcut 5 Vref connect bit
adcon1.opa0 6 External op-amp connection mode bit
adcon1.opa1 7
da0 0x3d8 D/A register 0
da1 0x3da D/A register 1
dacon 0x3dc D/A control register
dacon.da0e 0 D/A0 output enable bit
dacon.da1e 1 D/A1 output enable bit
p0 0x3e0 Port P0 register
p0.p0_0 0
p0.p0_1 1
p0.p0_2 2
p0.p0_3 3
p0.p0_4 4
p0.p0_5 5
p0.p0_6 6
p0.p0_7 7
p1 0x3e1 Port P1 register
p1.p1_0 0
p1.p1_1 1
p1.p1_2 2
p1.p1_3 3
p1.p1_4 4
p1.p1_5 5
p1.p1_6 6
p1.p1_7 7
pd0 0x3e2 Port P0 direction register
pd0.pd0_0 0
pd0.pd0_1 1
pd0.pd0_2 2
pd0.pd0_3 3
pd0.pd0_4 4
pd0.pd0_5 5
pd0.pd0_6 6
pd0.pd0_7 7
pd1 0x3e3 Port P1 direction register
pd1.pd1_0 0
pd1.pd1_1 1
pd1.pd1_2 2
pd1.pd1_3 3
pd1.pd1_4 4
pd1.pd1_5 5
pd1.pd1_6 6
pd1.pd1_7 7
p2 0x3e4 Port P2 register
p2.p2_0 0
p2.p2_1 1
p2.p2_2 2
p2.p2_3 3
p2.p2_4 4
p2.p2_5 5
p2.p2_6 6
p2.p2_7 7
p3 0x3e5 Port P3 register
p3.p3_0 0
p3.p3_1 1
p3.p3_2 2
p3.p3_3 3
p3.p3_4 4
p3.p3_5 5
p3.p3_6 6
p3.p3_7 7
pd2 0x3e6 Port P2 direction register
pd2.pd2_0 0
pd2.pd2_1 1
pd2.pd2_2 2
pd2.pd2_3 3
pd2.pd2_4 4
pd2.pd2_5 5
pd2.pd2_6 6
pd2.pd2_7 7
pd3 0x3e7 Port P3 direction register
pd3.pd3_0 0
pd3.pd3_1 1
pd3.pd3_2 2
pd3.pd3_3 3
pd3.pd3_4 4
pd3.pd3_5 5
pd3.pd3_6 6
pd3.pd3_7 7
p4 0x3e8 Port P4 register
p4.p4_0 0
p4.p4_1 1
p4.p4_2 2
p4.p4_3 3
p4.p4_4 4
p4.p4_5 5
p4.p4_6 6
p4.p4_7 7
p5 0x3e9 Port P5 register
p5.p5_0 0
p5.p5_1 1
p5.p5_2 2
p5.p5_3 3
p5.p5_4 4
p5.p5_5 5
p5.p5_6 6
p5.p5_7 7
pd4 0x3ea Port P4 direction register
pd4.pd4_0 0
pd4.pd4_1 1
pd4.pd4_2 2
pd4.pd4_3 3
pd4.pd4_4 4
pd4.pd4_5 5
pd4.pd4_6 6
pd4.pd4_7 7
pd5 0x3eb Port P5 direction register
pd5.pd5_0 0
pd5.pd5_1 1
pd5.pd5_2 2
pd5.pd5_3 3
pd5.pd5_4 4
pd5.pd5_5 5
pd5.pd5_6 6
pd5.pd5_7 7
p6 0x3ec Port P6 register
p6.p6_0 0
p6.p6_1 1
p6.p6_2 2
p6.p6_3 3
p6.p6_4 4
p6.p6_5 5
p6.p6_6 6
p6.p6_7 7
p7 0x3ed Port P7 register
p7.p7_0 0
p7.p7_1 1
p7.p7_2 2
p7.p7_3 3
p7.p7_4 4
p7.p7_5 5
p7.p7_6 6
p7.p7_7 7
pd6 0x3ee Port P6 direction register
pd6.pd6_0 0
pd6.pd6_1 1
pd6.pd6_2 2
pd6.pd6_3 3
pd6.pd6_4 4
pd6.pd6_5 5
pd6.pd6_6 6
pd6.pd6_7 7
pd7 0x3ef Port P7 direction register
pd7.pd7_0 0
pd7.pd7_1 1
pd7.pd7_2 2
pd7.pd7_3 3
pd7.pd7_4 4
pd7.pd7_5 5
pd7.pd7_6 6
pd7.pd7_7 7
p8 0x3f0 Port P8 register
p8.p8_0 0
p8.p8_1 1
p8.p8_2 2
p8.p8_3 3
p8.p8_4 4
p8.p8_5 5
p8.p8_6 6
p8.p8_7 7
p9 0x3f1 Port P9 register
p9.p9_0 0
p9.p9_1 1
p9.p9_2 2
p9.p9_3 3
p9.p9_4 4
p9.p9_5 5
p9.p9_6 6
p9.p9_7 7
pd8 0x3f2 Port P8 direction register
pd8.pd8_0 0
pd8.pd8_1 1
pd8.pd8_2 2
pd8.pd8_3 3
pd8.pd8_4 4
pd8.pd8_6 6
pd8.pd8_7 7
pd9 0x3f3 Port P9 direction register
pd9.pd9_0 0
pd9.pd9_1 1
pd9.pd9_2 2
pd9.pd9_3 3
pd9.pd9_4 4
pd9.pd9_5 5
pd9.pd9_6 6
pd9.pd9_7 7
p10 0x3f4 Port P10 register
p10.p10_0 0
p10.p10_1 1
p10.p10_2 2
p10.p10_3 3
p10.p10_4 4
p10.p10_5 5
p10.p10_6 6
p10.p10_7 7
pd10 0x3f6 Port P10 direction register
pd10.pd10_0 0
pd10.pd10_1 1
pd10.pd10_2 2
pd10.pd10_3 3
pd10.pd10_4 4
pd10.pd10_5 5
pd10.pd10_6 6
pd10.pd10_7 7
pur0 0x3fc Pull-up control register 0
pur0.pu00 0 P00 to P03 pull-up
pur0.pu01 1 P04 to P07 pull-up
pur0.pu02 2 P10 to P13 pull-up
pur0.pu03 3 P14 to P17 pull-up
pur0.pu04 4 P20 to P23 pull-up
pur0.pu05 5 P24 to P27 pull-up
pur0.pu06 6 P30 to P33 pull-up
pur0.pu07 7 P34 to P37 pull-up
pur1 0x3fd Pull-up control register 1
pur1.pu10 0 P40 to P43 pull-up
pur1.pu11 1 P44 to P47 pull-up
pur1.pu12 2 P50 to P53 pull-up
pur1.pu13 3 P54 to P57 pull-up
pur1.pu14 4 P60 to P63 pull-up
pur1.pu15 5 P64 to P67 pull-up
pur1.pu16 6 P70 to P73 pull-up (Except P70,P71
pur1.pu17 7 P74 to P77 pull-up
pur2 0x3fe Pull-up control register 2
pur2.pu20 0 P80 to P83 pull-up
pur2.pu21 1 P84 to P87 pull-up (Except P85)
pur2.pu22 2 P90 to P93 pull-up
pur2.pu23 3 P94 to P97 pull-up
pur2.pu24 4 P100 to P103 pull-up
pur2.pu25 5 P104 to P107 pull-up
pcr 0x3ff Port control register
pcr.pcr0 0 Port P1 control register