// Shortcuts for ARM64 system registers
// generated from arm_sys_reg.cfg

#ifndef ARM64_SYSREG
  #define ARM64_SYSREG(op0, op1, crn, crm, op2) \
            ( ((op0 &  1) << 14) \
            | ((op1 &  7) << 11) \
            | ((crn & 15) <<  7) \
            | ((crm & 15) <<  3) \
            | ((op2 &  7) <<  0) )
#endif

#define UAOIMM ARM64_SYSREG(0, 0, 4, 0, 3)
#define PANIMM ARM64_SYSREG(0, 0, 4, 0, 4)
#define SPSELIMM ARM64_SYSREG(0, 0, 4, 0, 5)
#define SSBSIMM ARM64_SYSREG(0, 3, 4, 0, 1)
#define DITIMM ARM64_SYSREG(0, 3, 4, 0, 2)
#define DAIFSET ARM64_SYSREG(0, 3, 4, 0, 6)
#define DAIFCLR ARM64_SYSREG(0, 3, 4, 0, 7)
#define OSDTRRX_EL1 ARM64_SYSREG(2, 0, 0, 0, 2)
#define MDCCINT_EL1 ARM64_SYSREG(2, 0, 0, 2, 0)
#define MDSCR_EL1 ARM64_SYSREG(2, 0, 0, 2, 2)
#define OSDTRTX_EL1 ARM64_SYSREG(2, 0, 0, 3, 2)
#define MDSELR_EL1 ARM64_SYSREG(2, 0, 0, 4, 2)
#define MDSTEPOP_EL1 ARM64_SYSREG(2, 0, 0, 5, 2)
#define DBGWFAR ARM64_SYSREG(2, 0, 0, 6, 0)
#define OSECCR_EL1 ARM64_SYSREG(2, 0, 0, 6, 2)
#define MDRAR_EL1 ARM64_SYSREG(2, 0, 1, 0, 0)
#define OSLAR_EL1 ARM64_SYSREG(2, 0, 1, 0, 4)
#define OSLSR_EL1 ARM64_SYSREG(2, 0, 1, 1, 4)
#define OSDLR_EL1 ARM64_SYSREG(2, 0, 1, 3, 4)
#define DBGPRCR_EL1 ARM64_SYSREG(2, 0, 1, 4, 4)
#define DBGCLAIMSET_EL1 ARM64_SYSREG(2, 0, 7, 8, 6)
#define DBGCLAIMCLR_EL1 ARM64_SYSREG(2, 0, 7, 9, 6)
#define DBGAUTHSTATUS_EL1 ARM64_SYSREG(2, 0, 7, 14, 6)
#define SPMACCESSR_EL1 ARM64_SYSREG(2, 0, 9, 13, 3)
#define SPMIIDR_EL1 ARM64_SYSREG(2, 0, 9, 13, 4)
#define SPMDEVARCH_EL1 ARM64_SYSREG(2, 0, 9, 13, 5)
#define SPMDEVAFF_EL1 ARM64_SYSREG(2, 0, 9, 13, 6)
#define SPMCFGR_EL1 ARM64_SYSREG(2, 0, 9, 13, 7)
#define SPMINTENSET_EL1 ARM64_SYSREG(2, 0, 9, 14, 1)
#define SPMINTENCLR_EL1 ARM64_SYSREG(2, 0, 9, 14, 2)
#define PMCCNTSVR_EL1 ARM64_SYSREG(2, 0, 14, 11, 7)
#define PMICNTSVR_EL1 ARM64_SYSREG(2, 0, 14, 12, 0)
#define TRCTRACEIDR ARM64_SYSREG(2, 1, 0, 0, 1)
#define TRCVICTLR ARM64_SYSREG(2, 1, 0, 0, 2)
#define TRCIDR8 ARM64_SYSREG(2, 1, 0, 0, 6)
#define TRCIMSPEC0 ARM64_SYSREG(2, 1, 0, 0, 7)
#define TRCPRGCTLR ARM64_SYSREG(2, 1, 0, 1, 0)
#define TRCQCTLR ARM64_SYSREG(2, 1, 0, 1, 1)
#define TRCVIIECTLR ARM64_SYSREG(2, 1, 0, 1, 2)
#define TRCIDR9 ARM64_SYSREG(2, 1, 0, 1, 6)
#define TRCITEEDCR ARM64_SYSREG(2, 1, 0, 2, 1)
#define TRCVISSCTLR ARM64_SYSREG(2, 1, 0, 2, 2)
#define TRCIDR10 ARM64_SYSREG(2, 1, 0, 2, 6)
#define TRCSTATR ARM64_SYSREG(2, 1, 0, 3, 0)
#define TRCVIPCSSCTLR ARM64_SYSREG(2, 1, 0, 3, 2)
#define TRCIDR11 ARM64_SYSREG(2, 1, 0, 3, 6)
#define TRCCONFIGR ARM64_SYSREG(2, 1, 0, 4, 0)
#define TRCIDR12 ARM64_SYSREG(2, 1, 0, 4, 6)
#define TRCIDR13 ARM64_SYSREG(2, 1, 0, 5, 6)
#define TRCAUXCTLR ARM64_SYSREG(2, 1, 0, 6, 0)
#define TRCSEQRSTEVR ARM64_SYSREG(2, 1, 0, 6, 4)
#define TRCSEQSTR ARM64_SYSREG(2, 1, 0, 7, 4)
#define TRCEVENTCTL0R ARM64_SYSREG(2, 1, 0, 8, 0)
#define TRCIDR0 ARM64_SYSREG(2, 1, 0, 8, 7)
#define TRCEVENTCTL1R ARM64_SYSREG(2, 1, 0, 9, 0)
#define TRCIDR1 ARM64_SYSREG(2, 1, 0, 9, 7)
#define TRCRSR ARM64_SYSREG(2, 1, 0, 10, 0)
#define TRCIDR2 ARM64_SYSREG(2, 1, 0, 10, 7)
#define TRCSTALLCTLR ARM64_SYSREG(2, 1, 0, 11, 0)
#define TRCIDR3 ARM64_SYSREG(2, 1, 0, 11, 7)
#define TRCTSCTLR ARM64_SYSREG(2, 1, 0, 12, 0)
#define TRCIDR4 ARM64_SYSREG(2, 1, 0, 12, 7)
#define TRCSYNCPR ARM64_SYSREG(2, 1, 0, 13, 0)
#define TRCIDR5 ARM64_SYSREG(2, 1, 0, 13, 7)
#define TRCCCCTLR ARM64_SYSREG(2, 1, 0, 14, 0)
#define TRCIDR6 ARM64_SYSREG(2, 1, 0, 14, 7)
#define TRCBBCTLR ARM64_SYSREG(2, 1, 0, 15, 0)
#define TRCIDR7 ARM64_SYSREG(2, 1, 0, 15, 7)
#define TRCOSLSR ARM64_SYSREG(2, 1, 1, 1, 4)
#define TRCCIDCCTLR0 ARM64_SYSREG(2, 1, 3, 0, 2)
#define TRCCIDCCTLR1 ARM64_SYSREG(2, 1, 3, 1, 2)
#define TRCVMIDCCTLR0 ARM64_SYSREG(2, 1, 3, 2, 2)
#define TRCVMIDCCTLR1 ARM64_SYSREG(2, 1, 3, 3, 2)
#define TRCDEVID ARM64_SYSREG(2, 1, 7, 2, 7)
#define TRCCLAIMSET ARM64_SYSREG(2, 1, 7, 8, 6)
#define TRCCLAIMCLR ARM64_SYSREG(2, 1, 7, 9, 6)
#define TRCAUTHSTATUS ARM64_SYSREG(2, 1, 7, 14, 6)
#define TRCDEVARCH ARM64_SYSREG(2, 1, 7, 15, 6)
#define BRBCR_EL1 ARM64_SYSREG(2, 1, 9, 0, 0)
#define BRBFCR_EL1 ARM64_SYSREG(2, 1, 9, 0, 1)
#define BRBTS_EL1 ARM64_SYSREG(2, 1, 9, 0, 2)
#define BRBINFINJ_EL1 ARM64_SYSREG(2, 1, 9, 1, 0)
#define BRBSRCINJ_EL1 ARM64_SYSREG(2, 1, 9, 1, 1)
#define BRBTGTINJ_EL1 ARM64_SYSREG(2, 1, 9, 1, 2)
#define BRBIDR0_EL1 ARM64_SYSREG(2, 1, 9, 2, 0)
#define TEECR32_EL1 ARM64_SYSREG(2, 2, 0, 0, 0)
#define TEEHBR32_EL1 ARM64_SYSREG(2, 2, 1, 0, 0)
#define MDCCSR_EL0 ARM64_SYSREG(2, 3, 0, 1, 0)
#define DBGDTR_EL0 ARM64_SYSREG(2, 3, 0, 4, 0)
#define DBGDTRRX_EL0 ARM64_SYSREG(2, 3, 0, 5, 0)
#define DBGDTRTX_EL0 ARM64_SYSREG(2, 3, 0, 5, 0)
#define SPMCR_EL0 ARM64_SYSREG(2, 3, 9, 12, 0)
#define SPMCNTENSET_EL0 ARM64_SYSREG(2, 3, 9, 12, 1)
#define SPMCNTENCLR_EL0 ARM64_SYSREG(2, 3, 9, 12, 2)
#define SPMOVSCLR_EL0 ARM64_SYSREG(2, 3, 9, 12, 3)
#define SPMZR_EL0 ARM64_SYSREG(2, 3, 9, 12, 4)
#define SPMSELR_EL0 ARM64_SYSREG(2, 3, 9, 12, 5)
#define SPMOVSSET_EL0 ARM64_SYSREG(2, 3, 9, 14, 3)
#define DBGVCR32_EL2 ARM64_SYSREG(2, 4, 0, 7, 0)
#define BRBCR_EL2 ARM64_SYSREG(2, 4, 9, 0, 0)
#define SPMACCESSR_EL2 ARM64_SYSREG(2, 4, 9, 13, 3)
#define BRBCR_EL12 ARM64_SYSREG(2, 5, 9, 0, 0)
#define SPMACCESSR_EL12 ARM64_SYSREG(2, 5, 9, 13, 3)
#define SPMACCESSR_EL3 ARM64_SYSREG(2, 6, 9, 13, 3)
#define SPMROOTCR_EL3 ARM64_SYSREG(2, 6, 9, 14, 7)
#define SPMSCR_EL1 ARM64_SYSREG(2, 7, 9, 14, 7)
#define MIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 0)
#define MPIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 5)
#define REVIDR_EL1 ARM64_SYSREG(3, 0, 0, 0, 6)
#define ID_PFR0_EL1 ARM64_SYSREG(3, 0, 0, 1, 0)
#define ID_PFR1_EL1 ARM64_SYSREG(3, 0, 0, 1, 1)
#define ID_DFR0_EL1 ARM64_SYSREG(3, 0, 0, 1, 2)
#define ID_AFR0_EL1 ARM64_SYSREG(3, 0, 0, 1, 3)
#define ID_MMFR0_EL1 ARM64_SYSREG(3, 0, 0, 1, 4)
#define ID_MMFR1_EL1 ARM64_SYSREG(3, 0, 0, 1, 5)
#define ID_MMFR2_EL1 ARM64_SYSREG(3, 0, 0, 1, 6)
#define ID_MMFR3_EL1 ARM64_SYSREG(3, 0, 0, 1, 7)
#define ID_ISAR0_EL1 ARM64_SYSREG(3, 0, 0, 2, 0)
#define ID_ISAR1_EL1 ARM64_SYSREG(3, 0, 0, 2, 1)
#define ID_ISAR2_EL1 ARM64_SYSREG(3, 0, 0, 2, 2)
#define ID_ISAR3_EL1 ARM64_SYSREG(3, 0, 0, 2, 3)
#define ID_ISAR4_EL1 ARM64_SYSREG(3, 0, 0, 2, 4)
#define ID_ISAR5_EL1 ARM64_SYSREG(3, 0, 0, 2, 5)
#define ID_MMFR4_EL1 ARM64_SYSREG(3, 0, 0, 2, 6)
#define ID_ISAR6_EL1 ARM64_SYSREG(3, 0, 0, 2, 7)
#define MVFR0_EL1 ARM64_SYSREG(3, 0, 0, 3, 0)
#define MVFR1_EL1 ARM64_SYSREG(3, 0, 0, 3, 1)
#define MVFR2_EL1 ARM64_SYSREG(3, 0, 0, 3, 2)
#define ID_AA32RES3_EL1 ARM64_SYSREG(3, 0, 0, 3, 3)
#define ID_PFR2_EL1 ARM64_SYSREG(3, 0, 0, 3, 4)
#define ID_DFR1_EL1 ARM64_SYSREG(3, 0, 0, 3, 5)
#define ID_MMFR5_EL1 ARM64_SYSREG(3, 0, 0, 3, 6)
#define ID_AA32RES7_EL1 ARM64_SYSREG(3, 0, 0, 3, 7)
#define ID_AA64PFR0_EL1 ARM64_SYSREG(3, 0, 0, 4, 0)
#define ID_AA64PFR1_EL1 ARM64_SYSREG(3, 0, 0, 4, 1)
#define ID_AA64PFR2_EL1 ARM64_SYSREG(3, 0, 0, 4, 2)
#define ID_AA64PFR3_EL1 ARM64_SYSREG(3, 0, 0, 4, 3)
#define ID_AA64ZFR0_EL1 ARM64_SYSREG(3, 0, 0, 4, 4)
#define ID_AA64SMFR0_EL1 ARM64_SYSREG(3, 0, 0, 4, 5)
#define ID_AA64ZFR2_EL1 ARM64_SYSREG(3, 0, 0, 4, 6)
#define ID_AA64FPFR0_EL1 ARM64_SYSREG(3, 0, 0, 4, 7)
#define ID_AA64DFR0_EL1 ARM64_SYSREG(3, 0, 0, 5, 0)
#define ID_AA64DFR1_EL1 ARM64_SYSREG(3, 0, 0, 5, 1)
#define ID_AA64DFR2_EL1 ARM64_SYSREG(3, 0, 0, 5, 2)
#define ID_AA64DFR3_EL1 ARM64_SYSREG(3, 0, 0, 5, 3)
#define ID_AA64AFR0_EL1 ARM64_SYSREG(3, 0, 0, 5, 4)
#define ID_AA64AFR1_EL1 ARM64_SYSREG(3, 0, 0, 5, 5)
#define ID_AA64AFR2_EL1 ARM64_SYSREG(3, 0, 0, 5, 6)
#define ID_AA64AFR3_EL1 ARM64_SYSREG(3, 0, 0, 5, 7)
#define ID_AA64ISAR0_EL1 ARM64_SYSREG(3, 0, 0, 6, 0)
#define ID_AA64ISAR1_EL1 ARM64_SYSREG(3, 0, 0, 6, 1)
#define ID_AA64ISAR2_EL1 ARM64_SYSREG(3, 0, 0, 6, 2)
#define ID_AA64ISAR3_EL1 ARM64_SYSREG(3, 0, 0, 6, 3)
#define ID_AA64ISAR4_EL1 ARM64_SYSREG(3, 0, 0, 6, 4)
#define ID_AA64ISAR5_EL1 ARM64_SYSREG(3, 0, 0, 6, 5)
#define ID_AA64ISAR6_EL1 ARM64_SYSREG(3, 0, 0, 6, 6)
#define ID_AA64ISAR7_EL1 ARM64_SYSREG(3, 0, 0, 6, 7)
#define ID_AA64MMFR0_EL1 ARM64_SYSREG(3, 0, 0, 7, 0)
#define ID_AA64MMFR1_EL1 ARM64_SYSREG(3, 0, 0, 7, 1)
#define ID_AA64MMFR2_EL1 ARM64_SYSREG(3, 0, 0, 7, 2)
#define ID_AA64MMFR3_EL1 ARM64_SYSREG(3, 0, 0, 7, 3)
#define ID_AA64MMFR4_EL1 ARM64_SYSREG(3, 0, 0, 7, 4)
#define ID_AA64MMFR5_EL1 ARM64_SYSREG(3, 0, 0, 7, 5)
#define ID_AA64MMFR6_EL1 ARM64_SYSREG(3, 0, 0, 7, 6)
#define ID_AA64MMFR7_EL1 ARM64_SYSREG(3, 0, 0, 7, 7)
#define SCTLR_EL1 ARM64_SYSREG(3, 0, 1, 0, 0)
#define ACTLR_EL1 ARM64_SYSREG(3, 0, 1, 0, 1)
#define CPACR_EL1 ARM64_SYSREG(3, 0, 1, 0, 2)
#define SCTLR2_EL1 ARM64_SYSREG(3, 0, 1, 0, 3)
#define RGSR_EL1 ARM64_SYSREG(3, 0, 1, 0, 5)
#define GCR_EL1 ARM64_SYSREG(3, 0, 1, 0, 6)
#define ZCR_EL1 ARM64_SYSREG(3, 0, 1, 2, 0)
#define TRFCR_EL1 ARM64_SYSREG(3, 0, 1, 2, 1)
#define TRCITECR_EL1 ARM64_SYSREG(3, 0, 1, 2, 3)
#define SMPRI_EL1 ARM64_SYSREG(3, 0, 1, 2, 4)
#define SMCR_EL1 ARM64_SYSREG(3, 0, 1, 2, 6)
#define TTBR0_EL1 ARM64_SYSREG(3, 0, 2, 0, 0)
#define TTBR1_EL1 ARM64_SYSREG(3, 0, 2, 0, 1)
#define TCR_EL1 ARM64_SYSREG(3, 0, 2, 0, 2)
#define TCR2_EL1 ARM64_SYSREG(3, 0, 2, 0, 3)
#define APIAKeyLo_EL1 ARM64_SYSREG(3, 0, 2, 1, 0)
#define APIAKeyHi_EL1 ARM64_SYSREG(3, 0, 2, 1, 1)
#define APIBKeyLo_EL1 ARM64_SYSREG(3, 0, 2, 1, 2)
#define APIBKeyHi_EL1 ARM64_SYSREG(3, 0, 2, 1, 3)
#define APDAKeyLo_EL1 ARM64_SYSREG(3, 0, 2, 2, 0)
#define APDAKeyHi_EL1 ARM64_SYSREG(3, 0, 2, 2, 1)
#define APDBKeyLo_EL1 ARM64_SYSREG(3, 0, 2, 2, 2)
#define APDBKeyHi_EL1 ARM64_SYSREG(3, 0, 2, 2, 3)
#define APGAKeyLo_EL1 ARM64_SYSREG(3, 0, 2, 3, 0)
#define APGAKeyHi_EL1 ARM64_SYSREG(3, 0, 2, 3, 1)
#define GCSCR_EL1 ARM64_SYSREG(3, 0, 2, 5, 0)
#define GCSPR_EL1 ARM64_SYSREG(3, 0, 2, 5, 1)
#define GCSCRE0_EL1 ARM64_SYSREG(3, 0, 2, 5, 2)
#define SPSR_EL1 ARM64_SYSREG(3, 0, 4, 0, 0)
#define ELR_EL1 ARM64_SYSREG(3, 0, 4, 0, 1)
#define SP_EL0 ARM64_SYSREG(3, 0, 4, 1, 0)
#define SPSel ARM64_SYSREG(3, 0, 4, 2, 0)
#define CurrentEL ARM64_SYSREG(3, 0, 4, 2, 2)
#define PAN ARM64_SYSREG(3, 0, 4, 2, 3)
#define UAO ARM64_SYSREG(3, 0, 4, 2, 4)
#define ALLINT ARM64_SYSREG(3, 0, 4, 3, 0)
#define PM ARM64_SYSREG(3, 0, 4, 3, 1)
#define ICC_PMR_EL1 ARM64_SYSREG(3, 0, 4, 6, 0)
#define AFSR0_EL1 ARM64_SYSREG(3, 0, 5, 1, 0)
#define AFSR1_EL1 ARM64_SYSREG(3, 0, 5, 1, 1)
#define ESR_EL1 ARM64_SYSREG(3, 0, 5, 2, 0)
#define ERRIDR_EL1 ARM64_SYSREG(3, 0, 5, 3, 0)
#define ERRSELR_EL1 ARM64_SYSREG(3, 0, 5, 3, 1)
#define ERXGSR_EL1 ARM64_SYSREG(3, 0, 5, 3, 2)
#define ERXFR_EL1 ARM64_SYSREG(3, 0, 5, 4, 0)
#define ERXCTLR_EL1 ARM64_SYSREG(3, 0, 5, 4, 1)
#define ERXSTATUS_EL1 ARM64_SYSREG(3, 0, 5, 4, 2)
#define ERXADDR_EL1 ARM64_SYSREG(3, 0, 5, 4, 3)
#define ERXPFGF_EL1 ARM64_SYSREG(3, 0, 5, 4, 4)
#define ERXPFGCTL_EL1 ARM64_SYSREG(3, 0, 5, 4, 5)
#define ERXPFGCDN_EL1 ARM64_SYSREG(3, 0, 5, 4, 6)
#define ERXMISC0_EL1 ARM64_SYSREG(3, 0, 5, 5, 0)
#define ERXMISC1_EL1 ARM64_SYSREG(3, 0, 5, 5, 1)
#define ERXMISC2_EL1 ARM64_SYSREG(3, 0, 5, 5, 2)
#define ERXMISC3_EL1 ARM64_SYSREG(3, 0, 5, 5, 3)
#define TFSR_EL1 ARM64_SYSREG(3, 0, 5, 6, 0)
#define TFSRE0_EL1 ARM64_SYSREG(3, 0, 5, 6, 1)
#define FAR_EL1 ARM64_SYSREG(3, 0, 6, 0, 0)
#define PFAR_EL1 ARM64_SYSREG(3, 0, 6, 0, 5)
#define PAR_EL1 ARM64_SYSREG(3, 0, 7, 4, 0)
#define PMSCR_EL1 ARM64_SYSREG(3, 0, 9, 9, 0)
#define PMSNEVFR_EL1 ARM64_SYSREG(3, 0, 9, 9, 1)
#define PMSICR_EL1 ARM64_SYSREG(3, 0, 9, 9, 2)
#define PMSIRR_EL1 ARM64_SYSREG(3, 0, 9, 9, 3)
#define PMSFCR_EL1 ARM64_SYSREG(3, 0, 9, 9, 4)
#define PMSEVFR_EL1 ARM64_SYSREG(3, 0, 9, 9, 5)
#define PMSLATFR_EL1 ARM64_SYSREG(3, 0, 9, 9, 6)
#define PMSIDR_EL1 ARM64_SYSREG(3, 0, 9, 9, 7)
#define PMBLIMITR_EL1 ARM64_SYSREG(3, 0, 9, 10, 0)
#define PMBPTR_EL1 ARM64_SYSREG(3, 0, 9, 10, 1)
#define PMBSR_EL1 ARM64_SYSREG(3, 0, 9, 10, 3)
#define PMSDSFR_EL1 ARM64_SYSREG(3, 0, 9, 10, 4)
#define PMBIDR_EL1 ARM64_SYSREG(3, 0, 9, 10, 7)
#define TRBLIMITR_EL1 ARM64_SYSREG(3, 0, 9, 11, 0)
#define TRBPTR_EL1 ARM64_SYSREG(3, 0, 9, 11, 1)
#define TRBBASER_EL1 ARM64_SYSREG(3, 0, 9, 11, 2)
#define TRBSR_EL1 ARM64_SYSREG(3, 0, 9, 11, 3)
#define TRBMAR_EL1 ARM64_SYSREG(3, 0, 9, 11, 4)
#define TRBMPAM_EL1 ARM64_SYSREG(3, 0, 9, 11, 5)
#define TRBTRG_EL1 ARM64_SYSREG(3, 0, 9, 11, 6)
#define TRBIDR_EL1 ARM64_SYSREG(3, 0, 9, 11, 7)
#define PMSSCR_EL1 ARM64_SYSREG(3, 0, 9, 13, 3)
#define PMINTENSET_EL1 ARM64_SYSREG(3, 0, 9, 14, 1)
#define PMINTENCLR_EL1 ARM64_SYSREG(3, 0, 9, 14, 2)
#define PMUACR_EL1 ARM64_SYSREG(3, 0, 9, 14, 4)
#define PMECR_EL1 ARM64_SYSREG(3, 0, 9, 14, 5)
#define PMMIR_EL1 ARM64_SYSREG(3, 0, 9, 14, 6)
#define PMIAR_EL1 ARM64_SYSREG(3, 0, 9, 14, 7)
#define MAIR_EL1 ARM64_SYSREG(3, 0, 10, 2, 0)
#define MAIR2_EL1 ARM64_SYSREG(3, 0, 10, 2, 1)
#define PIRE0_EL1 ARM64_SYSREG(3, 0, 10, 2, 2)
#define PIR_EL1 ARM64_SYSREG(3, 0, 10, 2, 3)
#define POR_EL1 ARM64_SYSREG(3, 0, 10, 2, 4)
#define S2POR_EL1 ARM64_SYSREG(3, 0, 10, 2, 5)
#define AMAIR_EL1 ARM64_SYSREG(3, 0, 10, 3, 0)
#define AMAIR2_EL1 ARM64_SYSREG(3, 0, 10, 3, 1)
#define LORSA_EL1 ARM64_SYSREG(3, 0, 10, 4, 0)
#define LOREA_EL1 ARM64_SYSREG(3, 0, 10, 4, 1)
#define LORN_EL1 ARM64_SYSREG(3, 0, 10, 4, 2)
#define LORC_EL1 ARM64_SYSREG(3, 0, 10, 4, 3)
#define MPAMIDR_EL1 ARM64_SYSREG(3, 0, 10, 4, 4)
#define LORID_EL1 ARM64_SYSREG(3, 0, 10, 4, 7)
#define MPAM1_EL1 ARM64_SYSREG(3, 0, 10, 5, 0)
#define MPAM0_EL1 ARM64_SYSREG(3, 0, 10, 5, 1)
#define MPAMSM_EL1 ARM64_SYSREG(3, 0, 10, 5, 3)
#define VBAR_EL1 ARM64_SYSREG(3, 0, 12, 0, 0)
#define RVBAR_EL1 ARM64_SYSREG(3, 0, 12, 0, 1)
#define RMR_EL1 ARM64_SYSREG(3, 0, 12, 0, 2)
#define ISR_EL1 ARM64_SYSREG(3, 0, 12, 1, 0)
#define DISR_EL1 ARM64_SYSREG(3, 0, 12, 1, 1)
#define ICC_IAR0_EL1 ARM64_SYSREG(3, 0, 12, 8, 0)
#define ICC_EOIR0_EL1 ARM64_SYSREG(3, 0, 12, 8, 1)
#define ICC_HPPIR0_EL1 ARM64_SYSREG(3, 0, 12, 8, 2)
#define ICC_BPR0_EL1 ARM64_SYSREG(3, 0, 12, 8, 3)
#define ICC_NMIAR1_EL1 ARM64_SYSREG(3, 0, 12, 9, 5)
#define ICC_DIR_EL1 ARM64_SYSREG(3, 0, 12, 11, 1)
#define ICC_RPR_EL1 ARM64_SYSREG(3, 0, 12, 11, 3)
#define ICC_SGI1R_EL1 ARM64_SYSREG(3, 0, 12, 11, 5)
#define ICC_ASGI1R_EL1 ARM64_SYSREG(3, 0, 12, 11, 6)
#define ICC_SGI0R_EL1 ARM64_SYSREG(3, 0, 12, 11, 7)
#define ICC_IAR1_EL1 ARM64_SYSREG(3, 0, 12, 12, 0)
#define ICC_EOIR1_EL1 ARM64_SYSREG(3, 0, 12, 12, 1)
#define ICC_HPPIR1_EL1 ARM64_SYSREG(3, 0, 12, 12, 2)
#define ICC_BPR1_EL1 ARM64_SYSREG(3, 0, 12, 12, 3)
#define ICC_CTLR_EL1 ARM64_SYSREG(3, 0, 12, 12, 4)
#define ICC_SRE_EL1 ARM64_SYSREG(3, 0, 12, 12, 5)
#define ICC_IGRPEN0_EL1 ARM64_SYSREG(3, 0, 12, 12, 6)
#define ICC_IGRPEN1_EL1 ARM64_SYSREG(3, 0, 12, 12, 7)
#define CONTEXTIDR_EL1 ARM64_SYSREG(3, 0, 13, 0, 1)
#define RCWSMASK_EL1 ARM64_SYSREG(3, 0, 13, 0, 3)
#define TPIDR_EL1 ARM64_SYSREG(3, 0, 13, 0, 4)
#define ACCDATA_EL1 ARM64_SYSREG(3, 0, 13, 0, 5)
#define RCWMASK_EL1 ARM64_SYSREG(3, 0, 13, 0, 6)
#define SCXTNUM_EL1 ARM64_SYSREG(3, 0, 13, 0, 7)
#define CNTKCTL_EL1 ARM64_SYSREG(3, 0, 14, 1, 0)
#define HID0_EL1 ARM64_SYSREG(3, 0, 15, 0, 0)
#define EHID0_EL1 ARM64_SYSREG(3, 0, 15, 0, 1)
#define HID25 ARM64_SYSREG(3, 0, 15, 0, 2)
#define HID26_EL1 ARM64_SYSREG(3, 0, 15, 0, 3)
#define HID27_EL1 ARM64_SYSREG(3, 0, 15, 0, 4)
#define HID28 ARM64_SYSREG(3, 0, 15, 0, 5)
#define HID29 ARM64_SYSREG(3, 0, 15, 0, 6)
#define HID1_EL1 ARM64_SYSREG(3, 0, 15, 1, 0)
#define EHID1_EL1 ARM64_SYSREG(3, 0, 15, 1, 1)
#define EHID20_EL1 ARM64_SYSREG(3, 0, 15, 1, 2)
#define HID21_EL1 ARM64_SYSREG(3, 0, 15, 1, 3)
#define HID22 ARM64_SYSREG(3, 0, 15, 1, 4)
#define HID23 ARM64_SYSREG(3, 0, 15, 1, 5)
#define HID2_EL1 ARM64_SYSREG(3, 0, 15, 2, 0)
#define EHID2_EL1 ARM64_SYSREG(3, 0, 15, 2, 1)
#define HID3_EL1 ARM64_SYSREG(3, 0, 15, 3, 0)
#define EHID3_EL1 ARM64_SYSREG(3, 0, 15, 3, 1)
#define HID4_EL1 ARM64_SYSREG(3, 0, 15, 4, 0)
#define EHID4_EL1 ARM64_SYSREG(3, 0, 15, 4, 1)
#define HID5_EL1 ARM64_SYSREG(3, 0, 15, 5, 0)
#define EHID5_EL1 ARM64_SYSREG(3, 0, 15, 5, 1)
#define HID6_EL1 ARM64_SYSREG(3, 0, 15, 6, 0)
#define HID7_EL1 ARM64_SYSREG(3, 0, 15, 7, 0)
#define EHID7_EL1 ARM64_SYSREG(3, 0, 15, 7, 1)
#define HID8_EL1 ARM64_SYSREG(3, 0, 15, 8, 0)
#define HID9_EL1 ARM64_SYSREG(3, 0, 15, 9, 0)
#define EHID9_EL1 ARM64_SYSREG(3, 0, 15, 9, 1)
#define HID10_EL1 ARM64_SYSREG(3, 0, 15, 10, 0)
#define EHID10_EL1 ARM64_SYSREG(3, 0, 15, 10, 1)
#define BLOCK_CMAINT_CFG ARM64_SYSREG(3, 0, 15, 10, 2)
#define HID11_EL1 ARM64_SYSREG(3, 0, 15, 11, 0)
#define EHID11_EL1 ARM64_SYSREG(3, 0, 15, 11, 1)
#define HID18_EL1 ARM64_SYSREG(3, 0, 15, 11, 2)
#define EHID18_EL1 ARM64_SYSREG(3, 0, 15, 11, 3)
#define HID12 ARM64_SYSREG(3, 0, 15, 12, 0)
#define HID15 ARM64_SYSREG(3, 0, 15, 12, 1)
#define HID19 ARM64_SYSREG(3, 0, 15, 12, 2)
#define BIU_TLIMIT ARM64_SYSREG(3, 0, 15, 13, 0)
#define HID13_EL1 ARM64_SYSREG(3, 0, 15, 14, 0)
#define HID14_EL1 ARM64_SYSREG(3, 0, 15, 15, 0)
#define HID16_EL1 ARM64_SYSREG(3, 0, 15, 15, 2)
#define LLC_WRR2 ARM64_SYSREG(3, 0, 15, 15, 3)
#define HID17_EL1 ARM64_SYSREG(3, 0, 15, 15, 5)
#define HID24 ARM64_SYSREG(3, 0, 15, 15, 6)
#define CCSIDR_EL1 ARM64_SYSREG(3, 1, 0, 0, 0)
#define CLIDR_EL1 ARM64_SYSREG(3, 1, 0, 0, 1)
#define CCSIDR2_EL1 ARM64_SYSREG(3, 1, 0, 0, 2)
#define GMID_EL1 ARM64_SYSREG(3, 1, 0, 0, 4)
#define SMIDR_EL1 ARM64_SYSREG(3, 1, 0, 0, 6)
#define AIDR_EL1 ARM64_SYSREG(3, 1, 0, 0, 7)
#define PMCR0_EL1 ARM64_SYSREG(3, 1, 15, 0, 0)
#define APPL_CONTEXTPTR ARM64_SYSREG(3, 1, 15, 0, 1)
#define LD_LATPROF_CTL_EL21 ARM64_SYSREG(3, 1, 15, 0, 2)
#define AON_CPU_MSTALL_CTL01_EL1 ARM64_SYSREG(3, 1, 15, 0, 3)
#define PM_MEMFLT_CTL23_EL1 ARM64_SYSREG(3, 1, 15, 0, 4)
#define REDIR_ACNTV_CTL_EL0 ARM64_SYSREG(3, 1, 15, 0, 5)
#define LCL_ACNTVCTSS_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 0, 6)
#define PMCR1_EL1 ARM64_SYSREG(3, 1, 15, 1, 0)
#define LD_LATPROF_CTR_EL1 ARM64_SYSREG(3, 1, 15, 1, 2)
#define AON_CPU_MSTALL_CTL23_EL1 ARM64_SYSREG(3, 1, 15, 1, 3)
#define PM_MEMFLT_CTL45_EL1 ARM64_SYSREG(3, 1, 15, 1, 4)
#define ACNTRDIR_EL21 ARM64_SYSREG(3, 1, 15, 1, 5)
#define ACNTKCTL_NOREDIR_EL1 ARM64_SYSREG(3, 1, 15, 1, 6)
#define PMCR2_EL1 ARM64_SYSREG(3, 1, 15, 2, 0)
#define LD_LATPROF_STS_EL1 ARM64_SYSREG(3, 1, 15, 2, 2)
#define AON_CPU_MSTALL_CTL45_EL1 ARM64_SYSREG(3, 1, 15, 2, 3)
#define REDIR_ACNTHP_CVAL_EL2 ARM64_SYSREG(3, 1, 15, 2, 4)
#define LCL_CNTVCT_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 2, 5)
#define ACNTP_CVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 2, 6)
#define PMCR3_EL1 ARM64_SYSREG(3, 1, 15, 3, 0)
#define LD_LATPROF_INF_EL1 ARM64_SYSREG(3, 1, 15, 3, 2)
#define AON_CPU_MSTALL_CTL67_EL1 ARM64_SYSREG(3, 1, 15, 3, 3)
#define REDIR_ACNTHP_TVAL_EL2 ARM64_SYSREG(3, 1, 15, 3, 4)
#define LCL_CNTPCTSS_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 3, 5)
#define ACNTP_TVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 3, 6)
#define PMCR4_EL1 ARM64_SYSREG(3, 1, 15, 4, 0)
#define LD_LATPROF_CTL_EL2 ARM64_SYSREG(3, 1, 15, 4, 2)
#define AON_CPU_MEMFLT_CTL01_EL1 ARM64_SYSREG(3, 1, 15, 4, 3)
#define REDIR_ACNTHP_CTL_EL2 ARM64_SYSREG(3, 1, 15, 4, 4)
#define LCL_CNTVCTSS_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 4, 5)
#define ACNTP_CTL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 4, 6)
#define PMESR0_EL1 ARM64_SYSREG(3, 1, 15, 5, 0)
#define LD_LATPROF_CMD_EL1 ARM64_SYSREG(3, 1, 15, 5, 2)
#define AON_CPU_MEMFLT_CTL23_EL1 ARM64_SYSREG(3, 1, 15, 5, 3)
#define REDIR_ACNTHV_CVAL_EL2 ARM64_SYSREG(3, 1, 15, 5, 4)
#define ACNTV_CVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 5, 6)
#define PMESR1_EL1 ARM64_SYSREG(3, 1, 15, 6, 0)
#define PMCR1_EL2 ARM64_SYSREG(3, 1, 15, 6, 2)
#define AON_CPU_MEMFLT_CTL45_EL1 ARM64_SYSREG(3, 1, 15, 6, 3)
#define REDIR_ACNTHV_TVAL_EL2 ARM64_SYSREG(3, 1, 15, 6, 4)
#define CNTKCTL_NOREDIR_EL1 ARM64_SYSREG(3, 1, 15, 6, 5)
#define ACNTV_TVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 6, 6)
#define OPMAT0 ARM64_SYSREG(3, 1, 15, 7, 0)
#define PMCR1_EL12 ARM64_SYSREG(3, 1, 15, 7, 2)
#define AON_CPU_MEMFLT_CTL67_EL1 ARM64_SYSREG(3, 1, 15, 7, 3)
#define REDIR_ACNTHV_CTL_EL2 ARM64_SYSREG(3, 1, 15, 7, 4)
#define CNTP_CVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 7, 5)
#define ACNTV_CTL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 7, 6)
#define OPMAT1 ARM64_SYSREG(3, 1, 15, 8, 0)
#define PMCR1_GL1 ARM64_SYSREG(3, 1, 15, 8, 2)
#define AON_CPU_MSTALL_CTR0_EL1 ARM64_SYSREG(3, 1, 15, 8, 3)
#define REDIR_ACNTFRQ_EL0 ARM64_SYSREG(3, 1, 15, 8, 4)
#define CNTP_TVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 8, 5)
#define LCL_CNTPCT_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 8, 6)
#define OPMSK0 ARM64_SYSREG(3, 1, 15, 9, 0)
#define LD_LATPROF_CTL_EL12 ARM64_SYSREG(3, 1, 15, 9, 2)
#define AON_CPU_MSTALL_CTR1_EL1 ARM64_SYSREG(3, 1, 15, 9, 3)
#define ACNTVOFF_EL2 ARM64_SYSREG(3, 1, 15, 9, 4)
#define CNTP_CTL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 9, 5)
#define CNTV_CTL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 9, 6)
#define OPMSK1 ARM64_SYSREG(3, 1, 15, 10, 0)
#define LD_LATPROF_INF_EL2 ARM64_SYSREG(3, 1, 15, 10, 2)
#define AON_CPU_MSTALL_CTR2_EL1 ARM64_SYSREG(3, 1, 15, 10, 3)
#define REDIR_ACNTP_CVAL_EL0 ARM64_SYSREG(3, 1, 15, 10, 4)
#define CNTV_CVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 10, 5)
#define LCL_ACNTPCT_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 10, 6)
#define PMCR_AFFINITY_EL1 ARM64_SYSREG(3, 1, 15, 11, 0)
#define AON_CPU_MSTALL_CTR3_EL1 ARM64_SYSREG(3, 1, 15, 11, 3)
#define REDIR_ACNTP_TVAL_EL0 ARM64_SYSREG(3, 1, 15, 11, 4)
#define CNTV_TVAL_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 11, 5)
#define VMSA_HV_LOCK_EL2 ARM64_SYSREG(3, 1, 15, 11, 6)
#define PMSWCTRL_EL1 ARM64_SYSREG(3, 1, 15, 12, 0)
#define PMCR5_EL0 ARM64_SYSREG(3, 1, 15, 12, 1)
#define AON_CPU_MSTALL_CTR4_EL1 ARM64_SYSREG(3, 1, 15, 12, 3)
#define PMCompare0_EL1 ARM64_SYSREG(3, 1, 15, 12, 4)
#define PMCompare1_EL1 ARM64_SYSREG(3, 1, 15, 12, 5)
#define VMSA_NV_LOCK_EL2 ARM64_SYSREG(3, 1, 15, 12, 6)
#define PMSR_EL1 ARM64_SYSREG(3, 1, 15, 13, 0)
#define AON_CPU_MSTALL_CTR5_EL1 ARM64_SYSREG(3, 1, 15, 13, 3)
#define REDIR_ACNTP_CTL_EL0 ARM64_SYSREG(3, 1, 15, 13, 4)
#define PMCompare5_EL1 ARM64_SYSREG(3, 1, 15, 13, 5)
#define PMCompare6_EL1 ARM64_SYSREG(3, 1, 15, 13, 6)
#define PMCompare7_EL1 ARM64_SYSREG(3, 1, 15, 13, 7)
#define PMCR_BVRNG4_EL1 ARM64_SYSREG(3, 1, 15, 14, 0)
#define PM_PMI_PC ARM64_SYSREG(3, 1, 15, 14, 1)
#define AON_CPU_MSTALL_CTR6_EL1 ARM64_SYSREG(3, 1, 15, 14, 3)
#define REDIR_ACNTV_CVAL_EL0 ARM64_SYSREG(3, 1, 15, 14, 4)
#define LCL_ACNTVCT_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 14, 5)
#define PMCR_BVRNG5_EL1 ARM64_SYSREG(3, 1, 15, 15, 0)
#define AON_CPU_MSTALL_CTR7_EL1 ARM64_SYSREG(3, 1, 15, 15, 3)
#define REDIR_ACNTV_TVAL_EL0 ARM64_SYSREG(3, 1, 15, 15, 4)
#define LCL_ACNTPCTSS_NOREDIR_EL0 ARM64_SYSREG(3, 1, 15, 15, 5)
#define CSSELR_EL1 ARM64_SYSREG(3, 2, 0, 0, 0)
#define PMC0_EL1 ARM64_SYSREG(3, 2, 15, 0, 0)
#define UPMCFILTER0 ARM64_SYSREG(3, 2, 15, 0, 1)
#define UPMCFILTER1 ARM64_SYSREG(3, 2, 15, 0, 2)
#define UPMCFILTER2 ARM64_SYSREG(3, 2, 15, 0, 3)
#define UPMCFILTER3 ARM64_SYSREG(3, 2, 15, 0, 4)
#define UPMCFILTER4 ARM64_SYSREG(3, 2, 15, 0, 5)
#define UPMCFILTER5 ARM64_SYSREG(3, 2, 15, 0, 6)
#define UPMCFILTER6 ARM64_SYSREG(3, 2, 15, 0, 7)
#define PMC1_EL1 ARM64_SYSREG(3, 2, 15, 1, 0)
#define UPMCFILTER7 ARM64_SYSREG(3, 2, 15, 1, 1)
#define PMC2_EL1 ARM64_SYSREG(3, 2, 15, 2, 0)
#define PMC3_EL1 ARM64_SYSREG(3, 2, 15, 3, 0)
#define PMC4_EL1 ARM64_SYSREG(3, 2, 15, 4, 0)
#define PMC5_EL1 ARM64_SYSREG(3, 2, 15, 5, 0)
#define PMC6_EL1 ARM64_SYSREG(3, 2, 15, 6, 0)
#define PMC7_EL1 ARM64_SYSREG(3, 2, 15, 7, 0)
#define PMC8_EL1 ARM64_SYSREG(3, 2, 15, 9, 0)
#define PMC9_EL1 ARM64_SYSREG(3, 2, 15, 10, 0)
#define PMTRHLD6 ARM64_SYSREG(3, 2, 15, 12, 0)
#define PMTRHLD4 ARM64_SYSREG(3, 2, 15, 13, 0)
#define PMTRHLD2 ARM64_SYSREG(3, 2, 15, 14, 0)
#define PMMMAP ARM64_SYSREG(3, 2, 15, 15, 0)
#define CTR_EL0 ARM64_SYSREG(3, 3, 0, 0, 1)
#define DCZID_EL0 ARM64_SYSREG(3, 3, 0, 0, 7)
#define RNDR ARM64_SYSREG(3, 3, 2, 4, 0)
#define RNDRRS ARM64_SYSREG(3, 3, 2, 4, 1)
#define GCSPR_EL0 ARM64_SYSREG(3, 3, 2, 5, 1)
#define NZCV ARM64_SYSREG(3, 3, 4, 2, 0)
#define DAIF ARM64_SYSREG(3, 3, 4, 2, 1)
#define SVCR ARM64_SYSREG(3, 3, 4, 2, 2)
#define DIT ARM64_SYSREG(3, 3, 4, 2, 5)
#define SSBS ARM64_SYSREG(3, 3, 4, 2, 6)
#define TCO ARM64_SYSREG(3, 3, 4, 2, 7)
#define FPCR ARM64_SYSREG(3, 3, 4, 4, 0)
#define FPSR ARM64_SYSREG(3, 3, 4, 4, 1)
#define FPMR ARM64_SYSREG(3, 3, 4, 4, 2)
#define DSPSR_EL0 ARM64_SYSREG(3, 3, 4, 5, 0)
#define DLR_EL0 ARM64_SYSREG(3, 3, 4, 5, 1)
#define PMICNTR_EL0 ARM64_SYSREG(3, 3, 9, 4, 0)
#define PMICFILTR_EL0 ARM64_SYSREG(3, 3, 9, 6, 0)
#define PMCR_EL0 ARM64_SYSREG(3, 3, 9, 12, 0)
#define PMCNTENSET_EL0 ARM64_SYSREG(3, 3, 9, 12, 1)
#define PMCNTENCLR_EL0 ARM64_SYSREG(3, 3, 9, 12, 2)
#define PMOVSCLR_EL0 ARM64_SYSREG(3, 3, 9, 12, 3)
#define PMSWINC_EL0 ARM64_SYSREG(3, 3, 9, 12, 4)
#define PMSELR_EL0 ARM64_SYSREG(3, 3, 9, 12, 5)
#define PMCEID0_EL0 ARM64_SYSREG(3, 3, 9, 12, 6)
#define PMCEID1_EL0 ARM64_SYSREG(3, 3, 9, 12, 7)
#define PMCCNTR_EL0 ARM64_SYSREG(3, 3, 9, 13, 0)
#define PMXEVTYPER_EL0 ARM64_SYSREG(3, 3, 9, 13, 1)
#define PMXEVCNTR_EL0 ARM64_SYSREG(3, 3, 9, 13, 2)
#define PMZR_EL0 ARM64_SYSREG(3, 3, 9, 13, 4)
#define PMUSERENR_EL0 ARM64_SYSREG(3, 3, 9, 14, 0)
#define PMOVSSET_EL0 ARM64_SYSREG(3, 3, 9, 14, 3)
#define POR_EL0 ARM64_SYSREG(3, 3, 10, 2, 4)
#define TPIDR_EL0 ARM64_SYSREG(3, 3, 13, 0, 2)
#define TPIDRRO_EL0 ARM64_SYSREG(3, 3, 13, 0, 3)
#define TPIDR2_EL0 ARM64_SYSREG(3, 3, 13, 0, 5)
#define SCXTNUM_EL0 ARM64_SYSREG(3, 3, 13, 0, 7)
#define AMCR_EL0 ARM64_SYSREG(3, 3, 13, 2, 0)
#define AMCFGR_EL0 ARM64_SYSREG(3, 3, 13, 2, 1)
#define AMCGCR_EL0 ARM64_SYSREG(3, 3, 13, 2, 2)
#define AMUSERENR_EL0 ARM64_SYSREG(3, 3, 13, 2, 3)
#define AMCNTENCLR0_EL0 ARM64_SYSREG(3, 3, 13, 2, 4)
#define AMCNTENSET0_EL0 ARM64_SYSREG(3, 3, 13, 2, 5)
#define AMCG1IDR_EL0 ARM64_SYSREG(3, 3, 13, 2, 6)
#define AMCNTENCLR1_EL0 ARM64_SYSREG(3, 3, 13, 3, 0)
#define AMCNTENSET1_EL0 ARM64_SYSREG(3, 3, 13, 3, 1)
#define CNTFRQ_EL0 ARM64_SYSREG(3, 3, 14, 0, 0)
#define CNTPCT_EL0 ARM64_SYSREG(3, 3, 14, 0, 1)
#define CNTVCT_EL0 ARM64_SYSREG(3, 3, 14, 0, 2)
#define CNTPCTSS_EL0 ARM64_SYSREG(3, 3, 14, 0, 5)
#define CNTVCTSS_EL0 ARM64_SYSREG(3, 3, 14, 0, 6)
#define CNTP_TVAL_EL0 ARM64_SYSREG(3, 3, 14, 2, 0)
#define CNTP_CTL_EL0 ARM64_SYSREG(3, 3, 14, 2, 1)
#define CNTP_CVAL_EL0 ARM64_SYSREG(3, 3, 14, 2, 2)
#define CNTV_TVAL_EL0 ARM64_SYSREG(3, 3, 14, 3, 0)
#define CNTV_CTL_EL0 ARM64_SYSREG(3, 3, 14, 3, 1)
#define CNTV_CVAL_EL0 ARM64_SYSREG(3, 3, 14, 3, 2)
#define PMCCFILTR_EL0 ARM64_SYSREG(3, 3, 14, 15, 7)
#define LSU_ERR_STS_EL1 ARM64_SYSREG(3, 3, 15, 0, 0)
#define AFLATCTL1_EL1 ARM64_SYSREG(3, 3, 15, 0, 4)
#define AFLATVALBIN0_EL1 ARM64_SYSREG(3, 3, 15, 0, 5)
#define AFLATINFLO_EL1 ARM64_SYSREG(3, 3, 15, 0, 6)
#define LSU_ERR_CTL_EL1 ARM64_SYSREG(3, 3, 15, 1, 0)
#define AFLATCTL2_EL1 ARM64_SYSREG(3, 3, 15, 1, 4)
#define AFLATVALBIN1_EL1 ARM64_SYSREG(3, 3, 15, 1, 5)
#define AFLATINFHI_EL1 ARM64_SYSREG(3, 3, 15, 1, 6)
#define E_LSU_ERR_STS_EL1 ARM64_SYSREG(3, 3, 15, 2, 0)
#define AFLATCTL3_EL1 ARM64_SYSREG(3, 3, 15, 2, 4)
#define AFLATVALBIN2_EL1 ARM64_SYSREG(3, 3, 15, 2, 5)
#define AFLATCTL4_EL1 ARM64_SYSREG(3, 3, 15, 3, 4)
#define AFLATVALBIN3_EL1 ARM64_SYSREG(3, 3, 15, 3, 5)
#define LLC_FILL_CTL ARM64_SYSREG(3, 3, 15, 4, 0)
#define AFLATCTL5_LO_EL1 ARM64_SYSREG(3, 3, 15, 4, 4)
#define AFLATVALBIN4_EL1 ARM64_SYSREG(3, 3, 15, 4, 5)
#define AFLATCTL5_HI_EL1 ARM64_SYSREG(3, 3, 15, 4, 6)
#define LLC_FILL_DAT ARM64_SYSREG(3, 3, 15, 5, 0)
#define AFLATVALBIN5_EL1 ARM64_SYSREG(3, 3, 15, 5, 5)
#define AFLATVALBIN6_EL1 ARM64_SYSREG(3, 3, 15, 6, 5)
#define L2_CRAMCONFIG ARM64_SYSREG(3, 3, 15, 7, 0)
#define AFLATVALBIN7_EL1 ARM64_SYSREG(3, 3, 15, 7, 5)
#define L2C_ERR_STS_EL1 ARM64_SYSREG(3, 3, 15, 8, 0)
#define L2E_ERR_STS ARM64_SYSREG(3, 3, 15, 8, 1)
#define CMAINT_BCAST_LIST_1 ARM64_SYSREG(3, 3, 15, 8, 2)
#define CMAINT_BCAST_CTL ARM64_SYSREG(3, 3, 15, 8, 3)
#define L2C_ERR_ADR_EL1 ARM64_SYSREG(3, 3, 15, 9, 0)
#define L2E_ERR_ADR ARM64_SYSREG(3, 3, 15, 9, 1)
#define LLC_ERR_INJ ARM64_SYSREG(3, 3, 15, 9, 2)
#define L2C_ERR_INF_EL1 ARM64_SYSREG(3, 3, 15, 10, 0)
#define L2E_ERR_INF ARM64_SYSREG(3, 3, 15, 10, 1)
#define UUSERTAG_EL0 ARM64_SYSREG(3, 3, 15, 10, 2)
#define KUSERTAG_EL1 ARM64_SYSREG(3, 3, 15, 10, 3)
#define HUSERTAG_EL2 ARM64_SYSREG(3, 3, 15, 10, 4)
#define LLC_TRACE_CTL0 ARM64_SYSREG(3, 3, 15, 11, 0)
#define LLC_TRACE_CTL1 ARM64_SYSREG(3, 3, 15, 12, 0)
#define LLC_UP_REQ_VC ARM64_SYSREG(3, 3, 15, 13, 0)
#define LLC_UP_REQ_VC_THRESH ARM64_SYSREG(3, 3, 15, 13, 1)
#define LLC_UP_REQ_VC_2 ARM64_SYSREG(3, 3, 15, 13, 2)
#define LLC_UP_REQ_VC_THRESH_2 ARM64_SYSREG(3, 3, 15, 13, 3)
#define LLC_DRAM_HASH0 ARM64_SYSREG(3, 3, 15, 13, 4)
#define LLC_DRAM_HASH1 ARM64_SYSREG(3, 3, 15, 13, 5)
#define LLC_DRAM_HASH2 ARM64_SYSREG(3, 3, 15, 13, 6)
#define LLC_DRAM_HASH3 ARM64_SYSREG(3, 3, 15, 13, 7)
#define LLC_TRACE_CTL2 ARM64_SYSREG(3, 3, 15, 14, 0)
#define LLC_HASH0 ARM64_SYSREG(3, 3, 15, 15, 0)
#define LLC_HASH1 ARM64_SYSREG(3, 3, 15, 15, 1)
#define LLC_HASH2 ARM64_SYSREG(3, 3, 15, 15, 2)
#define LLC_HASH3 ARM64_SYSREG(3, 3, 15, 15, 3)
#define LLC_WRR ARM64_SYSREG(3, 3, 15, 15, 4)
#define VPIDR_EL2 ARM64_SYSREG(3, 4, 0, 0, 0)
#define VMPIDR_EL2 ARM64_SYSREG(3, 4, 0, 0, 5)
#define SCTLR_EL2 ARM64_SYSREG(3, 4, 1, 0, 0)
#define ACTLR_EL2 ARM64_SYSREG(3, 4, 1, 0, 1)
#define SCTLR2_EL2 ARM64_SYSREG(3, 4, 1, 0, 3)
#define HCR_EL2 ARM64_SYSREG(3, 4, 1, 1, 0)
#define MDCR_EL2 ARM64_SYSREG(3, 4, 1, 1, 1)
#define CPTR_EL2 ARM64_SYSREG(3, 4, 1, 1, 2)
#define HSTR_EL2 ARM64_SYSREG(3, 4, 1, 1, 3)
#define HFGRTR_EL2 ARM64_SYSREG(3, 4, 1, 1, 4)
#define HFGWTR_EL2 ARM64_SYSREG(3, 4, 1, 1, 5)
#define HFGITR_EL2 ARM64_SYSREG(3, 4, 1, 1, 6)
#define HACR_EL2 ARM64_SYSREG(3, 4, 1, 1, 7)
#define ZCR_EL2 ARM64_SYSREG(3, 4, 1, 2, 0)
#define TRFCR_EL2 ARM64_SYSREG(3, 4, 1, 2, 1)
#define HCRX_EL2 ARM64_SYSREG(3, 4, 1, 2, 2)
#define TRCITECR_EL2 ARM64_SYSREG(3, 4, 1, 2, 3)
#define SMPRIMAP_EL2 ARM64_SYSREG(3, 4, 1, 2, 5)
#define SMCR_EL2 ARM64_SYSREG(3, 4, 1, 2, 6)
#define SDER32_EL2 ARM64_SYSREG(3, 4, 1, 3, 1)
#define TTBR0_EL2 ARM64_SYSREG(3, 4, 2, 0, 0)
#define TTBR1_EL2 ARM64_SYSREG(3, 4, 2, 0, 1)
#define TCR_EL2 ARM64_SYSREG(3, 4, 2, 0, 2)
#define TCR2_EL2 ARM64_SYSREG(3, 4, 2, 0, 3)
#define VTTBR_EL2 ARM64_SYSREG(3, 4, 2, 1, 0)
#define VTCR_EL2 ARM64_SYSREG(3, 4, 2, 1, 2)
#define VNCR_EL2 ARM64_SYSREG(3, 4, 2, 2, 0)
#define HDBSSBR_EL2 ARM64_SYSREG(3, 4, 2, 3, 2)
#define HDBSSPROD_EL2 ARM64_SYSREG(3, 4, 2, 3, 3)
#define HACDBSBR_EL2 ARM64_SYSREG(3, 4, 2, 3, 4)
#define HACDBSCONS_EL2 ARM64_SYSREG(3, 4, 2, 3, 5)
#define GCSCR_EL2 ARM64_SYSREG(3, 4, 2, 5, 0)
#define GCSPR_EL2 ARM64_SYSREG(3, 4, 2, 5, 1)
#define VSTTBR_EL2 ARM64_SYSREG(3, 4, 2, 6, 0)
#define VSTCR_EL2 ARM64_SYSREG(3, 4, 2, 6, 2)
#define DACR32_EL2 ARM64_SYSREG(3, 4, 3, 0, 0)
#define HDFGRTR2_EL2 ARM64_SYSREG(3, 4, 3, 1, 0)
#define HDFGWTR2_EL2 ARM64_SYSREG(3, 4, 3, 1, 1)
#define HFGRTR2_EL2 ARM64_SYSREG(3, 4, 3, 1, 2)
#define HFGWTR2_EL2 ARM64_SYSREG(3, 4, 3, 1, 3)
#define HDFGRTR_EL2 ARM64_SYSREG(3, 4, 3, 1, 4)
#define HDFGWTR_EL2 ARM64_SYSREG(3, 4, 3, 1, 5)
#define HAFGRTR_EL2 ARM64_SYSREG(3, 4, 3, 1, 6)
#define HFGITR2_EL2 ARM64_SYSREG(3, 4, 3, 1, 7)
#define SPSR_EL2 ARM64_SYSREG(3, 4, 4, 0, 0)
#define ELR_EL2 ARM64_SYSREG(3, 4, 4, 0, 1)
#define SP_EL1 ARM64_SYSREG(3, 4, 4, 1, 0)
#define SPSR_irq ARM64_SYSREG(3, 4, 4, 3, 0)
#define SPSR_abt ARM64_SYSREG(3, 4, 4, 3, 1)
#define SPSR_und ARM64_SYSREG(3, 4, 4, 3, 2)
#define SPSR_fiq ARM64_SYSREG(3, 4, 4, 3, 3)
#define IFSR32_EL2 ARM64_SYSREG(3, 4, 5, 0, 1)
#define AFSR0_EL2 ARM64_SYSREG(3, 4, 5, 1, 0)
#define AFSR1_EL2 ARM64_SYSREG(3, 4, 5, 1, 1)
#define ESR_EL2 ARM64_SYSREG(3, 4, 5, 2, 0)
#define VSESR_EL2 ARM64_SYSREG(3, 4, 5, 2, 3)
#define FPEXC32_EL2 ARM64_SYSREG(3, 4, 5, 3, 0)
#define TFSR_EL2 ARM64_SYSREG(3, 4, 5, 6, 0)
#define FAR_EL2 ARM64_SYSREG(3, 4, 6, 0, 0)
#define HPFAR_EL2 ARM64_SYSREG(3, 4, 6, 0, 4)
#define PFAR_EL2 ARM64_SYSREG(3, 4, 6, 0, 5)
#define PMSCR_EL2 ARM64_SYSREG(3, 4, 9, 9, 0)
#define MAIR2_EL2 ARM64_SYSREG(3, 4, 10, 1, 1)
#define MAIR_EL2 ARM64_SYSREG(3, 4, 10, 2, 0)
#define PIRE0_EL2 ARM64_SYSREG(3, 4, 10, 2, 2)
#define PIR_EL2 ARM64_SYSREG(3, 4, 10, 2, 3)
#define POR_EL2 ARM64_SYSREG(3, 4, 10, 2, 4)
#define S2PIR_EL2 ARM64_SYSREG(3, 4, 10, 2, 5)
#define AMAIR_EL2 ARM64_SYSREG(3, 4, 10, 3, 0)
#define AMAIR2_EL2 ARM64_SYSREG(3, 4, 10, 3, 1)
#define MPAMHCR_EL2 ARM64_SYSREG(3, 4, 10, 4, 0)
#define MPAMVPMV_EL2 ARM64_SYSREG(3, 4, 10, 4, 1)
#define MPAM2_EL2 ARM64_SYSREG(3, 4, 10, 5, 0)
#define MPAMVPM0_EL2 ARM64_SYSREG(3, 4, 10, 6, 0)
#define MPAMVPM1_EL2 ARM64_SYSREG(3, 4, 10, 6, 1)
#define MPAMVPM2_EL2 ARM64_SYSREG(3, 4, 10, 6, 2)
#define MPAMVPM3_EL2 ARM64_SYSREG(3, 4, 10, 6, 3)
#define MPAMVPM4_EL2 ARM64_SYSREG(3, 4, 10, 6, 4)
#define MPAMVPM5_EL2 ARM64_SYSREG(3, 4, 10, 6, 5)
#define MPAMVPM6_EL2 ARM64_SYSREG(3, 4, 10, 6, 6)
#define MPAMVPM7_EL2 ARM64_SYSREG(3, 4, 10, 6, 7)
#define MECID_P0_EL2 ARM64_SYSREG(3, 4, 10, 8, 0)
#define MECID_A0_EL2 ARM64_SYSREG(3, 4, 10, 8, 1)
#define MECID_P1_EL2 ARM64_SYSREG(3, 4, 10, 8, 2)
#define MECID_A1_EL2 ARM64_SYSREG(3, 4, 10, 8, 3)
#define MECIDR_EL2 ARM64_SYSREG(3, 4, 10, 8, 7)
#define VMECID_P_EL2 ARM64_SYSREG(3, 4, 10, 9, 0)
#define VMECID_A_EL2 ARM64_SYSREG(3, 4, 10, 9, 1)
#define VBAR_EL2 ARM64_SYSREG(3, 4, 12, 0, 0)
#define RVBAR_EL2 ARM64_SYSREG(3, 4, 12, 0, 1)
#define RMR_EL2 ARM64_SYSREG(3, 4, 12, 0, 2)
#define VDISR_EL2 ARM64_SYSREG(3, 4, 12, 1, 1)
#define ICC_SRE_EL2 ARM64_SYSREG(3, 4, 12, 9, 5)
#define ICH_HCR_EL2 ARM64_SYSREG(3, 4, 12, 11, 0)
#define ICH_VTR_EL2 ARM64_SYSREG(3, 4, 12, 11, 1)
#define ICH_MISR_EL2 ARM64_SYSREG(3, 4, 12, 11, 2)
#define ICH_EISR_EL2 ARM64_SYSREG(3, 4, 12, 11, 3)
#define ICH_ELRSR_EL2 ARM64_SYSREG(3, 4, 12, 11, 5)
#define ICH_VMCR_EL2 ARM64_SYSREG(3, 4, 12, 11, 7)
#define CONTEXTIDR_EL2 ARM64_SYSREG(3, 4, 13, 0, 1)
#define TPIDR_EL2 ARM64_SYSREG(3, 4, 13, 0, 2)
#define SCXTNUM_EL2 ARM64_SYSREG(3, 4, 13, 0, 7)
#define CNTVOFF_EL2 ARM64_SYSREG(3, 4, 14, 0, 3)
#define CNTPOFF_EL2 ARM64_SYSREG(3, 4, 14, 0, 6)
#define CNTHCTL_EL2 ARM64_SYSREG(3, 4, 14, 1, 0)
#define CNTHP_TVAL_EL2 ARM64_SYSREG(3, 4, 14, 2, 0)
#define CNTHP_CTL_EL2 ARM64_SYSREG(3, 4, 14, 2, 1)
#define CNTHP_CVAL_EL2 ARM64_SYSREG(3, 4, 14, 2, 2)
#define CNTHV_TVAL_EL2 ARM64_SYSREG(3, 4, 14, 3, 0)
#define CNTHV_CTL_EL2 ARM64_SYSREG(3, 4, 14, 3, 1)
#define CNTHV_CVAL_EL2 ARM64_SYSREG(3, 4, 14, 3, 2)
#define CNTHVS_TVAL_EL2 ARM64_SYSREG(3, 4, 14, 4, 0)
#define CNTHVS_CTL_EL2 ARM64_SYSREG(3, 4, 14, 4, 1)
#define CNTHVS_CVAL_EL2 ARM64_SYSREG(3, 4, 14, 4, 2)
#define CNTHPS_TVAL_EL2 ARM64_SYSREG(3, 4, 14, 5, 0)
#define CNTHPS_CTL_EL2 ARM64_SYSREG(3, 4, 14, 5, 1)
#define CNTHPS_CVAL_EL2 ARM64_SYSREG(3, 4, 14, 5, 2)
#define FED_ERR_STS_EL1 ARM64_SYSREG(3, 4, 15, 0, 0)
#define FED_ERR_CTL ARM64_SYSREG(3, 4, 15, 0, 1)
#define E_FED_ERR_STS_EL1 ARM64_SYSREG(3, 4, 15, 0, 2)
#define APCTL_EL1 ARM64_SYSREG(3, 4, 15, 0, 4)
#define SPR_LOCKDOWN_EL1 ARM64_SYSREG(3, 4, 15, 0, 5)
#define IMPL_MSR_RO_CTRL0_EL2 ARM64_SYSREG(3, 4, 15, 0, 7)
#define KERNKEYLO_EL1 ARM64_SYSREG(3, 4, 15, 1, 0)
#define KERNKEYHI_EL1 ARM64_SYSREG(3, 4, 15, 1, 1)
#define VMSA_LOCK_EL1 ARM64_SYSREG(3, 4, 15, 1, 2)
#define AMX_STATE_EL12 ARM64_SYSREG(3, 4, 15, 1, 3)
#define AMX_CONFIG_EL1 ARM64_SYSREG(3, 4, 15, 1, 4)
#define VMSA_LOCK_EL2 ARM64_SYSREG(3, 4, 15, 1, 5)
#define CTRR_B_UPR_EL1 ARM64_SYSREG(3, 4, 15, 1, 6)
#define CTRR_B_LWR_EL1 ARM64_SYSREG(3, 4, 15, 1, 7)
#define APRR_EL0 ARM64_SYSREG(3, 4, 15, 2, 0)
#define APRR_EL1 ARM64_SYSREG(3, 4, 15, 2, 1)
#define CTRR_LOCK_EL1 ARM64_SYSREG(3, 4, 15, 2, 2)
#define CTRR_A_LWR_EL1 ARM64_SYSREG(3, 4, 15, 2, 3)
#define CTRR_A_UPR_EL1 ARM64_SYSREG(3, 4, 15, 2, 4)
#define CTRR_CTL_EL1 ARM64_SYSREG(3, 4, 15, 2, 5)
#define VMSA_LOCK_EL12 ARM64_SYSREG(3, 4, 15, 2, 6)
#define APRR_JIT_MASK_EL2 ARM64_SYSREG(3, 4, 15, 2, 7)
#define AMX_STATE_C0_EL1 ARM64_SYSREG(3, 4, 15, 3, 0)
#define AMX_STATE_C1_EL1 ARM64_SYSREG(3, 4, 15, 3, 1)
#define AMX_STATE_C2_EL1 ARM64_SYSREG(3, 4, 15, 3, 2)
#define AMX_STATE_C3_EL1 ARM64_SYSREG(3, 4, 15, 3, 3)
#define AMX_STATUS_C0_EL1 ARM64_SYSREG(3, 4, 15, 3, 4)
#define AMX_STATUS_C1_EL1 ARM64_SYSREG(3, 4, 15, 3, 5)
#define AMX_STATUS_C2_EL1 ARM64_SYSREG(3, 4, 15, 3, 6)
#define AMX_STATUS_C3_EL1 ARM64_SYSREG(3, 4, 15, 3, 7)
#define AMX_NUMCTXT_EL1 ARM64_SYSREG(3, 4, 15, 4, 0)
#define ACNTP_CVAL_EL02 ARM64_SYSREG(3, 4, 15, 4, 1)
#define REDIR_ACNTP_TVAL_EL02 ARM64_SYSREG(3, 4, 15, 4, 2)
#define ACNTP_CTL_EL02 ARM64_SYSREG(3, 4, 15, 4, 3)
#define ACNTV_CVAL_EL02 ARM64_SYSREG(3, 4, 15, 4, 4)
#define ACNTV_TVAL_EL02 ARM64_SYSREG(3, 4, 15, 4, 5)
#define AMX_CONFIG_EL12 ARM64_SYSREG(3, 4, 15, 4, 6)
#define AMX_CTL_EL2 ARM64_SYSREG(3, 4, 15, 4, 7)
#define CORE_INDEX ARM64_SYSREG(3, 4, 15, 5, 0)
#define SPRR_PPERM_EL20 ARM64_SYSREG(3, 4, 15, 5, 1)
#define SPRR_UPERM_EL02 ARM64_SYSREG(3, 4, 15, 5, 2)
#define AMX_PRIORITY_C0_EL1 ARM64_SYSREG(3, 4, 15, 5, 6)
#define AMX_PRIORITY_C1_EL1 ARM64_SYSREG(3, 4, 15, 5, 7)
#define AMX_PRIORITY_C2_EL1 ARM64_SYSREG(3, 4, 15, 6, 0)
#define AMX_PRIORITY_C3_EL1 ARM64_SYSREG(3, 4, 15, 6, 1)
#define CTRR_CTL_EL2 ARM64_SYSREG(3, 4, 15, 6, 2)
#define CTRR_LOCK_EL2 ARM64_SYSREG(3, 4, 15, 6, 3)
#define CTRR_A_LWR_EL2 ARM64_SYSREG(3, 4, 15, 6, 4)
#define CTRR_A_UPR_EL2 ARM64_SYSREG(3, 4, 15, 6, 5)
#define CTRR_B_LWR_EL2 ARM64_SYSREG(3, 4, 15, 6, 6)
#define CTRR_B_UPR_EL2 ARM64_SYSREG(3, 4, 15, 6, 7)
#define SPRR_UMPRR_EL2 ARM64_SYSREG(3, 4, 15, 7, 0)
#define SPRR_UPERM_SH1_EL2 ARM64_SYSREG(3, 4, 15, 7, 1)
#define SPRR_UPERM_SH2_EL2 ARM64_SYSREG(3, 4, 15, 7, 2)
#define SPRR_UPERM_SH3_EL2 ARM64_SYSREG(3, 4, 15, 7, 3)
#define SPRR_HUPERM_SH04_EL2 ARM64_SYSREG(3, 4, 15, 7, 4)
#define SPRR_HUPERM_SH05_EL2 ARM64_SYSREG(3, 4, 15, 7, 5)
#define SPRR_HUPERM_SH06_EL2 ARM64_SYSREG(3, 4, 15, 7, 6)
#define SPRR_HUPERM_SH07_EL2 ARM64_SYSREG(3, 4, 15, 7, 7)
#define SPRR_UMPRR_EL12 ARM64_SYSREG(3, 4, 15, 8, 0)
#define SPRR_UPERM_SH1_EL12 ARM64_SYSREG(3, 4, 15, 8, 1)
#define SPRR_UPERM_SH2_EL12 ARM64_SYSREG(3, 4, 15, 8, 2)
#define SPRR_UPERM_SH3_EL12 ARM64_SYSREG(3, 4, 15, 8, 3)
#define SPRR_VUPERM_SH04_EL1 ARM64_SYSREG(3, 4, 15, 8, 4)
#define SPRR_VUPERM_SH05_EL1 ARM64_SYSREG(3, 4, 15, 8, 5)
#define SPRR_VUPERM_SH06_EL1 ARM64_SYSREG(3, 4, 15, 8, 6)
#define SPRR_VUPERM_SH07_EL1 ARM64_SYSREG(3, 4, 15, 8, 7)
#define CTRR_A_LWR_EL12 ARM64_SYSREG(3, 4, 15, 9, 0)
#define CTRR_A_UPR_EL12 ARM64_SYSREG(3, 4, 15, 9, 1)
#define CTRR_B_LWR_EL12 ARM64_SYSREG(3, 4, 15, 9, 2)
#define CTRR_B_UPR_EL12 ARM64_SYSREG(3, 4, 15, 9, 3)
#define CTRR_CTL_EL12 ARM64_SYSREG(3, 4, 15, 9, 4)
#define CTRR_LOCK_EL12 ARM64_SYSREG(3, 4, 15, 9, 5)
#define REDIR_ACNTKCTL_EL1 ARM64_SYSREG(3, 4, 15, 9, 6)
#define ACNTKCTL_EL12 ARM64_SYSREG(3, 4, 15, 9, 7)
#define PREDAKEYLo_EL1 ARM64_SYSREG(3, 4, 15, 10, 0)
#define PREDAKEYHi_EL1 ARM64_SYSREG(3, 4, 15, 10, 1)
#define PREDBKEYLo_EL1 ARM64_SYSREG(3, 4, 15, 10, 2)
#define PREDBKEYHi_EL1 ARM64_SYSREG(3, 4, 15, 10, 3)
#define SIQ_CFG_EL1 ARM64_SYSREG(3, 4, 15, 10, 4)
#define ACNTPCT_EL0 ARM64_SYSREG(3, 4, 15, 10, 5)
#define ACNTVCT_EL0 ARM64_SYSREG(3, 4, 15, 10, 6)
#define AVNCR_EL2 ARM64_SYSREG(3, 4, 15, 10, 7)
#define CTRR_A_LWR_EL2 ARM64_SYSREG(3, 4, 15, 11, 0)
#define CTRR_A_UPR_EL2 ARM64_SYSREG(3, 4, 15, 11, 1)
#define ACC_CTRR_B_LWR_EL2 ARM64_SYSREG(3, 4, 15, 11, 2)
#define ACC_CTRR_B_UPR_EL2 ARM64_SYSREG(3, 4, 15, 11, 3)
#define CTRR_CTL_EL2 ARM64_SYSREG(3, 4, 15, 11, 4)
#define CTRR_LOCK_EL2 ARM64_SYSREG(3, 4, 15, 11, 5)
#define REDIR_LCL_ACNTPCT_EL0 ARM64_SYSREG(3, 4, 15, 11, 6)
#define REDIR_LCL_ACNTVCT_EL0 ARM64_SYSREG(3, 4, 15, 11, 7)
#define ACFG_EL1 ARM64_SYSREG(3, 4, 15, 12, 0)
#define AHCR_EL2 ARM64_SYSREG(3, 4, 15, 12, 1)
#define APL_INTSTATUS_EL21 ARM64_SYSREG(3, 4, 15, 12, 2)
#define APL_INTSTATUS_EL2 ARM64_SYSREG(3, 4, 15, 12, 3)
#define IMPL_MSR_LOCK_EL21 ARM64_SYSREG(3, 4, 15, 12, 5)
#define REDIR_ACNTHCTL_EL2 ARM64_SYSREG(3, 4, 15, 12, 6)
#define IMPL_MSR_LOCK_EL2 ARM64_SYSREG(3, 4, 15, 12, 7)
#define JAPIAKeyLo_EL2 ARM64_SYSREG(3, 4, 15, 13, 0)
#define JAPIAKeyHi_EL2 ARM64_SYSREG(3, 4, 15, 13, 1)
#define JAPIBKeyLo_EL2 ARM64_SYSREG(3, 4, 15, 13, 2)
#define JAPIBKeyHi_EL2 ARM64_SYSREG(3, 4, 15, 13, 3)
#define JAPIAKeyLo_EL21 ARM64_SYSREG(3, 4, 15, 13, 4)
#define JAPIAKeyHi_EL21 ARM64_SYSREG(3, 4, 15, 13, 5)
#define JAPIBKeyLo_EL21 ARM64_SYSREG(3, 4, 15, 13, 6)
#define JAPIBKeyHi_EL21 ARM64_SYSREG(3, 4, 15, 13, 7)
#define JAPIAKeyLo_EL12 ARM64_SYSREG(3, 4, 15, 14, 0)
#define JAPIAKeyHi_EL12 ARM64_SYSREG(3, 4, 15, 14, 1)
#define JAPIBKeyLo_EL12 ARM64_SYSREG(3, 4, 15, 14, 2)
#define JAPIBKeyHi_EL12 ARM64_SYSREG(3, 4, 15, 14, 3)
#define ACNTRDIR_EL2 ARM64_SYSREG(3, 4, 15, 14, 5)
#define ACNTRDIR_EL12 ARM64_SYSREG(3, 4, 15, 14, 6)
#define JRANGE_EL2 ARM64_SYSREG(3, 4, 15, 15, 0)
#define JRANGE_EL21 ARM64_SYSREG(3, 4, 15, 15, 1)
#define JRANGE_EL12 ARM64_SYSREG(3, 4, 15, 15, 2)
#define JCTL_EL2 ARM64_SYSREG(3, 4, 15, 15, 3)
#define JCTL_EL21 ARM64_SYSREG(3, 4, 15, 15, 4)
#define JCTL_EL12 ARM64_SYSREG(3, 4, 15, 15, 5)
#define JCTL_EL0 ARM64_SYSREG(3, 4, 15, 15, 6)
#define AMDSCR_EL1 ARM64_SYSREG(3, 4, 15, 15, 7)
#define SCTLR_EL12 ARM64_SYSREG(3, 5, 1, 0, 0)
#define ACTLR_EL12 ARM64_SYSREG(3, 5, 1, 0, 1)
#define CPACR_EL12 ARM64_SYSREG(3, 5, 1, 0, 2)
#define SCTLR2_EL12 ARM64_SYSREG(3, 5, 1, 0, 3)
#define ZCR_EL12 ARM64_SYSREG(3, 5, 1, 2, 0)
#define TRFCR_EL12 ARM64_SYSREG(3, 5, 1, 2, 1)
#define TRCITECR_EL12 ARM64_SYSREG(3, 5, 1, 2, 3)
#define SMCR_EL12 ARM64_SYSREG(3, 5, 1, 2, 6)
#define TTBR0_EL12 ARM64_SYSREG(3, 5, 2, 0, 0)
#define TTBR1_EL12 ARM64_SYSREG(3, 5, 2, 0, 1)
#define TCR_EL12 ARM64_SYSREG(3, 5, 2, 0, 2)
#define TCR2_EL12 ARM64_SYSREG(3, 5, 2, 0, 3)
#define GCSCR_EL12 ARM64_SYSREG(3, 5, 2, 5, 0)
#define GCSPR_EL12 ARM64_SYSREG(3, 5, 2, 5, 1)
#define SPSR_EL12 ARM64_SYSREG(3, 5, 4, 0, 0)
#define ELR_EL12 ARM64_SYSREG(3, 5, 4, 0, 1)
#define AFSR0_EL12 ARM64_SYSREG(3, 5, 5, 1, 0)
#define AFSR1_EL12 ARM64_SYSREG(3, 5, 5, 1, 1)
#define ESR_EL12 ARM64_SYSREG(3, 5, 5, 2, 0)
#define TFSR_EL12 ARM64_SYSREG(3, 5, 5, 6, 0)
#define FAR_EL12 ARM64_SYSREG(3, 5, 6, 0, 0)
#define PFAR_EL12 ARM64_SYSREG(3, 5, 6, 0, 5)
#define PMSCR_EL12 ARM64_SYSREG(3, 5, 9, 9, 0)
#define MAIR_EL12 ARM64_SYSREG(3, 5, 10, 2, 0)
#define MAIR2_EL12 ARM64_SYSREG(3, 5, 10, 2, 1)
#define PIRE0_EL12 ARM64_SYSREG(3, 5, 10, 2, 2)
#define PIR_EL12 ARM64_SYSREG(3, 5, 10, 2, 3)
#define POR_EL12 ARM64_SYSREG(3, 5, 10, 2, 4)
#define AMAIR_EL12 ARM64_SYSREG(3, 5, 10, 3, 0)
#define AMAIR2_EL12 ARM64_SYSREG(3, 5, 10, 3, 1)
#define MPAM1_EL12 ARM64_SYSREG(3, 5, 10, 5, 0)
#define VBAR_EL12 ARM64_SYSREG(3, 5, 12, 0, 0)
#define CONTEXTIDR_EL12 ARM64_SYSREG(3, 5, 13, 0, 1)
#define SCXTNUM_EL12 ARM64_SYSREG(3, 5, 13, 0, 7)
#define CNTKCTL_EL12 ARM64_SYSREG(3, 5, 14, 1, 0)
#define CNTP_TVAL_EL02 ARM64_SYSREG(3, 5, 14, 2, 0)
#define CNTP_CTL_EL02 ARM64_SYSREG(3, 5, 14, 2, 1)
#define CNTP_CVAL_EL02 ARM64_SYSREG(3, 5, 14, 2, 2)
#define CNTV_TVAL_EL02 ARM64_SYSREG(3, 5, 14, 3, 0)
#define CNTV_CTL_EL02 ARM64_SYSREG(3, 5, 14, 3, 1)
#define CNTV_CVAL_EL02 ARM64_SYSREG(3, 5, 14, 3, 2)
#define IPI_RR_LOCAL_EL1 ARM64_SYSREG(3, 5, 15, 0, 0)
#define IPI_RR_GLOBAL_EL1 ARM64_SYSREG(3, 5, 15, 0, 1)
#define AF_ERR_CFG0 ARM64_SYSREG(3, 5, 15, 0, 2)
#define AP_ERR_CFG0 ARM64_SYSREG(3, 5, 15, 0, 3)
#define AF_ERR_SRC_IDS ARM64_SYSREG(3, 5, 15, 0, 4)
#define DPC_ERR_STS_EL1 ARM64_SYSREG(3, 5, 15, 0, 5)
#define DPC_ERR_CTL ARM64_SYSREG(3, 5, 15, 0, 6)
#define TRACE_CORE_CFG ARM64_SYSREG(3, 5, 15, 1, 0)
#define IPI_SR_EL1 ARM64_SYSREG(3, 5, 15, 1, 1)
#define VM_TMR_LR_EL2 ARM64_SYSREG(3, 5, 15, 1, 2)
#define VM_TMR_FIQ_ENA_EL2 ARM64_SYSREG(3, 5, 15, 1, 3)
#define KTRACE_MESSAGE ARM64_SYSREG(3, 5, 15, 1, 4)
#define TRACE_CORE_CFG_EXT ARM64_SYSREG(3, 5, 15, 1, 5)
#define WatchDogDiag0 ARM64_SYSREG(3, 5, 15, 1, 6)
#define WatchDogDiag1 ARM64_SYSREG(3, 5, 15, 1, 7)
#define DBG_WRAP_GLB ARM64_SYSREG(3, 5, 15, 2, 0)
#define TRACE_STREAM_BASE ARM64_SYSREG(3, 5, 15, 2, 1)
#define TRACE_STREAM_FILL ARM64_SYSREG(3, 5, 15, 2, 2)
#define TRACE_STREAM_BASE1 ARM64_SYSREG(3, 5, 15, 2, 3)
#define TRACE_STREAM_FILL1 ARM64_SYSREG(3, 5, 15, 2, 4)
#define TRACE_STREAM_IRQ ARM64_SYSREG(3, 5, 15, 2, 5)
#define AWL_SCRATCH_EL1 ARM64_SYSREG(3, 5, 15, 2, 6)
#define TRACE_AUX_CTL ARM64_SYSREG(3, 5, 15, 3, 0)
#define IPI_CR_EL1 ARM64_SYSREG(3, 5, 15, 3, 1)
#define UTRIG_EVENT ARM64_SYSREG(3, 5, 15, 3, 2)
#define TRACE_CTL ARM64_SYSREG(3, 5, 15, 3, 4)
#define TRACE_DAT ARM64_SYSREG(3, 5, 15, 3, 5)
#define ACC_CFG_EL1 ARM64_SYSREG(3, 5, 15, 4, 0)
#define PBLK_STS ARM64_SYSREG(3, 5, 15, 4, 1)
#define CYC_OVRD_EL1 ARM64_SYSREG(3, 5, 15, 5, 0)
#define PBLK_EXE_ST ARM64_SYSREG(3, 5, 15, 5, 2)
#define ACC_OVRD_EL1 ARM64_SYSREG(3, 5, 15, 6, 0)
#define ACC_EBLK_OVRD_EL1 ARM64_SYSREG(3, 5, 15, 6, 1)
#define CPM_PWRDN_CTL ARM64_SYSREG(3, 5, 15, 6, 2)
#define PRE_LLCFLUSH_TMR ARM64_SYSREG(3, 5, 15, 7, 0)
#define PRE_TD_TMR ARM64_SYSREG(3, 5, 15, 8, 0)
#define ACC_SLP_WAKE_UP_TMR ARM64_SYSREG(3, 5, 15, 8, 1)
#define PBLK_PSW_DLY ARM64_SYSREG(3, 5, 15, 9, 0)
#define CPU_STS ARM64_SYSREG(3, 5, 15, 10, 0)
#define HIST_TRIG ARM64_SYSREG(3, 5, 15, 10, 1)
#define ARRAY_INDEX ARM64_SYSREG(3, 5, 15, 11, 0)
#define IL1_DATA0 ARM64_SYSREG(3, 5, 15, 12, 0)
#define IL1_DATA1 ARM64_SYSREG(3, 5, 15, 12, 1)
#define DL1_DATA0 ARM64_SYSREG(3, 5, 15, 12, 2)
#define DL1_DATA1 ARM64_SYSREG(3, 5, 15, 12, 3)
#define MMUDATA0 ARM64_SYSREG(3, 5, 15, 12, 4)
#define MMUDATA1 ARM64_SYSREG(3, 5, 15, 12, 5)
#define LLC_DATA0 ARM64_SYSREG(3, 5, 15, 13, 4)
#define LLC_DATA1 ARM64_SYSREG(3, 5, 15, 13, 5)
#define SCTLR_EL3 ARM64_SYSREG(3, 6, 1, 0, 0)
#define ACTLR_EL3 ARM64_SYSREG(3, 6, 1, 0, 1)
#define SCTLR2_EL3 ARM64_SYSREG(3, 6, 1, 0, 3)
#define SCR_EL3 ARM64_SYSREG(3, 6, 1, 1, 0)
#define SDER32_EL3 ARM64_SYSREG(3, 6, 1, 1, 1)
#define CPTR_EL3 ARM64_SYSREG(3, 6, 1, 1, 2)
#define FGWTE3_EL3 ARM64_SYSREG(3, 6, 1, 1, 5)
#define ZCR_EL3 ARM64_SYSREG(3, 6, 1, 2, 0)
#define SMCR_EL3 ARM64_SYSREG(3, 6, 1, 2, 6)
#define MDCR_EL3 ARM64_SYSREG(3, 6, 1, 3, 1)
#define TTBR0_EL3 ARM64_SYSREG(3, 6, 2, 0, 0)
#define TCR_EL3 ARM64_SYSREG(3, 6, 2, 0, 2)
#define GPTBR_EL3 ARM64_SYSREG(3, 6, 2, 1, 4)
#define GPCCR_EL3 ARM64_SYSREG(3, 6, 2, 1, 6)
#define GCSCR_EL3 ARM64_SYSREG(3, 6, 2, 5, 0)
#define GCSPR_EL3 ARM64_SYSREG(3, 6, 2, 5, 1)
#define SPSR_EL3 ARM64_SYSREG(3, 6, 4, 0, 0)
#define ELR_EL3 ARM64_SYSREG(3, 6, 4, 0, 1)
#define SP_EL2 ARM64_SYSREG(3, 6, 4, 1, 0)
#define AFSR0_EL3 ARM64_SYSREG(3, 6, 5, 1, 0)
#define AFSR1_EL3 ARM64_SYSREG(3, 6, 5, 1, 1)
#define ESR_EL3 ARM64_SYSREG(3, 6, 5, 2, 0)
#define VSESR_EL3 ARM64_SYSREG(3, 6, 5, 2, 3)
#define TFSR_EL3 ARM64_SYSREG(3, 6, 5, 6, 0)
#define FAR_EL3 ARM64_SYSREG(3, 6, 6, 0, 0)
#define MFAR_EL3 ARM64_SYSREG(3, 6, 6, 0, 5)
#define MAIR2_EL3 ARM64_SYSREG(3, 6, 10, 1, 1)
#define MAIR_EL3 ARM64_SYSREG(3, 6, 10, 2, 0)
#define PIR_EL3 ARM64_SYSREG(3, 6, 10, 2, 3)
#define POR_EL3 ARM64_SYSREG(3, 6, 10, 2, 4)
#define AMAIR_EL3 ARM64_SYSREG(3, 6, 10, 3, 0)
#define AMAIR2_EL3 ARM64_SYSREG(3, 6, 10, 3, 1)
#define MPAM3_EL3 ARM64_SYSREG(3, 6, 10, 5, 0)
#define MECID_RL_A_EL3 ARM64_SYSREG(3, 6, 10, 10, 1)
#define VBAR_EL3 ARM64_SYSREG(3, 6, 12, 0, 0)
#define RVBAR_EL3 ARM64_SYSREG(3, 6, 12, 0, 1)
#define RMR_EL3 ARM64_SYSREG(3, 6, 12, 0, 2)
#define VDISR_EL3 ARM64_SYSREG(3, 6, 12, 1, 1)
#define ICC_CTLR_EL3 ARM64_SYSREG(3, 6, 12, 12, 4)
#define ICC_SRE_EL3 ARM64_SYSREG(3, 6, 12, 12, 5)
#define ICC_IGRPEN1_EL3 ARM64_SYSREG(3, 6, 12, 12, 7)
#define TPIDR_EL3 ARM64_SYSREG(3, 6, 13, 0, 2)
#define SCXTNUM_EL3 ARM64_SYSREG(3, 6, 13, 0, 7)
#define MMU_ERR_STS_EL1 ARM64_SYSREG(3, 6, 15, 0, 0)
#define AFSR1_GL1 ARM64_SYSREG(3, 6, 15, 0, 1)
#define AFSR1_GL2 ARM64_SYSREG(3, 6, 15, 0, 2)
#define AFSR1_GL12 ARM64_SYSREG(3, 6, 15, 0, 3)
#define BP_OBJC_ADR_EL1 ARM64_SYSREG(3, 6, 15, 0, 4)
#define BP_OBJC_CTL_EL1 ARM64_SYSREG(3, 6, 15, 0, 5)
#define SP_GL11_GL21 ARM64_SYSREG(3, 6, 15, 0, 6)
#define MMU_SESR_EL2 ARM64_SYSREG(3, 6, 15, 0, 7)
#define SPRR_CONFIG_EL1 ARM64_SYSREG(3, 6, 15, 1, 0)
#define HPFAR_GL2 ARM64_SYSREG(3, 6, 15, 1, 1)
#define GXF_CONFIG_EL1 ARM64_SYSREG(3, 6, 15, 1, 2)
#define SPRR_AMRANGE_EL1 ARM64_SYSREG(3, 6, 15, 1, 3)
#define GXF_CONFIG_EL2 ARM64_SYSREG(3, 6, 15, 1, 4)
#define SPRR_UPERM_EL0 ARM64_SYSREG(3, 6, 15, 1, 5)
#define SPRR_PPERM_EL1 ARM64_SYSREG(3, 6, 15, 1, 6)
#define SPRR_PPERM_EL2 ARM64_SYSREG(3, 6, 15, 1, 7)
#define E_MMU_ERR_STS_EL1 ARM64_SYSREG(3, 6, 15, 2, 0)
#define APGAKeyLo_EL12 ARM64_SYSREG(3, 6, 15, 2, 1)
#define APGAKeyHi_EL12 ARM64_SYSREG(3, 6, 15, 2, 2)
#define KERNKEYLO_EL12 ARM64_SYSREG(3, 6, 15, 2, 3)
#define KERNKEYHI_EL12 ARM64_SYSREG(3, 6, 15, 2, 4)
#define AFPCR_EL0 ARM64_SYSREG(3, 6, 15, 2, 5)
#define SP_GL22 ARM64_SYSREG(3, 6, 15, 2, 6)
#define AIDR2_EL1 ARM64_SYSREG(3, 6, 15, 2, 7)
#define SPRR_UMPRR_EL1 ARM64_SYSREG(3, 6, 15, 3, 0)
#define SPRR_PMPRR_EL1 ARM64_SYSREG(3, 6, 15, 3, 1)
#define SPRR_PMPRR_EL2 ARM64_SYSREG(3, 6, 15, 3, 2)
#define SPRR_UPERM_SH1_EL1 ARM64_SYSREG(3, 6, 15, 3, 3)
#define SPRR_UPERM_SH2_EL1 ARM64_SYSREG(3, 6, 15, 3, 4)
#define SPRR_UPERM_SH3_EL1 ARM64_SYSREG(3, 6, 15, 3, 5)
#define SPRR_UPERM_SH04_EL1 ARM64_SYSREG(3, 6, 15, 3, 6)
#define SPRR_UPERM_SH05_EL1 ARM64_SYSREG(3, 6, 15, 3, 7)
#define SPRR_UPERM_SH06_EL1 ARM64_SYSREG(3, 6, 15, 4, 0)
#define SPRR_UPERM_SH07_EL1 ARM64_SYSREG(3, 6, 15, 4, 1)
#define SPRR_PPERM_SH1_EL1 ARM64_SYSREG(3, 6, 15, 4, 2)
#define SPRR_PPERM_SH2_EL1 ARM64_SYSREG(3, 6, 15, 4, 3)
#define SPRR_PPERM_SH3_EL1 ARM64_SYSREG(3, 6, 15, 4, 4)
#define SPRR_PPERM_SH04_EL21 ARM64_SYSREG(3, 6, 15, 4, 5)
#define SPRR_PPERM_SH05_EL21 ARM64_SYSREG(3, 6, 15, 4, 6)
#define SPRR_PPERM_SH06_EL21 ARM64_SYSREG(3, 6, 15, 4, 7)
#define SPRR_PPERM_SH07_EL21 ARM64_SYSREG(3, 6, 15, 5, 0)
#define SPRR_PPERM_SH1_EL2 ARM64_SYSREG(3, 6, 15, 5, 1)
#define SPRR_PPERM_SH2_EL2 ARM64_SYSREG(3, 6, 15, 5, 2)
#define SPRR_PPERM_SH3_EL2 ARM64_SYSREG(3, 6, 15, 5, 3)
#define SPRR_PPERM_SH04_EL2 ARM64_SYSREG(3, 6, 15, 5, 4)
#define SPRR_PPERM_SH05_EL2 ARM64_SYSREG(3, 6, 15, 5, 5)
#define SPRR_PPERM_SH06_EL2 ARM64_SYSREG(3, 6, 15, 5, 6)
#define SPRR_PPERM_SH07_EL2 ARM64_SYSREG(3, 6, 15, 5, 7)
#define SPRR_PMPRR_EL12 ARM64_SYSREG(3, 6, 15, 6, 0)
#define SPRR_PPERM_SH1_EL12 ARM64_SYSREG(3, 6, 15, 6, 1)
#define SPRR_PPERM_SH2_EL12 ARM64_SYSREG(3, 6, 15, 6, 2)
#define SPRR_PPERM_SH3_EL12 ARM64_SYSREG(3, 6, 15, 6, 3)
#define SPRR_PPERM_SH04_EL12 ARM64_SYSREG(3, 6, 15, 6, 4)
#define SPRR_PPERM_SH05_EL12 ARM64_SYSREG(3, 6, 15, 6, 5)
#define SPRR_PPERM_SH06_EL12 ARM64_SYSREG(3, 6, 15, 6, 6)
#define SPRR_PPERM_SH07_EL12 ARM64_SYSREG(3, 6, 15, 6, 7)
#define APIAKeyLo_EL12 ARM64_SYSREG(3, 6, 15, 7, 0)
#define APIAKeyHi_EL12 ARM64_SYSREG(3, 6, 15, 7, 1)
#define APIBKeyLo_EL12 ARM64_SYSREG(3, 6, 15, 7, 2)
#define APIBKeyHi_EL12 ARM64_SYSREG(3, 6, 15, 7, 3)
#define APDAKeyLo_EL12 ARM64_SYSREG(3, 6, 15, 7, 4)
#define APDAKeyHi_EL12 ARM64_SYSREG(3, 6, 15, 7, 5)
#define APDBKeyLo_EL12 ARM64_SYSREG(3, 6, 15, 7, 6)
#define APDBKeyHi_EL12 ARM64_SYSREG(3, 6, 15, 7, 7)
#define GXF_STATUS_EL1 ARM64_SYSREG(3, 6, 15, 8, 0)
#define GXF_ENTRY_EL1 ARM64_SYSREG(3, 6, 15, 8, 1)
#define GXF_PABENTRY_EL1 ARM64_SYSREG(3, 6, 15, 8, 2)
#define ASPSR_EL1 ARM64_SYSREG(3, 6, 15, 8, 3)
#define ADSPSR_EL0 ARM64_SYSREG(3, 6, 15, 8, 4)
#define PMCR1_GL2 ARM64_SYSREG(3, 6, 15, 8, 5)
#define ASPSR_EL2 ARM64_SYSREG(3, 6, 15, 8, 6)
#define PMCR1_GL21 ARM64_SYSREG(3, 6, 15, 8, 7)
#define VBAR_GL12 ARM64_SYSREG(3, 6, 15, 9, 2)
#define SPSR_GL12 ARM64_SYSREG(3, 6, 15, 9, 3)
#define ASPSR_GL12 ARM64_SYSREG(3, 6, 15, 9, 4)
#define ESR_GL12 ARM64_SYSREG(3, 6, 15, 9, 5)
#define ELR_GL12 ARM64_SYSREG(3, 6, 15, 9, 6)
#define FAR_GL12 ARM64_SYSREG(3, 6, 15, 9, 7)
#define SP_GL12 ARM64_SYSREG(3, 6, 15, 10, 0)
#define TPIDR_GL1 ARM64_SYSREG(3, 6, 15, 10, 1)
#define VBAR_GL1 ARM64_SYSREG(3, 6, 15, 10, 2)
#define SPSR_GL1 ARM64_SYSREG(3, 6, 15, 10, 3)
#define ASPSR_GL1 ARM64_SYSREG(3, 6, 15, 10, 4)
#define ESR_GL1 ARM64_SYSREG(3, 6, 15, 10, 5)
#define ELR_GL1 ARM64_SYSREG(3, 6, 15, 10, 6)
#define FAR_GL1 ARM64_SYSREG(3, 6, 15, 10, 7)
#define SP_GL2 ARM64_SYSREG(3, 6, 15, 11, 0)
#define TPIDR_GL2 ARM64_SYSREG(3, 6, 15, 11, 1)
#define VBAR_GL2 ARM64_SYSREG(3, 6, 15, 11, 2)
#define SPSR_GL2 ARM64_SYSREG(3, 6, 15, 11, 3)
#define ASPSR_GL2 ARM64_SYSREG(3, 6, 15, 11, 4)
#define ESR_GL2 ARM64_SYSREG(3, 6, 15, 11, 5)
#define ELR_GL2 ARM64_SYSREG(3, 6, 15, 11, 6)
#define FAR_GL2 ARM64_SYSREG(3, 6, 15, 11, 7)
#define GXF_ENTRY_EL2 ARM64_SYSREG(3, 6, 15, 12, 0)
#define GXF_PABENTRY_EL2 ARM64_SYSREG(3, 6, 15, 12, 1)
#define APCTL_EL2 ARM64_SYSREG(3, 6, 15, 12, 2)
#define APSTS_EL2_MAYBE ARM64_SYSREG(3, 6, 15, 12, 3)
#define APSTS_EL1 ARM64_SYSREG(3, 6, 15, 12, 4)
#define KERNKEYLo_EL2 ARM64_SYSREG(3, 6, 15, 12, 5)
#define KERNKEYHi_EL2 ARM64_SYSREG(3, 6, 15, 12, 6)
#define ASPSR_EL12 ARM64_SYSREG(3, 6, 15, 12, 7)
#define APIAKeyLo_EL2 ARM64_SYSREG(3, 6, 15, 13, 0)
#define APIAKeyHi_EL2 ARM64_SYSREG(3, 6, 15, 13, 1)
#define APIBKeyLo_EL2 ARM64_SYSREG(3, 6, 15, 13, 2)
#define APIBKeyHi_EL2 ARM64_SYSREG(3, 6, 15, 13, 3)
#define APDAKeyLo_EL2 ARM64_SYSREG(3, 6, 15, 13, 4)
#define APDAKeyHi_EL2 ARM64_SYSREG(3, 6, 15, 13, 5)
#define APDBKeyLo_EL2 ARM64_SYSREG(3, 6, 15, 13, 6)
#define APDBKeyHi_EL2 ARM64_SYSREG(3, 6, 15, 13, 7)
#define APGAKeyLo_EL2 ARM64_SYSREG(3, 6, 15, 14, 0)
#define APGAKeyHi_EL2 ARM64_SYSREG(3, 6, 15, 14, 1)
#define SPRR_CONFIG_EL2 ARM64_SYSREG(3, 6, 15, 14, 2)
#define SPRR_AMRANGE_EL2 ARM64_SYSREG(3, 6, 15, 14, 3)
#define VMKEYLO_EL2 ARM64_SYSREG(3, 6, 15, 14, 4)
#define VMKEYHI_EL2 ARM64_SYSREG(3, 6, 15, 14, 5)
#define ACTLR_EL12 ARM64_SYSREG(3, 6, 15, 14, 6)
#define APSTS_EL12 ARM64_SYSREG(3, 6, 15, 14, 7)
#define APCTL_EL12 ARM64_SYSREG(3, 6, 15, 15, 0)
#define GXF_CONFIG_EL12 ARM64_SYSREG(3, 6, 15, 15, 1)
#define GXF_ENTRY_EL12 ARM64_SYSREG(3, 6, 15, 15, 2)
#define GXF_PABENTRY_EL12 ARM64_SYSREG(3, 6, 15, 15, 3)
#define SPRR_CONFIG_EL12 ARM64_SYSREG(3, 6, 15, 15, 4)
#define SPRR_AMRANGE_EL12 ARM64_SYSREG(3, 6, 15, 15, 5)
#define MMU_SESR_CTL_EL2 ARM64_SYSREG(3, 6, 15, 15, 6)
#define SPRR_PPERM_EL12 ARM64_SYSREG(3, 6, 15, 15, 7)
#define CNTPS_TVAL_EL1 ARM64_SYSREG(3, 7, 14, 2, 0)
#define CNTPS_CTL_EL1 ARM64_SYSREG(3, 7, 14, 2, 1)
#define CNTPS_CVAL_EL1 ARM64_SYSREG(3, 7, 14, 2, 2)
#define PWRDNSAVE0 ARM64_SYSREG(3, 7, 15, 0, 0)
#define NRG_ACC_CTL ARM64_SYSREG(3, 7, 15, 0, 1)
#define AON_CNT0 ARM64_SYSREG(3, 7, 15, 0, 2)
#define CPU_CNT0 ARM64_SYSREG(3, 7, 15, 0, 3)
#define UPMCR0_EL1 ARM64_SYSREG(3, 7, 15, 0, 4)
#define UPMC8_EL1 ARM64_SYSREG(3, 7, 15, 0, 5)
#define PWRDNSAVE1 ARM64_SYSREG(3, 7, 15, 1, 0)
#define CORE_NRG_ACC_DAT ARM64_SYSREG(3, 7, 15, 1, 1)
#define AON_CNT_CTL0 ARM64_SYSREG(3, 7, 15, 1, 2)
#define CPU_CNT_CTL0 ARM64_SYSREG(3, 7, 15, 1, 3)
#define UPMESR0_EL1 ARM64_SYSREG(3, 7, 15, 1, 4)
#define UPMC9_EL1 ARM64_SYSREG(3, 7, 15, 1, 5)
#define ACC_PWR_DN_SAVE ARM64_SYSREG(3, 7, 15, 2, 0)
#define CPM_NRG_ACC_DAT ARM64_SYSREG(3, 7, 15, 2, 1)
#define AON_CNT1 ARM64_SYSREG(3, 7, 15, 2, 2)
#define CPU_CNT1 ARM64_SYSREG(3, 7, 15, 2, 3)
#define UPMSWCTRL_EL1 ARM64_SYSREG(3, 7, 15, 2, 4)
#define UPMC10_EL1 ARM64_SYSREG(3, 7, 15, 2, 5)
#define CORE_SRM_NRG_ACC_DAT ARM64_SYSREG(3, 7, 15, 3, 1)
#define AON_CNT_CTL1 ARM64_SYSREG(3, 7, 15, 3, 2)
#define CPU_CNT_CTL1 ARM64_SYSREG(3, 7, 15, 3, 3)
#define UPMECM0_EL1 ARM64_SYSREG(3, 7, 15, 3, 4)
#define UPMC11_EL1 ARM64_SYSREG(3, 7, 15, 3, 5)
#define AON_CNT_CTL ARM64_SYSREG(3, 7, 15, 4, 0)
#define CPM_SRM_NRG_ACC_DAT ARM64_SYSREG(3, 7, 15, 4, 1)
#define AON_CNT2 ARM64_SYSREG(3, 7, 15, 4, 2)
#define CPU_CNT2 ARM64_SYSREG(3, 7, 15, 4, 3)
#define UPMECM1_EL1 ARM64_SYSREG(3, 7, 15, 4, 4)
#define UPMC12_EL1 ARM64_SYSREG(3, 7, 15, 4, 5)
#define CPU_CNT_CTL ARM64_SYSREG(3, 7, 15, 5, 0)
#define AON_CNT_CTL2 ARM64_SYSREG(3, 7, 15, 5, 2)
#define CPU_CNT_CTL2 ARM64_SYSREG(3, 7, 15, 5, 3)
#define UPMPCM_EL1 ARM64_SYSREG(3, 7, 15, 5, 4)
#define UPMC13_EL1 ARM64_SYSREG(3, 7, 15, 5, 5)
#define AON_CNT3 ARM64_SYSREG(3, 7, 15, 6, 2)
#define CPU_CNT3 ARM64_SYSREG(3, 7, 15, 6, 3)
#define UPMSR_EL1 ARM64_SYSREG(3, 7, 15, 6, 4)
#define UPMC14_EL1 ARM64_SYSREG(3, 7, 15, 6, 5)
#define AON_CNT_CTL3 ARM64_SYSREG(3, 7, 15, 7, 2)
#define CPU_CNT_CTL3 ARM64_SYSREG(3, 7, 15, 7, 3)
#define UPMC0_EL1 ARM64_SYSREG(3, 7, 15, 7, 4)
#define UPMC15_EL1 ARM64_SYSREG(3, 7, 15, 7, 5)
#define AON_CNT4 ARM64_SYSREG(3, 7, 15, 8, 2)
#define CPU_CNT4 ARM64_SYSREG(3, 7, 15, 8, 3)
#define UPMC1_EL1 ARM64_SYSREG(3, 7, 15, 8, 4)
#define UPMECM2_EL1 ARM64_SYSREG(3, 7, 15, 8, 5)
#define AON_CNT_CTL4 ARM64_SYSREG(3, 7, 15, 9, 2)
#define CPU_CNT_CTL4 ARM64_SYSREG(3, 7, 15, 9, 3)
#define UPMC2_EL1 ARM64_SYSREG(3, 7, 15, 9, 4)
#define UPMECM3_EL1 ARM64_SYSREG(3, 7, 15, 9, 5)
#define AON_CNT5 ARM64_SYSREG(3, 7, 15, 10, 2)
#define CPU_CNT5 ARM64_SYSREG(3, 7, 15, 10, 3)
#define UPMC3_EL1 ARM64_SYSREG(3, 7, 15, 10, 4)
#define UPMCR1_EL1 ARM64_SYSREG(3, 7, 15, 10, 5)
#define AON_CNT_CTL5 ARM64_SYSREG(3, 7, 15, 11, 2)
#define CPU_CNT_CTL5 ARM64_SYSREG(3, 7, 15, 11, 3)
#define UPMC4_EL1 ARM64_SYSREG(3, 7, 15, 11, 4)
#define UPMESR1_EL1 ARM64_SYSREG(3, 7, 15, 11, 5)
#define AON_CNT6 ARM64_SYSREG(3, 7, 15, 12, 2)
#define CPU_CNT6 ARM64_SYSREG(3, 7, 15, 12, 3)
#define UPMC5_EL1 ARM64_SYSREG(3, 7, 15, 12, 4)
#define AON_CNT_CTL6 ARM64_SYSREG(3, 7, 15, 13, 2)
#define CPU_CNT_CTL6 ARM64_SYSREG(3, 7, 15, 13, 3)
#define UPMC6_EL1 ARM64_SYSREG(3, 7, 15, 13, 4)
#define AON_CNT7 ARM64_SYSREG(3, 7, 15, 14, 2)
#define CPU_CNT7 ARM64_SYSREG(3, 7, 15, 14, 3)
#define UPMC7_EL1 ARM64_SYSREG(3, 7, 15, 14, 4)
#define AON_CNT_CTL7 ARM64_SYSREG(3, 7, 15, 15, 2)
#define CPU_CNT_CTL7 ARM64_SYSREG(3, 7, 15, 15, 3)
#define ALLINT ARM64_SYSREG(0, 1, 0, 0, 0)
#define PM ARM64_SYSREG(0, 1, 0, 2, 0)
#define SVCRSM ARM64_SYSREG(0, 3, 0, 2, 3)
#define SVCRZA ARM64_SYSREG(0, 3, 0, 4, 3)
#define SVCRSMZA ARM64_SYSREG(0, 3, 0, 6, 3)