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|
Version:
9.1~250226-1.fc41 ▾
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; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;---------------------------------
; Infineon C166V2 SPECIFIC LINES
;---------------------------------
;
; the processor definition may include the memory configuration.
; the line format is:
; area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
; START and END are addresses, the end address is not included
; Interrupt vectors are declared in the following way:
; entry NAME ADDRESS COMMENT
.default XC161CJ
.C166V2_core
; c166sv2um.pdf
; MEMORY MAP
area DATA MEM_EXT 0x0000:0x8000 External Memory
area DATA SRAM 0x8000:0xE000 Internal SRAM
area DATA INT_IO 0xE000:0xF000 internal-IO Area
area DATA E_SFR 0xF000:0xF200 ESFR Area
area DATA DPRAM 0xF200:0xFE00 DPRAM
area DATA SFR 0xFE00:0x10000 SFR Area
; Interrupt and reset vector assignments
entry RESET 0x0000 Reset
entry NMITRAP 0x0008 Non maskable interrupt
entry STOTRAP 0x0010 Stack overflow
entry STUTRAP 0x0018 Stack underflow
entry SBRKTRAP 0x0020 Software Break
entry BTRAP 0x0028 Class B Trap
; INPUT/OUTPUT PORTS
FINT0CSP 0xEC00 Fast Interrupt 0 CSP Register
FINT0CSP.EN 15 Fast Interrupt Enable
FINT0CSP.GPX 12 Group Priority Extension
FINT0CSP.ILVL_11 11 Interrupt Priority Level - bit 1
FINT0CSP.ILVL_10 10 Interrupt Priority Level - bit 10
FINT0CSP.GLVL_9 9 Group Priority Level - bit 9
FINT0CSP.GLVL_8 8 Group Priority Level - bit 8
FINT0CSP.SEG_7 7 Segment Number of Interrupt Service Routine - bit 7
FINT0CSP.SEG_6 6 Segment Number of Interrupt Service Routine - bit 6
FINT0CSP.SEG_5 5 Segment Number of Interrupt Service Routine - bit 5
FINT0CSP.SEG_4 4 Segment Number of Interrupt Service Routine - bit 4
FINT0CSP.SEG_3 3 Segment Number of Interrupt Service Routine - bit 3
FINT0CSP.SEG_2 2 Segment Number of Interrupt Service Routine - bit 2
FINT0CSP.SEG_1 1 Segment Number of Interrupt Service Routine - bit 1
FINT0CSP.SEG_0 0 Segment Number of Interrupt Service Routine - bit 0
FINT0ADDR 0xEC02 Fast Interrupt 0 Address Register
FINT1CSP 0xEC04 Fast Interrupt 1 CSP Register
FINT1CSP.EN 15 Fast Interrupt Enable
FINT1CSP.GPX 12 Group Priority Extension
FINT1CSP.ILVL_11 11 Interrupt Priority Level - bit 1
FINT1CSP.ILVL_10 10 Interrupt Priority Level - bit 10
FINT1CSP.GLVL_9 9 Group Priority Level - bit 9
FINT1CSP.GLVL_8 8 Group Priority Level - bit 8
FINT1CSP.SEG_7 7 Segment Number of Interrupt Service Routine - bit 7
FINT1CSP.SEG_6 6 Segment Number of Interrupt Service Routine - bit 6
FINT1CSP.SEG_5 5 Segment Number of Interrupt Service Routine - bit 5
FINT1CSP.SEG_4 4 Segment Number of Interrupt Service Routine - bit 4
FINT1CSP.SEG_3 3 Segment Number of Interrupt Service Routine - bit 3
FINT1CSP.SEG_2 2 Segment Number of Interrupt Service Routine - bit 2
FINT1CSP.SEG_1 1 Segment Number of Interrupt Service Routine - bit 1
FINT1CSP.SEG_0 0 Segment Number of Interrupt Service Routine - bit 0
FINT1ADDR 0xEC06 Fast Interrupt 1 Address Register
BNKSEL0 0xEC20 Bank Selection Register 0
BNKSEL0.GPRSEL7_15 15 Register Bank Selection - bit 7_15
BNKSEL0.GPRSEL7_14 14 Register Bank Selection - bit 7_14
BNKSEL0.GPRSEL6_13 13 Register Bank Selection - bit 6_13
BNKSEL0.GPRSEL6_12 12 Register Bank Selection - bit 6_12
BNKSEL0.GPRSEL5_11 11 Register Bank Selection - bit 5_11
BNKSEL0.GPRSEL5_10 10 Register Bank Selection - bit 5_10
BNKSEL0.GPRSEL4_9 9 Register Bank Selection - bit 4_9
BNKSEL0.GPRSEL4_8 8 Register Bank Selection - bit 4_8
BNKSEL0.GPRSEL3_7 7 Register Bank Selection - bit 3_7
BNKSEL0.GPRSEL3_6 6 Register Bank Selection - bit 3_6
BNKSEL0.GPRSEL2_5 5 Register Bank Selection - bit 2_5
BNKSEL0.GPRSEL2_4 4 Register Bank Selection - bit 2_4
BNKSEL0.GPRSEL1_3 3 Register Bank Selection - bit 1_3
BNKSEL0.GPRSEL1_2 2 Register Bank Selection - bit 1_2
BNKSEL0.GPRSEL0_1 1 Register Bank Selection - bit 0_1
BNKSEL0.GPRSEL0_0 0 Register Bank Selection - bit 0_0
BNKSEL1 0xEC22 Bank Selection Register 1
BNKSEL1.GPRSEL7_15 15 Register Bank Selection - bit 7_15
BNKSEL1.GPRSEL7_14 14 Register Bank Selection - bit 7_14
BNKSEL1.GPRSEL6_13 13 Register Bank Selection - bit 6_13
BNKSEL1.GPRSEL6_12 12 Register Bank Selection - bit 6_12
BNKSEL1.GPRSEL5_11 11 Register Bank Selection - bit 5_11
BNKSEL1.GPRSEL5_10 10 Register Bank Selection - bit 5_10
BNKSEL1.GPRSEL4_9 9 Register Bank Selection - bit 4_9
BNKSEL1.GPRSEL4_8 8 Register Bank Selection - bit 4_8
BNKSEL1.GPRSEL3_7 7 Register Bank Selection - bit 3_7
BNKSEL1.GPRSEL3_6 6 Register Bank Selection - bit 3_6
BNKSEL1.GPRSEL2_5 5 Register Bank Selection - bit 2_5
BNKSEL1.GPRSEL2_4 4 Register Bank Selection - bit 2_4
BNKSEL1.GPRSEL1_3 3 Register Bank Selection - bit 1_3
BNKSEL1.GPRSEL1_2 2 Register Bank Selection - bit 1_2
BNKSEL1.GPRSEL0_1 1 Register Bank Selection - bit 0_1
BNKSEL1.GPRSEL0_0 0 Register Bank Selection - bit 0_0
BNKSEL2 0xEC24 Bank Selection Register 2
BNKSEL2.GPRSEL7_15 15 Register Bank Selection - bit 7_15
BNKSEL2.GPRSEL7_14 14 Register Bank Selection - bit 7_14
BNKSEL2.GPRSEL6_13 13 Register Bank Selection - bit 6_13
BNKSEL2.GPRSEL6_12 12 Register Bank Selection - bit 6_12
BNKSEL2.GPRSEL5_11 11 Register Bank Selection - bit 5_11
BNKSEL2.GPRSEL5_10 10 Register Bank Selection - bit 5_10
BNKSEL2.GPRSEL4_9 9 Register Bank Selection - bit 4_9
BNKSEL2.GPRSEL4_8 8 Register Bank Selection - bit 4_8
BNKSEL2.GPRSEL3_7 7 Register Bank Selection - bit 3_7
BNKSEL2.GPRSEL3_6 6 Register Bank Selection - bit 3_6
BNKSEL2.GPRSEL2_5 5 Register Bank Selection - bit 2_5
BNKSEL2.GPRSEL2_4 4 Register Bank Selection - bit 2_4
BNKSEL2.GPRSEL1_3 3 Register Bank Selection - bit 1_3
BNKSEL2.GPRSEL1_2 2 Register Bank Selection - bit 1_2
BNKSEL2.GPRSEL0_1 1 Register Bank Selection - bit 0_1
BNKSEL2.GPRSEL0_0 0 Register Bank Selection - bit 0_0
BNKSEL3 0xEC26 Bank Selection Register 3
BNKSEL3.GPRSEL7_15 15 Register Bank Selection - bit 7_15
BNKSEL3.GPRSEL7_14 14 Register Bank Selection - bit 7_14
BNKSEL3.GPRSEL6_13 13 Register Bank Selection - bit 6_13
BNKSEL3.GPRSEL6_12 12 Register Bank Selection - bit 6_12
BNKSEL3.GPRSEL5_11 11 Register Bank Selection - bit 5_11
BNKSEL3.GPRSEL5_10 10 Register Bank Selection - bit 5_10
BNKSEL3.GPRSEL4_9 9 Register Bank Selection - bit 4_9
BNKSEL3.GPRSEL4_8 8 Register Bank Selection - bit 4_8
BNKSEL3.GPRSEL3_7 7 Register Bank Selection - bit 3_7
BNKSEL3.GPRSEL3_6 6 Register Bank Selection - bit 3_6
BNKSEL3.GPRSEL2_5 5 Register Bank Selection - bit 2_5
BNKSEL3.GPRSEL2_4 4 Register Bank Selection - bit 2_4
BNKSEL3.GPRSEL1_3 3 Register Bank Selection - bit 1_3
BNKSEL3.GPRSEL1_2 2 Register Bank Selection - bit 1_2
BNKSEL3.GPRSEL0_1 1 Register Bank Selection - bit 0_1
BNKSEL3.GPRSEL0_0 0 Register Bank Selection - bit 0_0
SRCP0 0xEC40 PEC Channel 0 Source Pointer
SRCP0.SRCP0_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP0.SRCP0_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP0.SRCP0_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP0.SRCP0_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP0.SRCP0_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP0.SRCP0_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP0.SRCP0_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP0.SRCP0_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP0.SRCP0_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP0.SRCP0_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP0.SRCP0_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP0.SRCP0_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP0.SRCP0_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP0.SRCP0_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP0.SRCP0_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP0.SRCP0_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP0 0xEC42 PEC Channel 0 Destination Pointer
DSTP0.DSTP0_15 15 Destination Pointer Address of Channel 0 - bit 15
DSTP0.DSTP0_14 14 Destination Pointer Address of Channel 0 - bit 14
DSTP0.DSTP0_13 13 Destination Pointer Address of Channel 0 - bit 13
DSTP0.DSTP0_12 12 Destination Pointer Address of Channel 0 - bit 12
DSTP0.DSTP0_11 11 Destination Pointer Address of Channel 0 - bit 11
DSTP0.DSTP0_10 10 Destination Pointer Address of Channel 0 - bit 10
DSTP0.DSTP0_9 9 Destination Pointer Address of Channel 0 - bit 9
DSTP0.DSTP0_8 8 Destination Pointer Address of Channel 0 - bit 8
DSTP0.DSTP0_7 7 Destination Pointer Address of Channel 0 - bit 7
DSTP0.DSTP0_6 6 Destination Pointer Address of Channel 0 - bit 6
DSTP0.DSTP0_5 5 Destination Pointer Address of Channel 0 - bit 5
DSTP0.DSTP0_4 4 Destination Pointer Address of Channel 0 - bit 4
DSTP0.DSTP0_3 3 Destination Pointer Address of Channel 0 - bit 3
DSTP0.DSTP0_2 2 Destination Pointer Address of Channel 0 - bit 2
DSTP0.DSTP0_1 1 Destination Pointer Address of Channel 0 - bit 1
DSTP0.DSTP0_0 0 Destination Pointer Address of Channel 0 - bit 0
SRCP1 0xEC44 PEC Channel 1 Source Pointer
SRCP1.SRCP1_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP1.SRCP1_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP1.SRCP1_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP1.SRCP1_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP1.SRCP1_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP1.SRCP1_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP1.SRCP1_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP1.SRCP1_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP1.SRCP1_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP1.SRCP1_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP1.SRCP1_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP1.SRCP1_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP1.SRCP1_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP1.SRCP1_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP1.SRCP1_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP1.SRCP1_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP1 0xEC46 PEC Channel 1 Destination Pointer
DSTP1.DSTP1_15 15 Destination Pointer Address of Channel 1 - bit 15
DSTP1.DSTP1_14 14 Destination Pointer Address of Channel 1 - bit 14
DSTP1.DSTP1_13 13 Destination Pointer Address of Channel 1 - bit 13
DSTP1.DSTP1_12 12 Destination Pointer Address of Channel 1 - bit 12
DSTP1.DSTP1_11 11 Destination Pointer Address of Channel 1 - bit 11
DSTP1.DSTP1_10 10 Destination Pointer Address of Channel 1 - bit 10
DSTP1.DSTP1_9 9 Destination Pointer Address of Channel 1 - bit 9
DSTP1.DSTP1_8 8 Destination Pointer Address of Channel 1 - bit 8
DSTP1.DSTP1_7 7 Destination Pointer Address of Channel 1 - bit 7
DSTP1.DSTP1_6 6 Destination Pointer Address of Channel 1 - bit 6
DSTP1.DSTP1_5 5 Destination Pointer Address of Channel 1 - bit 5
DSTP1.DSTP1_4 4 Destination Pointer Address of Channel 1 - bit 4
DSTP1.DSTP1_3 3 Destination Pointer Address of Channel 1 - bit 3
DSTP1.DSTP1_2 2 Destination Pointer Address of Channel 1 - bit 2
DSTP1.DSTP1_1 1 Destination Pointer Address of Channel 1 - bit 1
DSTP1.DSTP1_0 0 Destination Pointer Address of Channel 1 - bit 0
SRCP2 0xEC48 PEC Channel 2 Source Pointer
SRCP2.SRCP2_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP2.SRCP2_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP2.SRCP2_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP2.SRCP2_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP2.SRCP2_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP2.SRCP2_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP2.SRCP2_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP2.SRCP2_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP2.SRCP2_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP2.SRCP2_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP2.SRCP2_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP2.SRCP2_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP2.SRCP2_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP2.SRCP2_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP2.SRCP2_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP2.SRCP2_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP2 0xEC4A PEC Channel 2 Destination Pointer
DSTP2.DSTP2_15 15 Destination Pointer Address of Channel 2 - bit 15
DSTP2.DSTP2_14 14 Destination Pointer Address of Channel 2 - bit 14
DSTP2.DSTP2_13 13 Destination Pointer Address of Channel 2 - bit 13
DSTP2.DSTP2_12 12 Destination Pointer Address of Channel 2 - bit 12
DSTP2.DSTP2_11 11 Destination Pointer Address of Channel 2 - bit 11
DSTP2.DSTP2_10 10 Destination Pointer Address of Channel 2 - bit 10
DSTP2.DSTP2_9 9 Destination Pointer Address of Channel 2 - bit 9
DSTP2.DSTP2_8 8 Destination Pointer Address of Channel 2 - bit 8
DSTP2.DSTP2_7 7 Destination Pointer Address of Channel 2 - bit 7
DSTP2.DSTP2_6 6 Destination Pointer Address of Channel 2 - bit 6
DSTP2.DSTP2_5 5 Destination Pointer Address of Channel 2 - bit 5
DSTP2.DSTP2_4 4 Destination Pointer Address of Channel 2 - bit 4
DSTP2.DSTP2_3 3 Destination Pointer Address of Channel 2 - bit 3
DSTP2.DSTP2_2 2 Destination Pointer Address of Channel 2 - bit 2
DSTP2.DSTP2_1 1 Destination Pointer Address of Channel 2 - bit 1
DSTP2.DSTP2_0 0 Destination Pointer Address of Channel 2 - bit 0
SRCP3 0xEC4C PEC Channel 3 Source Pointer
SRCP3.SRCP3_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP3.SRCP3_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP3.SRCP3_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP3.SRCP3_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP3.SRCP3_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP3.SRCP3_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP3.SRCP3_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP3.SRCP3_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP3.SRCP3_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP3.SRCP3_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP3.SRCP3_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP3.SRCP3_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP3.SRCP3_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP3.SRCP3_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP3.SRCP3_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP3.SRCP3_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP3 0xEC4E PEC Channel 3 Destination Pointer
DSTP3.DSTP3_15 15 Destination Pointer Address of Channel 3 - bit 15
DSTP3.DSTP3_14 14 Destination Pointer Address of Channel 3 - bit 14
DSTP3.DSTP3_13 13 Destination Pointer Address of Channel 3 - bit 13
DSTP3.DSTP3_12 12 Destination Pointer Address of Channel 3 - bit 12
DSTP3.DSTP3_11 11 Destination Pointer Address of Channel 3 - bit 11
DSTP3.DSTP3_10 10 Destination Pointer Address of Channel 3 - bit 10
DSTP3.DSTP3_9 9 Destination Pointer Address of Channel 3 - bit 9
DSTP3.DSTP3_8 8 Destination Pointer Address of Channel 3 - bit 8
DSTP3.DSTP3_7 7 Destination Pointer Address of Channel 3 - bit 7
DSTP3.DSTP3_6 6 Destination Pointer Address of Channel 3 - bit 6
DSTP3.DSTP3_5 5 Destination Pointer Address of Channel 3 - bit 5
DSTP3.DSTP3_4 4 Destination Pointer Address of Channel 3 - bit 4
DSTP3.DSTP3_3 3 Destination Pointer Address of Channel 3 - bit 3
DSTP3.DSTP3_2 2 Destination Pointer Address of Channel 3 - bit 2
DSTP3.DSTP3_1 1 Destination Pointer Address of Channel 3 - bit 1
DSTP3.DSTP3_0 0 Destination Pointer Address of Channel 3 - bit 0
SRCP4 0xEC50 PEC Channel 4 Source Pointer
SRCP4.SRCP4_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP4.SRCP4_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP4.SRCP4_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP4.SRCP4_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP4.SRCP4_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP4.SRCP4_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP4.SRCP4_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP4.SRCP4_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP4.SRCP4_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP4.SRCP4_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP4.SRCP4_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP4.SRCP4_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP4.SRCP4_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP4.SRCP4_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP4.SRCP4_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP4.SRCP4_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP4 0xEC52 PEC Channel 4 Destination Pointer
DSTP4.DSTP4_15 15 Destination Pointer Address of Channel 4 - bit 15
DSTP4.DSTP4_14 14 Destination Pointer Address of Channel 4 - bit 14
DSTP4.DSTP4_13 13 Destination Pointer Address of Channel 4 - bit 13
DSTP4.DSTP4_12 12 Destination Pointer Address of Channel 4 - bit 12
DSTP4.DSTP4_11 11 Destination Pointer Address of Channel 4 - bit 11
DSTP4.DSTP4_10 10 Destination Pointer Address of Channel 4 - bit 10
DSTP4.DSTP4_9 9 Destination Pointer Address of Channel 4 - bit 9
DSTP4.DSTP4_8 8 Destination Pointer Address of Channel 4 - bit 8
DSTP4.DSTP4_7 7 Destination Pointer Address of Channel 4 - bit 7
DSTP4.DSTP4_6 6 Destination Pointer Address of Channel 4 - bit 6
DSTP4.DSTP4_5 5 Destination Pointer Address of Channel 4 - bit 5
DSTP4.DSTP4_4 4 Destination Pointer Address of Channel 4 - bit 4
DSTP4.DSTP4_3 3 Destination Pointer Address of Channel 4 - bit 3
DSTP4.DSTP4_2 2 Destination Pointer Address of Channel 4 - bit 2
DSTP4.DSTP4_1 1 Destination Pointer Address of Channel 4 - bit 1
DSTP4.DSTP4_0 0 Destination Pointer Address of Channel 4 - bit 0
SRCP5 0xEC54 PEC Channel 5 Source Pointer
SRCP5.SRCP5_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP5.SRCP5_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP5.SRCP5_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP5.SRCP5_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP5.SRCP5_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP5.SRCP5_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP5.SRCP5_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP5.SRCP5_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP5.SRCP5_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP5.SRCP5_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP5.SRCP5_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP5.SRCP5_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP5.SRCP5_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP5.SRCP5_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP5.SRCP5_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP5.SRCP5_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP5 0xEC56 PEC Channel 5 Destination Pointer
DSTP5.DSTP5_15 15 Destination Pointer Address of Channel 5 - bit 15
DSTP5.DSTP5_14 14 Destination Pointer Address of Channel 5 - bit 14
DSTP5.DSTP5_13 13 Destination Pointer Address of Channel 5 - bit 13
DSTP5.DSTP5_12 12 Destination Pointer Address of Channel 5 - bit 12
DSTP5.DSTP5_11 11 Destination Pointer Address of Channel 5 - bit 11
DSTP5.DSTP5_10 10 Destination Pointer Address of Channel 5 - bit 10
DSTP5.DSTP5_9 9 Destination Pointer Address of Channel 5 - bit 9
DSTP5.DSTP5_8 8 Destination Pointer Address of Channel 5 - bit 8
DSTP5.DSTP5_7 7 Destination Pointer Address of Channel 5 - bit 7
DSTP5.DSTP5_6 6 Destination Pointer Address of Channel 5 - bit 6
DSTP5.DSTP5_5 5 Destination Pointer Address of Channel 5 - bit 5
DSTP5.DSTP5_4 4 Destination Pointer Address of Channel 5 - bit 4
DSTP5.DSTP5_3 3 Destination Pointer Address of Channel 5 - bit 3
DSTP5.DSTP5_2 2 Destination Pointer Address of Channel 5 - bit 2
DSTP5.DSTP5_1 1 Destination Pointer Address of Channel 5 - bit 1
DSTP5.DSTP5_0 0 Destination Pointer Address of Channel 5 - bit 0
SRCP6 0xEC58 PEC Channel 6 Source Pointer
SRCP6.SRCP6_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP6.SRCP6_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP6.SRCP6_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP6.SRCP6_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP6.SRCP6_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP6.SRCP6_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP6.SRCP6_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP6.SRCP6_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP6.SRCP6_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP6.SRCP6_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP6.SRCP6_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP6.SRCP6_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP6.SRCP6_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP6.SRCP6_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP6.SRCP6_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP6.SRCP6_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP6 0xEC5A PEC Channel 6 Destination Pointer
DSTP6.DSTP6_15 15 Destination Pointer Address of Channel 6 - bit 15
DSTP6.DSTP6_14 14 Destination Pointer Address of Channel 6 - bit 14
DSTP6.DSTP6_13 13 Destination Pointer Address of Channel 6 - bit 13
DSTP6.DSTP6_12 12 Destination Pointer Address of Channel 6 - bit 12
DSTP6.DSTP6_11 11 Destination Pointer Address of Channel 6 - bit 11
DSTP6.DSTP6_10 10 Destination Pointer Address of Channel 6 - bit 10
DSTP6.DSTP6_9 9 Destination Pointer Address of Channel 6 - bit 9
DSTP6.DSTP6_8 8 Destination Pointer Address of Channel 6 - bit 8
DSTP6.DSTP6_7 7 Destination Pointer Address of Channel 6 - bit 7
DSTP6.DSTP6_6 6 Destination Pointer Address of Channel 6 - bit 6
DSTP6.DSTP6_5 5 Destination Pointer Address of Channel 6 - bit 5
DSTP6.DSTP6_4 4 Destination Pointer Address of Channel 6 - bit 4
DSTP6.DSTP6_3 3 Destination Pointer Address of Channel 6 - bit 3
DSTP6.DSTP6_2 2 Destination Pointer Address of Channel 6 - bit 2
DSTP6.DSTP6_1 1 Destination Pointer Address of Channel 6 - bit 1
DSTP6.DSTP6_0 0 Destination Pointer Address of Channel 6 - bit 0
SRCP7 0xEC5C PEC Channel 7 Source Pointer
SRCP7.SRCP7_15 15 Source Pointer Address of Channel 0 - bit 15
SRCP7.SRCP7_14 14 Source Pointer Address of Channel 0 - bit 14
SRCP7.SRCP7_13 13 Source Pointer Address of Channel 0 - bit 13
SRCP7.SRCP7_12 12 Source Pointer Address of Channel 0 - bit 12
SRCP7.SRCP7_11 11 Source Pointer Address of Channel 0 - bit 11
SRCP7.SRCP7_10 10 Source Pointer Address of Channel 0 - bit 10
SRCP7.SRCP7_9 9 Source Pointer Address of Channel 0 - bit 9
SRCP7.SRCP7_8 8 Source Pointer Address of Channel 0 - bit 8
SRCP7.SRCP7_7 7 Source Pointer Address of Channel 0 - bit 7
SRCP7.SRCP7_6 6 Source Pointer Address of Channel 0 - bit 6
SRCP7.SRCP7_5 5 Source Pointer Address of Channel 0 - bit 5
SRCP7.SRCP7_4 4 Source Pointer Address of Channel 0 - bit 4
SRCP7.SRCP7_3 3 Source Pointer Address of Channel 0 - bit 3
SRCP7.SRCP7_2 2 Source Pointer Address of Channel 0 - bit 2
SRCP7.SRCP7_1 1 Source Pointer Address of Channel 0 - bit 1
SRCP7.SRCP7_0 0 Source Pointer Address of Channel 0 - bit 0
DSTP7 0xEC5E PEC Channel 7 Destination Pointer
DSTP7.DSTP7_15 15 Destination Pointer Address of Channel 7 - bit 15
DSTP7.DSTP7_14 14 Destination Pointer Address of Channel 7 - bit 14
DSTP7.DSTP7_13 13 Destination Pointer Address of Channel 7 - bit 13
DSTP7.DSTP7_12 12 Destination Pointer Address of Channel 7 - bit 12
DSTP7.DSTP7_11 11 Destination Pointer Address of Channel 7 - bit 11
DSTP7.DSTP7_10 10 Destination Pointer Address of Channel 7 - bit 10
DSTP7.DSTP7_9 9 Destination Pointer Address of Channel 7 - bit 9
DSTP7.DSTP7_8 8 Destination Pointer Address of Channel 7 - bit 8
DSTP7.DSTP7_7 7 Destination Pointer Address of Channel 7 - bit 7
DSTP7.DSTP7_6 6 Destination Pointer Address of Channel 7 - bit 6
DSTP7.DSTP7_5 5 Destination Pointer Address of Channel 7 - bit 5
DSTP7.DSTP7_4 4 Destination Pointer Address of Channel 7 - bit 4
DSTP7.DSTP7_3 3 Destination Pointer Address of Channel 7 - bit 3
DSTP7.DSTP7_2 2 Destination Pointer Address of Channel 7 - bit 2
DSTP7.DSTP7_1 1 Destination Pointer Address of Channel 7 - bit 1
DSTP7.DSTP7_0 0 Destination Pointer Address of Channel 7 - bit 0
PECSEG0 0xEC80 PEC Pointer 0 Segment Address Reg.
PECSEG0.SRCSEG0_15 15 Source Pointer Segment Address of Channel 0 - bit 15
PECSEG0.SRCSEG0_14 14 Source Pointer Segment Address of Channel 0 - bit 14
PECSEG0.SRCSEG0_13 13 Source Pointer Segment Address of Channel 0 - bit 13
PECSEG0.SRCSEG0_12 12 Source Pointer Segment Address of Channel 0 - bit 12
PECSEG0.SRCSEG0_11 11 Source Pointer Segment Address of Channel 0 - bit 11
PECSEG0.SRCSEG0_10 10 Source Pointer Segment Address of Channel 0 - bit 10
PECSEG0.SRCSEG0_9 9 Source Pointer Segment Address of Channel 0 - bit 9
PECSEG0.SRCSEG0_8 8 Source Pointer Segment Address of Channel 0 - bit 8
PECSEG0.DSTSEG0_7 7 Destination Pointer Segment Address of Channel 0 - bit 7
PECSEG0.DSTSEG0_6 6 Destination Pointer Segment Address of Channel 0 - bit 6
PECSEG0.DSTSEG0_5 5 Destination Pointer Segment Address of Channel 0 - bit 5
PECSEG0.DSTSEG0_4 4 Destination Pointer Segment Address of Channel 0 - bit 4
PECSEG0.DSTSEG0_3 3 Destination Pointer Segment Address of Channel 0 - bit 3
PECSEG0.DSTSEG0_2 2 Destination Pointer Segment Address of Channel 0 - bit 2
PECSEG0.DSTSEG0_1 1 Destination Pointer Segment Address of Channel 0 - bit 1
PECSEG0.DSTSEG0_0 0 Destination Pointer Segment Address of Channel 0 - bit 0
PECSEG1 0xEC82 PEC Pointer 1 Segment Address Reg.
PECSEG1.SRCSEG1_15 15 Source Pointer Segment Address of Channel 1 - bit 15
PECSEG1.SRCSEG1_14 14 Source Pointer Segment Address of Channel 1 - bit 14
PECSEG1.SRCSEG1_13 13 Source Pointer Segment Address of Channel 1 - bit 13
PECSEG1.SRCSEG1_12 12 Source Pointer Segment Address of Channel 1 - bit 12
PECSEG1.SRCSEG1_11 11 Source Pointer Segment Address of Channel 1 - bit 11
PECSEG1.SRCSEG1_10 10 Source Pointer Segment Address of Channel 1 - bit 10
PECSEG1.SRCSEG1_9 9 Source Pointer Segment Address of Channel 1 - bit 9
PECSEG1.SRCSEG1_8 8 Source Pointer Segment Address of Channel 1 - bit 8
PECSEG1.DSTSEG1_7 7 Destination Pointer Segment Address of Channel 1 - bit 7
PECSEG1.DSTSEG1_6 6 Destination Pointer Segment Address of Channel 1 - bit 6
PECSEG1.DSTSEG1_5 5 Destination Pointer Segment Address of Channel 1 - bit 5
PECSEG1.DSTSEG1_4 4 Destination Pointer Segment Address of Channel 1 - bit 4
PECSEG1.DSTSEG1_3 3 Destination Pointer Segment Address of Channel 1 - bit 3
PECSEG1.DSTSEG1_2 2 Destination Pointer Segment Address of Channel 1 - bit 2
PECSEG1.DSTSEG1_1 1 Destination Pointer Segment Address of Channel 1 - bit 1
PECSEG1.DSTSEG1_0 0 Destination Pointer Segment Address of Channel 1 - bit 0
PECSEG2 0xEC84 PEC Pointer 2 Segment Address Reg.
PECSEG2.SRCSEG2_15 15 Source Pointer Segment Address of Channel 2 - bit 15
PECSEG2.SRCSEG2_14 14 Source Pointer Segment Address of Channel 2 - bit 14
PECSEG2.SRCSEG2_13 13 Source Pointer Segment Address of Channel 2 - bit 13
PECSEG2.SRCSEG2_12 12 Source Pointer Segment Address of Channel 2 - bit 12
PECSEG2.SRCSEG2_11 11 Source Pointer Segment Address of Channel 2 - bit 11
PECSEG2.SRCSEG2_10 10 Source Pointer Segment Address of Channel 2 - bit 10
PECSEG2.SRCSEG2_9 9 Source Pointer Segment Address of Channel 2 - bit 9
PECSEG2.SRCSEG2_8 8 Source Pointer Segment Address of Channel 2 - bit 8
PECSEG2.DSTSEG2_7 7 Destination Pointer Segment Address of Channel 2 - bit 7
PECSEG2.DSTSEG2_6 6 Destination Pointer Segment Address of Channel 2 - bit 6
PECSEG2.DSTSEG2_5 5 Destination Pointer Segment Address of Channel 2 - bit 5
PECSEG2.DSTSEG2_4 4 Destination Pointer Segment Address of Channel 2 - bit 4
PECSEG2.DSTSEG2_3 3 Destination Pointer Segment Address of Channel 2 - bit 3
PECSEG2.DSTSEG2_2 2 Destination Pointer Segment Address of Channel 2 - bit 2
PECSEG2.DSTSEG2_1 1 Destination Pointer Segment Address of Channel 2 - bit 1
PECSEG2.DSTSEG2_0 0 Destination Pointer Segment Address of Channel 2 - bit 0
PECSEG3 0xEC86 PEC Pointer 3 Segment Address Reg.
PECSEG3.SRCSEG3_15 15 Source Pointer Segment Address of Channel 3 - bit 15
PECSEG3.SRCSEG3_14 14 Source Pointer Segment Address of Channel 3 - bit 14
PECSEG3.SRCSEG3_13 13 Source Pointer Segment Address of Channel 3 - bit 13
PECSEG3.SRCSEG3_12 12 Source Pointer Segment Address of Channel 3 - bit 12
PECSEG3.SRCSEG3_11 11 Source Pointer Segment Address of Channel 3 - bit 11
PECSEG3.SRCSEG3_10 10 Source Pointer Segment Address of Channel 3 - bit 10
PECSEG3.SRCSEG3_9 9 Source Pointer Segment Address of Channel 3 - bit 9
PECSEG3.SRCSEG3_8 8 Source Pointer Segment Address of Channel 3 - bit 8
PECSEG3.DSTSEG3_7 7 Destination Pointer Segment Address of Channel 3 - bit 7
PECSEG3.DSTSEG3_6 6 Destination Pointer Segment Address of Channel 3 - bit 6
PECSEG3.DSTSEG3_5 5 Destination Pointer Segment Address of Channel 3 - bit 5
PECSEG3.DSTSEG3_4 4 Destination Pointer Segment Address of Channel 3 - bit 4
PECSEG3.DSTSEG3_3 3 Destination Pointer Segment Address of Channel 3 - bit 3
PECSEG3.DSTSEG3_2 2 Destination Pointer Segment Address of Channel 3 - bit 2
PECSEG3.DSTSEG3_1 1 Destination Pointer Segment Address of Channel 3 - bit 1
PECSEG3.DSTSEG3_0 0 Destination Pointer Segment Address of Channel 3 - bit 0
PECSEG4 0xEC88 PEC Pointer 4 Segment Address Reg.
PECSEG4.SRCSEG4_15 15 Source Pointer Segment Address of Channel 4 - bit 15
PECSEG4.SRCSEG4_14 14 Source Pointer Segment Address of Channel 4 - bit 14
PECSEG4.SRCSEG4_13 13 Source Pointer Segment Address of Channel 4 - bit 13
PECSEG4.SRCSEG4_12 12 Source Pointer Segment Address of Channel 4 - bit 12
PECSEG4.SRCSEG4_11 11 Source Pointer Segment Address of Channel 4 - bit 11
PECSEG4.SRCSEG4_10 10 Source Pointer Segment Address of Channel 4 - bit 10
PECSEG4.SRCSEG4_9 9 Source Pointer Segment Address of Channel 4 - bit 9
PECSEG4.SRCSEG4_8 8 Source Pointer Segment Address of Channel 4 - bit 8
PECSEG4.DSTSEG4_7 7 Destination Pointer Segment Address of Channel 4 - bit 7
PECSEG4.DSTSEG4_6 6 Destination Pointer Segment Address of Channel 4 - bit 6
PECSEG4.DSTSEG4_5 5 Destination Pointer Segment Address of Channel 4 - bit 5
PECSEG4.DSTSEG4_4 4 Destination Pointer Segment Address of Channel 4 - bit 4
PECSEG4.DSTSEG4_3 3 Destination Pointer Segment Address of Channel 4 - bit 3
PECSEG4.DSTSEG4_2 2 Destination Pointer Segment Address of Channel 4 - bit 2
PECSEG4.DSTSEG4_1 1 Destination Pointer Segment Address of Channel 4 - bit 1
PECSEG4.DSTSEG4_0 0 Destination Pointer Segment Address of Channel 4 - bit 0
PECSEG5 0xEC8A PEC Pointer 5 Segment Address Reg.
PECSEG5.SRCSEG5_15 15 Source Pointer Segment Address of Channel 5 - bit 15
PECSEG5.SRCSEG5_14 14 Source Pointer Segment Address of Channel 5 - bit 14
PECSEG5.SRCSEG5_13 13 Source Pointer Segment Address of Channel 5 - bit 13
PECSEG5.SRCSEG5_12 12 Source Pointer Segment Address of Channel 5 - bit 12
PECSEG5.SRCSEG5_11 11 Source Pointer Segment Address of Channel 5 - bit 11
PECSEG5.SRCSEG5_10 10 Source Pointer Segment Address of Channel 5 - bit 10
PECSEG5.SRCSEG5_9 9 Source Pointer Segment Address of Channel 5 - bit 9
PECSEG5.SRCSEG5_8 8 Source Pointer Segment Address of Channel 5 - bit 8
PECSEG5.DSTSEG5_7 7 Destination Pointer Segment Address of Channel 5 - bit 7
PECSEG5.DSTSEG5_6 6 Destination Pointer Segment Address of Channel 5 - bit 6
PECSEG5.DSTSEG5_5 5 Destination Pointer Segment Address of Channel 5 - bit 5
PECSEG5.DSTSEG5_4 4 Destination Pointer Segment Address of Channel 5 - bit 4
PECSEG5.DSTSEG5_3 3 Destination Pointer Segment Address of Channel 5 - bit 3
PECSEG5.DSTSEG5_2 2 Destination Pointer Segment Address of Channel 5 - bit 2
PECSEG5.DSTSEG5_1 1 Destination Pointer Segment Address of Channel 5 - bit 1
PECSEG5.DSTSEG5_0 0 Destination Pointer Segment Address of Channel 5 - bit 0
PECSEG6 0xEC8C PEC Pointer 6 Segment Address Reg.
PECSEG6.SRCSEG6_15 15 Source Pointer Segment Address of Channel 6 - bit 15
PECSEG6.SRCSEG6_14 14 Source Pointer Segment Address of Channel 6 - bit 14
PECSEG6.SRCSEG6_13 13 Source Pointer Segment Address of Channel 6 - bit 13
PECSEG6.SRCSEG6_12 12 Source Pointer Segment Address of Channel 6 - bit 12
PECSEG6.SRCSEG6_11 11 Source Pointer Segment Address of Channel 6 - bit 11
PECSEG6.SRCSEG6_10 10 Source Pointer Segment Address of Channel 6 - bit 10
PECSEG6.SRCSEG6_9 9 Source Pointer Segment Address of Channel 6 - bit 9
PECSEG6.SRCSEG6_8 8 Source Pointer Segment Address of Channel 6 - bit 8
PECSEG6.DSTSEG6_7 7 Destination Pointer Segment Address of Channel 6 - bit 7
PECSEG6.DSTSEG6_6 6 Destination Pointer Segment Address of Channel 6 - bit 6
PECSEG6.DSTSEG6_5 5 Destination Pointer Segment Address of Channel 6 - bit 5
PECSEG6.DSTSEG6_4 4 Destination Pointer Segment Address of Channel 6 - bit 4
PECSEG6.DSTSEG6_3 3 Destination Pointer Segment Address of Channel 6 - bit 3
PECSEG6.DSTSEG6_2 2 Destination Pointer Segment Address of Channel 6 - bit 2
PECSEG6.DSTSEG6_1 1 Destination Pointer Segment Address of Channel 6 - bit 1
PECSEG6.DSTSEG6_0 0 Destination Pointer Segment Address of Channel 6 - bit 0
PECSEG7 0xEC8E PEC Pointer 7 Segment Address Reg.
PECSEG7.SRCSEG7_15 15 Source Pointer Segment Address of Channel 7 - bit 15
PECSEG7.SRCSEG7_14 14 Source Pointer Segment Address of Channel 7 - bit 14
PECSEG7.SRCSEG7_13 13 Source Pointer Segment Address of Channel 7 - bit 13
PECSEG7.SRCSEG7_12 12 Source Pointer Segment Address of Channel 7 - bit 12
PECSEG7.SRCSEG7_11 11 Source Pointer Segment Address of Channel 7 - bit 11
PECSEG7.SRCSEG7_10 10 Source Pointer Segment Address of Channel 7 - bit 10
PECSEG7.SRCSEG7_9 9 Source Pointer Segment Address of Channel 7 - bit 9
PECSEG7.SRCSEG7_8 8 Source Pointer Segment Address of Channel 7 - bit 8
PECSEG7.DSTSEG7_7 7 Destination Pointer Segment Address of Channel 7 - bit 7
PECSEG7.DSTSEG7_6 6 Destination Pointer Segment Address of Channel 7 - bit 6
PECSEG7.DSTSEG7_5 5 Destination Pointer Segment Address of Channel 7 - bit 5
PECSEG7.DSTSEG7_4 4 Destination Pointer Segment Address of Channel 7 - bit 4
PECSEG7.DSTSEG7_3 3 Destination Pointer Segment Address of Channel 7 - bit 3
PECSEG7.DSTSEG7_2 2 Destination Pointer Segment Address of Channel 7 - bit 2
PECSEG7.DSTSEG7_1 1 Destination Pointer Segment Address of Channel 7 - bit 1
PECSEG7.DSTSEG7_0 0 Destination Pointer Segment Address of Channel 7 - bit 0
EBCMOD0 0xEE00 Alternate Function of EBC Pins
EBCMOD0.RDYPOL 15 READY pin Polarity
EBCMOD0.RDYDIS 14 READY pin Disable
EBCMOD0.ALEDIS 13 ALE pin Disable
EBCMOD0.BYTDIS 12 BHE pin Disable
EBCMOD0.WRCFG 11 Configuration for pins WR/WRL, BHE/WRH
EBCMOD0.EBCDIS 10 EBC pins Disable
EBCMOD0.SLAVE 9 SLAVE mode enable
EBCMOD0.ARBEN 8 BUS Arbitration Pins enable
EBCMOD0.CSPEN_7 7 CS Pins Enable - bit 7
EBCMOD0.CSPEN_6 6 CS Pins Enable - bit 6
EBCMOD0.CSPEN_5 5 CS Pins Enable - bit 5
EBCMOD0.CSPEN_4 4 CS Pins Enable - bit 4
EBCMOD0.SAPEN_3 3 Segment Addresses Pins Enable - bit 3
EBCMOD0.SAPEN_2 2 Segment Addresses Pins Enable - bit 2
EBCMOD0.SAPEN_1 1 Segment Addresses Pins Enable - bit 1
EBCMOD0.SAPEN_0 0 Segment Addresses Pins Enable - bit 0
EBCMOD1 0xEE02 Global Behavior of EBC
EBCMOD1.DHPDIS 6 Data High Pins Disable
EBCMOD1.APDIS_4 4 Address Pins Disable - bit 4
EBCMOD1.APDIS_3 3 Address Pins Disable - bit 3
EBCMOD1.APDIS_2 2 Address Pins Disable - bit 2
EBCMOD1.APDIS_1 1 Address Pins Disable - bit 1
EBCMOD1.APDIS_0 0 Address Pins Disable - bit 0
TCONCSMM 0xEE0C Timing Control for Monitor Memory
TCONCSMM.WRPHF_14 14 Write Phase F - bit 14
TCONCSMM.WRPHF_13 13 Write Phase F - bit 13
TCONCSMM.RDPHF_12 12 Read Phase F - bit 12
TCONCSMM.RDPHF_11 11 Read Phase F - bit 11
TCONCSMM.PHE_10 10 Phase E - bit 10
TCONCSMM.PHE_9 9 Phase E - bit 9
TCONCSMM.PHE_8 8 Phase E - bit 8
TCONCSMM.PHE_7 7 Phase E - bit 7
TCONCSMM.PHE_6 6 Phase E - bit 6
TCONCSMM.PHD 5 Phase D
TCONCSMM.PHC_4 4 Phase C - bit 4
TCONCSMM.PHC_3 3 Phase C - bit 3
TCONCSMM.PHB 2 Phase B
TCONCSMM.PHA_1 1 Phase A - bit 1
TCONCSMM.PHA_0 0 Phase A - bit 0
TCONCSSM 0xEE0E Timing Control for Startup Memory
TCONCSSM.WRPHF_14 14 Write Phase F - bit 14
TCONCSSM.WRPHF_13 13 Write Phase F - bit 13
TCONCSSM.RDPHF_12 12 Read Phase F - bit 12
TCONCSSM.RDPHF_11 11 Read Phase F - bit 11
TCONCSSM.PHE_10 10 Phase E - bit 10
TCONCSSM.PHE_9 9 Phase E - bit 9
TCONCSSM.PHE_8 8 Phase E - bit 8
TCONCSSM.PHE_7 7 Phase E - bit 7
TCONCSSM.PHE_6 6 Phase E - bit 6
TCONCSSM.PHD 5 Phase D
TCONCSSM.PHC_4 4 Phase C - bit 4
TCONCSSM.PHC_3 3 Phase C - bit 3
TCONCSSM.PHB 2 Phase B
TCONCSSM.PHA_1 1 Phase A - bit 1
TCONCSSM.PHA_0 0 Phase A - bit 0
TCONCS0 0xEE10 Timing Control for CS0
TCONCS0.WRPHF_14 14 Write Phase F - bit 14
TCONCS0.WRPHF_13 13 Write Phase F - bit 13
TCONCS0.RDPHF_12 12 Read Phase F - bit 12
TCONCS0.RDPHF_11 11 Read Phase F - bit 11
TCONCS0.PHE_10 10 Phase E - bit 10
TCONCS0.PHE_9 9 Phase E - bit 9
TCONCS0.PHE_8 8 Phase E - bit 8
TCONCS0.PHE_7 7 Phase E - bit 7
TCONCS0.PHE_6 6 Phase E - bit 6
TCONCS0.PHD 5 Phase D
TCONCS0.PHC_4 4 Phase C - bit 4
TCONCS0.PHC_3 3 Phase C - bit 3
TCONCS0.PHB 2 Phase B
TCONCS0.PHA_1 1 Phase A - bit 1
TCONCS0.PHA_0 0 Phase A - bit 0
FCONCS0 0xEE12 Function Control for CS0
FCONCS0.BTYP_5 5 Bus Type Selection - bit 5
FCONCS0.BTYP_4 4 Bus Type Selection - bit 4
FCONCS0.RDYMOD 2 Ready Mode
FCONCS0.RDYEN 1 Ready enable
FCONCS0.ENCS 0 Enable Chip Select
TCONCS1 0xEE18 Timing Control for CS1
TCONCS1.WRPHF_14 14 Write Phase F - bit 14
TCONCS1.WRPHF_13 13 Write Phase F - bit 13
TCONCS1.RDPHF_12 12 Read Phase F - bit 12
TCONCS1.RDPHF_11 11 Read Phase F - bit 11
TCONCS1.PHE_10 10 Phase E - bit 10
TCONCS1.PHE_9 9 Phase E - bit 9
TCONCS1.PHE_8 8 Phase E - bit 8
TCONCS1.PHE_7 7 Phase E - bit 7
TCONCS1.PHE_6 6 Phase E - bit 6
TCONCS1.PHD 5 Phase D
TCONCS1.PHC_4 4 Phase C - bit 4
TCONCS1.PHC_3 3 Phase C - bit 3
TCONCS1.PHB 2 Phase B
TCONCS1.PHA_1 1 Phase A - bit 1
TCONCS1.PHA_0 0 Phase A - bit 0
FCONCS1 0xEE1A Function Control for CS1
FCONCS1.BTYP_5 5 Bus Type Selection - bit 5
FCONCS1.BTYP_4 4 Bus Type Selection - bit 4
FCONCS1.RDYMOD 2 Ready Mode
FCONCS1.RDYEN 1 Ready enable
FCONCS1.ENCS 0 Enable Chip Select
ADDRSEL1 0xEE1E Address Window Selection for CS1
ADDRSEL1.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL1.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL1.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL1.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL1.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL1.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL1.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL1.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL1.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL1.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL1.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL1.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL1.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL1.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL1.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL1.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS2 0xEE20 Timing Control for CS2
TCONCS2.WRPHF_14 14 Write Phase F - bit 14
TCONCS2.WRPHF_13 13 Write Phase F - bit 13
TCONCS2.RDPHF_12 12 Read Phase F - bit 12
TCONCS2.RDPHF_11 11 Read Phase F - bit 11
TCONCS2.PHE_10 10 Phase E - bit 10
TCONCS2.PHE_9 9 Phase E - bit 9
TCONCS2.PHE_8 8 Phase E - bit 8
TCONCS2.PHE_7 7 Phase E - bit 7
TCONCS2.PHE_6 6 Phase E - bit 6
TCONCS2.PHD 5 Phase D
TCONCS2.PHC_4 4 Phase C - bit 4
TCONCS2.PHC_3 3 Phase C - bit 3
TCONCS2.PHB 2 Phase B
TCONCS2.PHA_1 1 Phase A - bit 1
TCONCS2.PHA_0 0 Phase A - bit 0
FCONCS2 0xEE22 Function Control for CS2
FCONCS2.BTYP_5 5 Bus Type Selection - bit 5
FCONCS2.BTYP_4 4 Bus Type Selection - bit 4
FCONCS2.RDYMOD 2 Ready Mode
FCONCS2.RDYEN 1 Ready enable
FCONCS2.ENCS 0 Enable Chip Select
ADDRSEL2 0xEE26 Address Window Selection for CS2
ADDRSEL2.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL2.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL2.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL2.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL2.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL2.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL2.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL2.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL2.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL2.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL2.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL2.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL2.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL2.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL2.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL2.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS3 0xEE28 Timing Control for CS3
TCONCS3.WRPHF_14 14 Write Phase F - bit 14
TCONCS3.WRPHF_13 13 Write Phase F - bit 13
TCONCS3.RDPHF_12 12 Read Phase F - bit 12
TCONCS3.RDPHF_11 11 Read Phase F - bit 11
TCONCS3.PHE_10 10 Phase E - bit 10
TCONCS3.PHE_9 9 Phase E - bit 9
TCONCS3.PHE_8 8 Phase E - bit 8
TCONCS3.PHE_7 7 Phase E - bit 7
TCONCS3.PHE_6 6 Phase E - bit 6
TCONCS3.PHD 5 Phase D
TCONCS3.PHC_4 4 Phase C - bit 4
TCONCS3.PHC_3 3 Phase C - bit 3
TCONCS3.PHB 2 Phase B
TCONCS3.PHA_1 1 Phase A - bit 1
TCONCS3.PHA_0 0 Phase A - bit 0
FCONCS3 0xEE2A Function Control for CS3
FCONCS3.BTYP_5 5 Bus Type Selection - bit 5
FCONCS3.BTYP_4 4 Bus Type Selection - bit 4
FCONCS3.RDYMOD 2 Ready Mode
FCONCS3.RDYEN 1 Ready enable
FCONCS3.ENCS 0 Enable Chip Select
ADDRSEL3 0xEE2E Address Window Selection for CS3
ADDRSEL3.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL3.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL3.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL3.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL3.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL3.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL3.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL3.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL3.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL3.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL3.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL3.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL3.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL3.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL3.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL3.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS4 0xEE30 Timing Control for CS4
TCONCS4.WRPHF_14 14 Write Phase F - bit 14
TCONCS4.WRPHF_13 13 Write Phase F - bit 13
TCONCS4.RDPHF_12 12 Read Phase F - bit 12
TCONCS4.RDPHF_11 11 Read Phase F - bit 11
TCONCS4.PHE_10 10 Phase E - bit 10
TCONCS4.PHE_9 9 Phase E - bit 9
TCONCS4.PHE_8 8 Phase E - bit 8
TCONCS4.PHE_7 7 Phase E - bit 7
TCONCS4.PHE_6 6 Phase E - bit 6
TCONCS4.PHD 5 Phase D
TCONCS4.PHC_4 4 Phase C - bit 4
TCONCS4.PHC_3 3 Phase C - bit 3
TCONCS4.PHB 2 Phase B
TCONCS4.PHA_1 1 Phase A - bit 1
TCONCS4.PHA_0 0 Phase A - bit 0
FCONCS4 0xEE32 Function Control for CS4
FCONCS4.BTYP_5 5 Bus Type Selection - bit 5
FCONCS4.BTYP_4 4 Bus Type Selection - bit 4
FCONCS4.RDYMOD 2 Ready Mode
FCONCS4.RDYEN 1 Ready enable
FCONCS4.ENCS 0 Enable Chip Select
ADDRSEL4 0xEE36 address window selection for CS4
ADDRSEL4.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL4.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL4.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL4.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL4.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL4.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL4.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL4.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL4.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL4.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL4.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL4.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL4.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL4.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL4.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL4.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS5 0xEE38 Timing Control for CS5
TCONCS5.WRPHF_14 14 Write Phase F - bit 14
TCONCS5.WRPHF_13 13 Write Phase F - bit 13
TCONCS5.RDPHF_12 12 Read Phase F - bit 12
TCONCS5.RDPHF_11 11 Read Phase F - bit 11
TCONCS5.PHE_10 10 Phase E - bit 10
TCONCS5.PHE_9 9 Phase E - bit 9
TCONCS5.PHE_8 8 Phase E - bit 8
TCONCS5.PHE_7 7 Phase E - bit 7
TCONCS5.PHE_6 6 Phase E - bit 6
TCONCS5.PHD 5 Phase D
TCONCS5.PHC_4 4 Phase C - bit 4
TCONCS5.PHC_3 3 Phase C - bit 3
TCONCS5.PHB 2 Phase B
TCONCS5.PHA_1 1 Phase A - bit 1
TCONCS5.PHA_0 0 Phase A - bit 0
FCONCS5 0xEE3A Function Control for CS5
FCONCS5.BTYP_5 5 Bus Type Selection - bit 5
FCONCS5.BTYP_4 4 Bus Type Selection - bit 4
FCONCS5.RDYMOD 2 Ready Mode
FCONCS5.RDYEN 1 Ready enable
FCONCS5.ENCS 0 Enable Chip Select
ADDRSEL5 0xEE3E Address Window Selection for CS5
ADDRSEL5.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL5.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL5.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL5.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL5.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL5.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL5.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL5.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL5.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL5.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL5.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL5.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL5.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL5.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL5.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL5.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS6 0xEE40 Timing Control for CS6
TCONCS6.WRPHF_14 14 Write Phase F - bit 14
TCONCS6.WRPHF_13 13 Write Phase F - bit 13
TCONCS6.RDPHF_12 12 Read Phase F - bit 12
TCONCS6.RDPHF_11 11 Read Phase F - bit 11
TCONCS6.PHE_10 10 Phase E - bit 10
TCONCS6.PHE_9 9 Phase E - bit 9
TCONCS6.PHE_8 8 Phase E - bit 8
TCONCS6.PHE_7 7 Phase E - bit 7
TCONCS6.PHE_6 6 Phase E - bit 6
TCONCS6.PHD 5 Phase D
TCONCS6.PHC_4 4 Phase C - bit 4
TCONCS6.PHC_3 3 Phase C - bit 3
TCONCS6.PHB 2 Phase B
TCONCS6.PHA_1 1 Phase A - bit 1
TCONCS6.PHA_0 0 Phase A - bit 0
FCONCS6 0xEE42 Function Control for CS6
FCONCS6.BTYP_5 5 Bus Type Selection - bit 5
FCONCS6.BTYP_4 4 Bus Type Selection - bit 4
FCONCS6.RDYMOD 2 Ready Mode
FCONCS6.RDYEN 1 Ready enable
FCONCS6.ENCS 0 Enable Chip Select
ADDRSEL6 0xEE46 Address Window Selection for CS6
ADDRSEL6.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL6.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL6.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL6.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL6.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL6.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL6.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL6.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL6.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL6.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL6.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL6.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL6.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL6.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL6.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL6.RGSZ_0 0 Address Range Size Selection - bit 0
TCONCS7 0xEE48 Timing Control for CS7
TCONCS7.WRPHF_14 14 Write Phase F - bit 14
TCONCS7.WRPHF_13 13 Write Phase F - bit 13
TCONCS7.RDPHF_12 12 Read Phase F - bit 12
TCONCS7.RDPHF_11 11 Read Phase F - bit 11
TCONCS7.PHE_10 10 Phase E - bit 10
TCONCS7.PHE_9 9 Phase E - bit 9
TCONCS7.PHE_8 8 Phase E - bit 8
TCONCS7.PHE_7 7 Phase E - bit 7
TCONCS7.PHE_6 6 Phase E - bit 6
TCONCS7.PHD 5 Phase D
TCONCS7.PHC_4 4 Phase C - bit 4
TCONCS7.PHC_3 3 Phase C - bit 3
TCONCS7.PHB 2 Phase B
TCONCS7.PHA_1 1 Phase A - bit 1
TCONCS7.PHA_0 0 Phase A - bit 0
FCONCS7 0xEE4A Function Control for CS7
FCONCS7.BTYP_5 5 Bus Type Selection - bit 5
FCONCS7.BTYP_4 4 Bus Type Selection - bit 4
FCONCS7.RDYMOD 2 Ready Mode
FCONCS7.RDYEN 1 Ready enable
FCONCS7.ENCS 0 Enable Chip Select
ADDRSEL7 0xEE4E Address Window Selection for CS7
ADDRSEL7.RGSAD_15 15 Address Range Start Address Selection - bit 15
ADDRSEL7.RGSAD_14 14 Address Range Start Address Selection - bit 14
ADDRSEL7.RGSAD_13 13 Address Range Start Address Selection - bit 13
ADDRSEL7.RGSAD_12 12 Address Range Start Address Selection - bit 12
ADDRSEL7.RGSAD_11 11 Address Range Start Address Selection - bit 11
ADDRSEL7.RGSAD_10 10 Address Range Start Address Selection - bit 10
ADDRSEL7.RGSAD_9 9 Address Range Start Address Selection - bit 9
ADDRSEL7.RGSAD_8 8 Address Range Start Address Selection - bit 8
ADDRSEL7.RGSAD_7 7 Address Range Start Address Selection - bit 7
ADDRSEL7.RGSAD_6 6 Address Range Start Address Selection - bit 6
ADDRSEL7.RGSAD_5 5 Address Range Start Address Selection - bit 5
ADDRSEL7.RGSAD_4 4 Address Range Start Address Selection - bit 4
ADDRSEL7.RGSZ_3 3 Address Range Size Selection - bit 3
ADDRSEL7.RGSZ_2 2 Address Range Size Selection - bit 2
ADDRSEL7.RGSZ_1 1 Address Range Size Selection - bit 1
ADDRSEL7.RGSZ_0 0 Address Range Size Selection - bit 0
QX0 0xF000 MAC Offset Register X0
QX0.QX_15 15 Modifiable portion of register QX0 - bit 15
QX0.QX_14 14 Modifiable portion of register QX0 - bit 14
QX0.QX_13 13 Modifiable portion of register QX0 - bit 13
QX0.QX_12 12 Modifiable portion of register QX0 - bit 12
QX0.QX_11 11 Modifiable portion of register QX0 - bit 11
QX0.QX_10 10 Modifiable portion of register QX0 - bit 10
QX0.QX_9 9 Modifiable portion of register QX0 - bit 9
QX0.QX_8 8 Modifiable portion of register QX0 - bit 8
QX0.QX_7 7 Modifiable portion of register QX0 - bit 7
QX0.QX_6 6 Modifiable portion of register QX0 - bit 6
QX0.QX_5 5 Modifiable portion of register QX0 - bit 5
QX0.QX_4 4 Modifiable portion of register QX0 - bit 4
QX0.QX_3 3 Modifiable portion of register QX0 - bit 3
QX0.QX_2 2 Modifiable portion of register QX0 - bit 2
QX0.QX_1 1 Modifiable portion of register QX0 - bit 1
QX1 0xF002 MAC Offset Register X1
QX1.QX_15 15 Modifiable portion of register QX1 - bit 15
QX1.QX_14 14 Modifiable portion of register QX1 - bit 14
QX1.QX_13 13 Modifiable portion of register QX1 - bit 13
QX1.QX_12 12 Modifiable portion of register QX1 - bit 12
QX1.QX_11 11 Modifiable portion of register QX1 - bit 11
QX1.QX_10 10 Modifiable portion of register QX1 - bit 10
QX1.QX_9 9 Modifiable portion of register QX1 - bit 9
QX1.QX_8 8 Modifiable portion of register QX1 - bit 8
QX1.QX_7 7 Modifiable portion of register QX1 - bit 7
QX1.QX_6 6 Modifiable portion of register QX1 - bit 6
QX1.QX_5 5 Modifiable portion of register QX1 - bit 5
QX1.QX_4 4 Modifiable portion of register QX1 - bit 4
QX1.QX_3 3 Modifiable portion of register QX1 - bit 3
QX1.QX_2 2 Modifiable portion of register QX1 - bit 2
QX1.QX_1 1 Modifiable portion of register QX1 - bit 1
QR0 0xF004 MAC Offset Register R0
QR0.QR_15 15 Modifiable portion of register QR0 - bit 15
QR0.QR_14 14 Modifiable portion of register QR0 - bit 14
QR0.QR_13 13 Modifiable portion of register QR0 - bit 13
QR0.QR_12 12 Modifiable portion of register QR0 - bit 12
QR0.QR_11 11 Modifiable portion of register QR0 - bit 11
QR0.QR_10 10 Modifiable portion of register QR0 - bit 10
QR0.QR_9 9 Modifiable portion of register QR0 - bit 9
QR0.QR_8 8 Modifiable portion of register QR0 - bit 8
QR0.QR_7 7 Modifiable portion of register QR0 - bit 7
QR0.QR_6 6 Modifiable portion of register QR0 - bit 6
QR0.QR_5 5 Modifiable portion of register QR0 - bit 5
QR0.QR_4 4 Modifiable portion of register QR0 - bit 4
QR0.QR_3 3 Modifiable portion of register QR0 - bit 3
QR0.QR_2 2 Modifiable portion of register QR0 - bit 2
QR0.QR_1 1 Modifiable portion of register QR0 - bit 1
QR1 0xF006 MAC Offset Register R1
QR1.QR_15 15 Modifiable portion of register QR1 - bit 15
QR1.QR_14 14 Modifiable portion of register QR1 - bit 14
QR1.QR_13 13 Modifiable portion of register QR1 - bit 13
QR1.QR_12 12 Modifiable portion of register QR1 - bit 12
QR1.QR_11 11 Modifiable portion of register QR1 - bit 11
QR1.QR_10 10 Modifiable portion of register QR1 - bit 10
QR1.QR_9 9 Modifiable portion of register QR1 - bit 9
QR1.QR_8 8 Modifiable portion of register QR1 - bit 8
QR1.QR_7 7 Modifiable portion of register QR1 - bit 7
QR1.QR_6 6 Modifiable portion of register QR1 - bit 6
QR1.QR_5 5 Modifiable portion of register QR1 - bit 5
QR1.QR_4 4 Modifiable portion of register QR1 - bit 4
QR1.QR_3 3 Modifiable portion of register QR1 - bit 3
QR1.QR_2 2 Modifiable portion of register QR1 - bit 2
QR1.QR_1 1 Modifiable portion of register QR1 - bit 1
CPUID 0xF00C CPU Identification Register
CPUID.MODULE_NUMBER_15 15 Module Number - bit 15
CPUID.MODULE_NUMBER_14 14 Module Number - bit 14
CPUID.MODULE_NUMBER_13 13 Module Number - bit 13
CPUID.MODULE_NUMBER_12 12 Module Number - bit 12
CPUID.MODULE_NUMBER_11 11 Module Number - bit 11
CPUID.MODULE_NUMBER_10 10 Module Number - bit 10
CPUID.MODULE_NUMBER_9 9 Module Number - bit 9
CPUID.MODULE_NUMBER_8 8 Module Number - bit 8
CPUID.VERSION_NUMBER_7 7 Version Number - bit 7
CPUID.VERSION_NUMBER_6 6 Version Number - bit 6
CPUID.VERSION_NUMBER_5 5 Version Number - bit 5
CPUID.VERSION_NUMBER_4 4 Version Number - bit 4
CPUID.VERSION_NUMBER_3 3 Version Number - bit 3
CPUID.VERSION_NUMBER_2 2 Version Number - bit 2
CPUID.VERSION_NUMBER_1 1 Version Number - bit 1
CPUID.VERSION_NUMBER_0 0 Version Number - bit 0
EOPIC 0xF180 End of PEC Transfer Interrupt Control Register
EOPIC.GPX 8 Group Priority Extension
EOPIC.EOPIR 7 Interrupt Request Flag
EOPIC.EOPIE 6 Interrupt Enable Control Bit
EOPIC.ILVL_5 5 Interrupt Priority Level - bit 5
EOPIC.ILVL_4 4 Interrupt Priority Level - bit 4
EOPIC.ILVL_3 3 Interrupt Priority Level - bit 3
EOPIC.ILVL_2 2 Interrupt Priority Level - bit 2
EOPIC.GLVL_1 1 Group Priority Level - 1
EOPIC.GLVL_0 0 Group Priority Level - 0
DPP0 0xFE00 CPU Data Page Pointer 0 Register (10 bits)
DPP0.DPP0PN_9 9 Data Page Number of DPP - bit 9
DPP0.DPP0PN_8 8 Data Page Number of DPP - bit 8
DPP0.DPP0PN_7 7 Data Page Number of DPP - bit 7
DPP0.DPP0PN_6 6 Data Page Number of DPP - bit 6
DPP0.DPP0PN_5 5 Data Page Number of DPP - bit 5
DPP0.DPP0PN_4 4 Data Page Number of DPP - bit 4
DPP0.DPP0PN_3 3 Data Page Number of DPP - bit 3
DPP0.DPP0PN_2 2 Data Page Number of DPP - bit 2
DPP0.DPP0PN_1 1 Data Page Number of DPP - bit 1
DPP0.DPP0PN_0 0 Data Page Number of DPP - bit 0
DPP1 0xFE02 CPU Data Page Pointer 1 Register (10 bits)
DPP1.DPP1PN_9 9 Data Page Number of DPP - bit 9
DPP1.DPP1PN_8 8 Data Page Number of DPP - bit 8
DPP1.DPP1PN_7 7 Data Page Number of DPP - bit 7
DPP1.DPP1PN_6 6 Data Page Number of DPP - bit 6
DPP1.DPP1PN_5 5 Data Page Number of DPP - bit 5
DPP1.DPP1PN_4 4 Data Page Number of DPP - bit 4
DPP1.DPP1PN_3 3 Data Page Number of DPP - bit 3
DPP1.DPP1PN_2 2 Data Page Number of DPP - bit 2
DPP1.DPP1PN_1 1 Data Page Number of DPP - bit 1
DPP1.DPP1PN_0 0 Data Page Number of DPP - bit 0
DPP2 0xFE04 CPU Data Page Pointer 2 Register (10 bits)
DPP2.DPP2PN_9 9 Data Page Number of DPP - bit 9
DPP2.DPP2PN_8 8 Data Page Number of DPP - bit 8
DPP2.DPP2PN_7 7 Data Page Number of DPP - bit 7
DPP2.DPP2PN_6 6 Data Page Number of DPP - bit 6
DPP2.DPP2PN_5 5 Data Page Number of DPP - bit 5
DPP2.DPP2PN_4 4 Data Page Number of DPP - bit 4
DPP2.DPP2PN_3 3 Data Page Number of DPP - bit 3
DPP2.DPP2PN_2 2 Data Page Number of DPP - bit 2
DPP2.DPP2PN_1 1 Data Page Number of DPP - bit 1
DPP2.DPP2PN_0 0 Data Page Number of DPP - bit 0
DPP3 0xFE06 CPU Data Page Pointer 3 Register (10 bits)
DPP3.DPP3PN_9 9 Data Page Number of DPP - bit 9
DPP3.DPP3PN_8 8 Data Page Number of DPP - bit 8
DPP3.DPP3PN_7 7 Data Page Number of DPP - bit 7
DPP3.DPP3PN_6 6 Data Page Number of DPP - bit 6
DPP3.DPP3PN_5 5 Data Page Number of DPP - bit 5
DPP3.DPP3PN_4 4 Data Page Number of DPP - bit 4
DPP3.DPP3PN_3 3 Data Page Number of DPP - bit 3
DPP3.DPP3PN_2 2 Data Page Number of DPP - bit 2
DPP3.DPP3PN_1 1 Data Page Number of DPP - bit 1
DPP3.DPP3PN_0 0 Data Page Number of DPP - bit 0
CSP 0xFE08 CPU Code Segment Pointer Register (8 bits)
CSP.SEGNR_7 7 Specifies the code segment from which the current instruction is to be fetched - bit 7
CSP.SEGNR_6 6 Specifies the code segment from which the current instruction is to be fetched - bit 6
CSP.SEGNR_5 5 Specifies the code segment from which the current instruction is to be fetched - bit 5
CSP.SEGNR_4 4 Specifies the code segment from which the current instruction is to be fetched - bit 4
CSP.SEGNR_3 3 Specifies the code segment from which the current instruction is to be fetched - bit 3
CSP.SEGNR_2 2 Specifies the code segment from which the current instruction is to be fetched - bit 2
CSP.SEGNR_1 1 Specifies the code segment from which the current instruction is to be fetched - bit 1
CSP.SEGNR_0 0 Specifies the code segment from which the current instruction is to be fetched - bit 0
MDH 0xFE0C CPU Multiply Divide Register - High Word
MDH.MDH_15 15 High part of MD - bit 15
MDH.MDH_14 14 High part of MD - bit 14
MDH.MDH_13 13 High part of MD - bit 13
MDH.MDH_12 12 High part of MD - bit 12
MDH.MDH_11 11 High part of MD - bit 11
MDH.MDH_10 10 High part of MD - bit 10
MDH.MDH_9 9 High part of MD - bit 9
MDH.MDH_8 8 High part of MD - bit 8
MDH.MDH_7 7 High part of MD - bit 7
MDH.MDH_6 6 High part of MD - bit 6
MDH.MDH_5 5 High part of MD - bit 5
MDH.MDH_4 4 High part of MD - bit 4
MDH.MDH_3 3 High part of MD - bit 3
MDH.MDH_2 2 High part of MD - bit 2
MDH.MDH_1 1 High part of MD - bit 1
MDH.MDH_0 0 High part of MD - bit 0
MDL 0xFE0E CPU Multiply Divide Register - Low Word
MDL.MDL_15 15 Low part of MD - bit 15
MDL.MDL_14 14 Low part of MD - bit 14
MDL.MDL_13 13 Low part of MD - bit 13
MDL.MDL_12 12 Low part of MD - bit 12
MDL.MDL_11 11 Low part of MD - bit 11
MDL.MDL_10 10 Low part of MD - bit 10
MDL.MDL_9 9 Low part of MD - bit 9
MDL.MDL_8 8 Low part of MD - bit 8
MDL.MDL_7 7 Low part of MD - bit 7
MDL.MDL_6 6 Low part of MD - bit 6
MDL.MDL_5 5 Low part of MD - bit 5
MDL.MDL_4 4 Low part of MD - bit 4
MDL.MDL_3 3 Low part of MD - bit 3
MDL.MDL_2 2 Low part of MD - bit 2
MDL.MDL_1 1 Low part of MD - bit 1
MDL.MDL_0 0 Low part of MD - bit 0
CP 0xFE10 CPU Context Pointer Register
CP.CONTEXT_POINTER_11 11 Modifiable portion of register CP - bit 11
CP.CONTEXT_POINTER_10 10 Modifiable portion of register CP - bit 10
CP.CONTEXT_POINTER_9 9 Modifiable portion of register CP - bit 9
CP.CONTEXT_POINTER_8 8 Modifiable portion of register CP - bit 8
CP.CONTEXT_POINTER_7 7 Modifiable portion of register CP - bit 7
CP.CONTEXT_POINTER_6 6 Modifiable portion of register CP - bit 6
CP.CONTEXT_POINTER_5 5 Modifiable portion of register CP - bit 5
CP.CONTEXT_POINTER_4 4 Modifiable portion of register CP - bit 4
CP.CONTEXT_POINTER_3 3 Modifiable portion of register CP - bit 3
CP.CONTEXT_POINTER_2 2 Modifiable portion of register CP - bit 2
CP.CONTEXT_POINTER_1 1 Modifiable portion of register CP - bit 1
SP 0xFE12 CPU System Stack Pointer Register
SP.SP_15 15 Modifiable portion of register SP - bit 15
SP.SP_14 14 Modifiable portion of register SP - bit 14
SP.SP_13 13 Modifiable portion of register SP - bit 13
SP.SP_12 12 Modifiable portion of register SP - bit 12
SP.SP_11 11 Modifiable portion of register SP - bit 11
SP.SP_10 10 Modifiable portion of register SP - bit 10
SP.SP_9 9 Modifiable portion of register SP - bit 9
SP.SP_8 8 Modifiable portion of register SP - bit 8
SP.SP_7 7 Modifiable portion of register SP - bit 7
SP.SP_6 6 Modifiable portion of register SP - bit 6
SP.SP_5 5 Modifiable portion of register SP - bit 5
SP.SP_4 4 Modifiable portion of register SP - bit 4
SP.SP_3 3 Modifiable portion of register SP - bit 3
SP.SP_2 2 Modifiable portion of register SP - bit 2
SP.SP_1 1 Modifiable portion of register SP - bit 1
STKOV 0xFE14 CPU Stack Overflow Pointer Register
STKOV.STKOV_15 15 Modifiable portion of register STKOV - bit 15
STKOV.STKOV_14 14 Modifiable portion of register STKOV - bit 14
STKOV.STKOV_13 13 Modifiable portion of register STKOV - bit 13
STKOV.STKOV_12 12 Modifiable portion of register STKOV - bit 12
STKOV.STKOV_11 11 Modifiable portion of register STKOV - bit 11
STKOV.STKOV_10 10 Modifiable portion of register STKOV - bit 10
STKOV.STKOV_9 9 Modifiable portion of register STKOV - bit 9
STKOV.STKOV_8 8 Modifiable portion of register STKOV - bit 8
STKOV.STKOV_7 7 Modifiable portion of register STKOV - bit 7
STKOV.STKOV_6 6 Modifiable portion of register STKOV - bit 6
STKOV.STKOV_5 5 Modifiable portion of register STKOV - bit 5
STKOV.STKOV_4 4 Modifiable portion of register STKOV - bit 4
STKOV.STKOV_3 3 Modifiable portion of register STKOV - bit 3
STKOV.STKOV_2 2 Modifiable portion of register STKOV - bit 2
STKOV.STKOV_1 1 Modifiable portion of register STKOV - bit 1
STKUN 0xFE16 CPU Stack Underflow Pointer Register
STKUN.STKUN_15 15 Modifiable portion of register SP - bit 15
STKUN.STKUN_14 14 Modifiable portion of register SP - bit 14
STKUN.STKUN_13 13 Modifiable portion of register SP - bit 13
STKUN.STKUN_12 12 Modifiable portion of register SP - bit 12
STKUN.STKUN_11 11 Modifiable portion of register SP - bit 11
STKUN.STKUN_10 10 Modifiable portion of register SP - bit 10
STKUN.STKUN_9 9 Modifiable portion of register SP - bit 9
STKUN.STKUN_8 8 Modifiable portion of register SP - bit 8
STKUN.STKUN_7 7 Modifiable portion of register SP - bit 7
STKUN.STKUN_6 6 Modifiable portion of register SP - bit 6
STKUN.STKUN_5 5 Modifiable portion of register SP - bit 5
STKUN.STKUN_4 4 Modifiable portion of register SP - bit 4
STKUN.STKUN_3 3 Modifiable portion of register SP - bit 3
STKUN.STKUN_2 2 Modifiable portion of register SP - bit 2
STKUN.STKUN_1 1 Modifiable portion of register SP - bit 1
CPUCON1 0xFE18 Core Control Register
CPUCON1.VECSC_6 6 Scaling factor of Vector Table - bit 6
CPUCON1.VECSC_5 5 Scaling factor of Vector Table - bit 5
CPUCON1.WDTCTL 4 Configuration of Watch Dog Timer
CPUCON1.SGTDIS 3 Segmentation Disable/Enable Control
CPUCON1.INTSCXT 2 Enable Interruptibility of Switch Context
CPUCON1.BP 1 Enable Branch Prediction Unit
CPUCON1.ZCJ 0 Enable Zero Cycle Jump function
CPUCON2 0xFE1A Core Control Register
CPUCON2.FIFODEPTH_15 15 FIFO Depth configuration - bit 15
CPUCON2.FIFODEPTH_14 14 FIFO Depth configuration - bit 14
CPUCON2.FIFODEPTH_13 13 FIFO Depth configuration - bit 13
CPUCON2.FIFODEPTH_12 12 FIFO Depth configuration - bit 12
CPUCON2.FIFOFED_11 11 FIFO Fed configuration - 11
CPUCON2.FIFOFED_10 10 FIFO Fed configuration - 10
CPUCON2.BYPPF 9 Prefetch Bypass control
CPUCON2.BYPF 8 Fetch Bypass control
CPUCON2.EIOIAEN 7 Early IO Injection Acknowledge Enable
CPUCON2.STEN 6 Stall Instruction Enable
CPUCON2.LFIC 5 Linear Follower Instruction Cache
CPUCON2.OVRUN 4 Pipeline control
CPUCON2.RETST 3 Enable return Stack
CPUCON2.FASTBL 2 Enables the fast injection of block transfers
CPUCON2.SL 0 Enables short loop mode
MAL 0xFE5C MAC Accumulator - Low Word
MAL.MAL_15 15 Low part of Accumulator - bit 15
MAL.MAL_14 14 Low part of Accumulator - bit 14
MAL.MAL_13 13 Low part of Accumulator - bit 13
MAL.MAL_12 12 Low part of Accumulator - bit 12
MAL.MAL_11 11 Low part of Accumulator - bit 11
MAL.MAL_10 10 Low part of Accumulator - bit 10
MAL.MAL_9 9 Low part of Accumulator - bit 9
MAL.MAL_8 8 Low part of Accumulator - bit 8
MAL.MAL_7 7 Low part of Accumulator - bit 7
MAL.MAL_6 6 Low part of Accumulator - bit 6
MAL.MAL_5 5 Low part of Accumulator - bit 5
MAL.MAL_4 4 Low part of Accumulator - bit 4
MAL.MAL_3 3 Low part of Accumulator - bit 3
MAL.MAL_2 2 Low part of Accumulator - bit 2
MAL.MAL_1 1 Low part of Accumulator - bit 1
MAL.MAL_0 0 Low part of Accumulator - bit 0
MAH 0xFE5E MAC Accumulator - High Word
MAH.MAH_15 15 High part of Accumulator - bit 15
MAH.MAH_14 14 High part of Accumulator - bit 14
MAH.MAH_13 13 High part of Accumulator - bit 13
MAH.MAH_12 12 High part of Accumulator - bit 12
MAH.MAH_11 11 High part of Accumulator - bit 11
MAH.MAH_10 10 High part of Accumulator - bit 10
MAH.MAH_9 9 High part of Accumulator - bit 9
MAH.MAH_8 8 High part of Accumulator - bit 8
MAH.MAH_7 7 High part of Accumulator - bit 7
MAH.MAH_6 6 High part of Accumulator - bit 6
MAH.MAH_5 5 High part of Accumulator - bit 5
MAH.MAH_4 4 High part of Accumulator - bit 4
MAH.MAH_3 3 High part of Accumulator - bit 3
MAH.MAH_2 2 High part of Accumulator - bit 2
MAH.MAH_1 1 High part of Accumulator - bit 1
MAH.MAH_0 0 High part of Accumulator - bit 0
PECC0 0xFEC0 PEC Channel 0 Control Register
PECC0.EOPINT 14 End of PEC Interrupt Selection
PECC0.PLEV_13 13 PEC Level Selection - bit 13
PECC0.PLEV_12 12 PEC Level Selection - bit 12
PECC0.CL 11 Channel Link Control
PECC0.INC_10 10 Increment Control - bit 10
PECC0.INC_9 9 Increment Control - bit 9
PECC0.BWT 8 Byte / Word Transfer Selection
PECC0.COUNT_7 7 PEC Transfer Count - bit 7
PECC0.COUNT_6 6 PEC Transfer Count - bit 6
PECC0.COUNT_5 5 PEC Transfer Count - bit 5
PECC0.COUNT_4 4 PEC Transfer Count - bit 4
PECC0.COUNT_3 3 PEC Transfer Count - bit 3
PECC0.COUNT_2 2 PEC Transfer Count - bit 2
PECC0.COUNT_1 1 PEC Transfer Count - bit 1
PECC0.COUNT_0 0 PEC Transfer Count - bit 0
PECC1 0xFEC2 PEC Channel 1 Control Register
PECC1.EOPINT 14 End of PEC Interrupt Selection
PECC1.PLEV_13 13 PEC Level Selection - bit 13
PECC1.PLEV_12 12 PEC Level Selection - bit 12
PECC1.CL 11 Channel Link Control
PECC1.INC_10 10 Increment Control - bit 10
PECC1.INC_9 9 Increment Control - bit 9
PECC1.BWT 8 Byte / Word Transfer Selection
PECC1.COUNT_7 7 PEC Transfer Count - bit 7
PECC1.COUNT_6 6 PEC Transfer Count - bit 6
PECC1.COUNT_5 5 PEC Transfer Count - bit 5
PECC1.COUNT_4 4 PEC Transfer Count - bit 4
PECC1.COUNT_3 3 PEC Transfer Count - bit 3
PECC1.COUNT_2 2 PEC Transfer Count - bit 2
PECC1.COUNT_1 1 PEC Transfer Count - bit 1
PECC1.COUNT_0 0 PEC Transfer Count - bit 0
PECC2 0xFEC4 PEC Channel 2 Control Register
PECC2.EOPINT 14 End of PEC Interrupt Selection
PECC2.PLEV_13 13 PEC Level Selection - bit 13
PECC2.PLEV_12 12 PEC Level Selection - bit 12
PECC2.CL 11 Channel Link Control
PECC2.INC_10 10 Increment Control - bit 10
PECC2.INC_9 9 Increment Control - bit 9
PECC2.BWT 8 Byte / Word Transfer Selection
PECC2.COUNT_7 7 PEC Transfer Count - bit 7
PECC2.COUNT_6 6 PEC Transfer Count - bit 6
PECC2.COUNT_5 5 PEC Transfer Count - bit 5
PECC2.COUNT_4 4 PEC Transfer Count - bit 4
PECC2.COUNT_3 3 PEC Transfer Count - bit 3
PECC2.COUNT_2 2 PEC Transfer Count - bit 2
PECC2.COUNT_1 1 PEC Transfer Count - bit 1
PECC2.COUNT_0 0 PEC Transfer Count - bit 0
PECC3 0xFEC6 PEC Channel 3 Control Register
PECC3.EOPINT 14 End of PEC Interrupt Selection
PECC3.PLEV_13 13 PEC Level Selection - bit 13
PECC3.PLEV_12 12 PEC Level Selection - bit 12
PECC3.CL 11 Channel Link Control
PECC3.INC_10 10 Increment Control - bit 10
PECC3.INC_9 9 Increment Control - bit 9
PECC3.BWT 8 Byte / Word Transfer Selection
PECC3.COUNT_7 7 PEC Transfer Count - bit 7
PECC3.COUNT_6 6 PEC Transfer Count - bit 6
PECC3.COUNT_5 5 PEC Transfer Count - bit 5
PECC3.COUNT_4 4 PEC Transfer Count - bit 4
PECC3.COUNT_3 3 PEC Transfer Count - bit 3
PECC3.COUNT_2 2 PEC Transfer Count - bit 2
PECC3.COUNT_1 1 PEC Transfer Count - bit 1
PECC3.COUNT_0 0 PEC Transfer Count - bit 0
PECC4 0xFEC8 PEC Channel 4 Control Register
PECC4.EOPINT 14 End of PEC Interrupt Selection
PECC4.PLEV_13 13 PEC Level Selection - bit 13
PECC4.PLEV_12 12 PEC Level Selection - bit 12
PECC4.CL 11 Channel Link Control
PECC4.INC_10 10 Increment Control - bit 10
PECC4.INC_9 9 Increment Control - bit 9
PECC4.BWT 8 Byte / Word Transfer Selection
PECC4.COUNT_7 7 PEC Transfer Count - bit 7
PECC4.COUNT_6 6 PEC Transfer Count - bit 6
PECC4.COUNT_5 5 PEC Transfer Count - bit 5
PECC4.COUNT_4 4 PEC Transfer Count - bit 4
PECC4.COUNT_3 3 PEC Transfer Count - bit 3
PECC4.COUNT_2 2 PEC Transfer Count - bit 2
PECC4.COUNT_1 1 PEC Transfer Count - bit 1
PECC4.COUNT_0 0 PEC Transfer Count - bit 0
PECC5 0xFECA PEC Channel 5 Control Register
PECC5.EOPINT 14 End of PEC Interrupt Selection
PECC5.PLEV_13 13 PEC Level Selection - bit 13
PECC5.PLEV_12 12 PEC Level Selection - bit 12
PECC5.CL 11 Channel Link Control
PECC5.INC_10 10 Increment Control - bit 10
PECC5.INC_9 9 Increment Control - bit 9
PECC5.BWT 8 Byte / Word Transfer Selection
PECC5.COUNT_7 7 PEC Transfer Count - bit 7
PECC5.COUNT_6 6 PEC Transfer Count - bit 6
PECC5.COUNT_5 5 PEC Transfer Count - bit 5
PECC5.COUNT_4 4 PEC Transfer Count - bit 4
PECC5.COUNT_3 3 PEC Transfer Count - bit 3
PECC5.COUNT_2 2 PEC Transfer Count - bit 2
PECC5.COUNT_1 1 PEC Transfer Count - bit 1
PECC5.COUNT_0 0 PEC Transfer Count - bit 0
PECC6 0xFECC PEC Channel 6 Control Register
PECC6.EOPINT 14 End of PEC Interrupt Selection
PECC6.PLEV_13 13 PEC Level Selection - bit 13
PECC6.PLEV_12 12 PEC Level Selection - bit 12
PECC6.CL 11 Channel Link Control
PECC6.INC_10 10 Increment Control - bit 10
PECC6.INC_9 9 Increment Control - bit 9
PECC6.BWT 8 Byte / Word Transfer Selection
PECC6.COUNT_7 7 PEC Transfer Count - bit 7
PECC6.COUNT_6 6 PEC Transfer Count - bit 6
PECC6.COUNT_5 5 PEC Transfer Count - bit 5
PECC6.COUNT_4 4 PEC Transfer Count - bit 4
PECC6.COUNT_3 3 PEC Transfer Count - bit 3
PECC6.COUNT_2 2 PEC Transfer Count - bit 2
PECC6.COUNT_1 1 PEC Transfer Count - bit 1
PECC6.COUNT_0 0 PEC Transfer Count - bit 0
PECC7 0xFECE PEC Channel 7 Control Register
PECC7.EOPINT 14 End of PEC Interrupt Selection
PECC7.PLEV_13 13 PEC Level Selection - bit 13
PECC7.PLEV_12 12 PEC Level Selection - bit 12
PECC7.CL 11 Channel Link Control
PECC7.INC_10 10 Increment Control - bit 10
PECC7.INC_9 9 Increment Control - bit 9
PECC7.BWT 8 Byte / Word Transfer Selection
PECC7.COUNT_7 7 PEC Transfer Count - bit 7
PECC7.COUNT_6 6 PEC Transfer Count - bit 6
PECC7.COUNT_5 5 PEC Transfer Count - bit 5
PECC7.COUNT_4 4 PEC Transfer Count - bit 4
PECC7.COUNT_3 3 PEC Transfer Count - bit 3
PECC7.COUNT_2 2 PEC Transfer Count - bit 2
PECC7.COUNT_1 1 PEC Transfer Count - bit 1
PECC7.COUNT_0 0 PEC Transfer Count - bit 0
IDX0 0xFF08 MAC Address Pointer 0
IDX0.IDX_15 15 Modifiable portion of register IDX0 - bit 15
IDX0.IDX_14 14 Modifiable portion of register IDX0 - bit 14
IDX0.IDX_13 13 Modifiable portion of register IDX0 - bit 13
IDX0.IDX_12 12 Modifiable portion of register IDX0 - bit 12
IDX0.IDX_11 11 Modifiable portion of register IDX0 - bit 11
IDX0.IDX_10 10 Modifiable portion of register IDX0 - bit 10
IDX0.IDX_9 9 Modifiable portion of register IDX0 - bit 9
IDX0.IDX_8 8 Modifiable portion of register IDX0 - bit 8
IDX0.IDX_7 7 Modifiable portion of register IDX0 - bit 7
IDX0.IDX_6 6 Modifiable portion of register IDX0 - bit 6
IDX0.IDX_5 5 Modifiable portion of register IDX0 - bit 5
IDX0.IDX_4 4 Modifiable portion of register IDX0 - bit 4
IDX0.IDX_3 3 Modifiable portion of register IDX0 - bit 3
IDX0.IDX_2 2 Modifiable portion of register IDX0 - bit 2
IDX0.IDX_1 1 Modifiable portion of register IDX0 - bit 1
IDX1 0xFF0A MAC Address Pointer 1
IDX1.IDX_15 15 Modifiable portion of register IDX1 - bit 15
IDX1.IDX_14 14 Modifiable portion of register IDX1 - bit 14
IDX1.IDX_13 13 Modifiable portion of register IDX1 - bit 13
IDX1.IDX_12 12 Modifiable portion of register IDX1 - bit 12
IDX1.IDX_11 11 Modifiable portion of register IDX1 - bit 11
IDX1.IDX_10 10 Modifiable portion of register IDX1 - bit 10
IDX1.IDX_9 9 Modifiable portion of register IDX1 - bit 9
IDX1.IDX_8 8 Modifiable portion of register IDX1 - bit 8
IDX1.IDX_7 7 Modifiable portion of register IDX1 - bit 7
IDX1.IDX_6 6 Modifiable portion of register IDX1 - bit 6
IDX1.IDX_5 5 Modifiable portion of register IDX1 - bit 5
IDX1.IDX_4 4 Modifiable portion of register IDX1 - bit 4
IDX1.IDX_3 3 Modifiable portion of register IDX1 - bit 3
IDX1.IDX_2 2 Modifiable portion of register IDX1 - bit 2
IDX1.IDX_1 1 Modifiable portion of register IDX1 - bit 1
SPSEG 0xFF0C Stack Pointer Segment Register
SPSEG.SPSEGNR_7 7 Stack Pointer Segment Number - bit 7
SPSEG.SPSEGNR_6 6 Stack Pointer Segment Number - bit 6
SPSEG.SPSEGNR_5 5 Stack Pointer Segment Number - bit 5
SPSEG.SPSEGNR_4 4 Stack Pointer Segment Number - bit 4
SPSEG.SPSEGNR_3 3 Stack Pointer Segment Number - bit 3
SPSEG.SPSEGNR_2 2 Stack Pointer Segment Number - bit 2
SPSEG.SPSEGNR_1 1 Stack Pointer Segment Number - bit 1
SPSEG.SPSEGNR_0 0 Stack Pointer Segment Number - bit 0
MDC 0xFF0E CPU Multiply Divide Control Register
MDC.MDRIU 4 Multiply/Divide Register In Use
PSW 0xFF10 CPU Program Status Word
PSW.ILVL_15 15 CPU Priority Level - bit 15
PSW.ILVL_14 14 CPU Priority Level - bit 14
PSW.ILVL_13 13 CPU Priority Level - bit 13
PSW.ILVL_12 12 CPU Priority Level - bit 12
PSW.IEN 11 Interrupt/PEC Enable Flag (globally)
PSW.HLDEN 10 Interrupt and EBC Control Fields
PSW.BANK_9 9 Reserved for register file bank selection - bit 9
PSW.BANK_8 8 Reserved for register file bank selection - bit 8
PSW.USR1 7 User General Purpose Flag
PSW.USR0 6 User General Purpose Flag
PSW.MULIP 5 Multiplication/Division In Progress
PSW.E 4 End of Table Flag
PSW.Z 3 Zero Flag
PSW.V 2 Overflow Result
PSW.C 1 Carry Flag
PSW.N 0 Negative Result
VECSEG 0xFF12 Vector Table Segment Register
VECSEG.VECSEG_7 7 Segment number of the Vector Table - bit 7
VECSEG.VECSEG_6 6 Segment number of the Vector Table - bit 6
VECSEG.VECSEG_5 5 Segment number of the Vector Table - bit 5
VECSEG.VECSEG_4 4 Segment number of the Vector Table - bit 4
VECSEG.VECSEG_3 3 Segment number of the Vector Table - bit 3
VECSEG.VECSEG_2 2 Segment number of the Vector Table - bit 2
VECSEG.VECSEG_1 1 Segment number of the Vector Table - bit 1
VECSEG.VECSEG_0 0 Segment number of the Vector Table - bit 0
ZEROS 0xFF1C Constant Value 0's Register
ONES 0xFF1E Constant Value 1's Register
PECISNC 0xFFA8 PEC Interrupt Subnode Control Register
PECISNC.C7IR 15 Interrupt Sub-node Request Flag of PEC Channel 7
PECISNC.C7IE 14 Interrupt Sub-node Enable Control Bit of PEC Channel 7
PECISNC.C6IR 13 Interrupt Sub-node Request Flag of PEC Channel 6
PECISNC.C6IE 12 Interrupt Sub-node Enable Control Bit of PEC Channel 6
PECISNC.C5IR 11 Interrupt Sub-node Request Flag of PEC Channel 5
PECISNC.C5IE 10 Interrupt Sub-node Enable Control Bit of PEC Channel 5
PECISNC.C4IR 9 Interrupt Sub-node Request Flag of PEC Channel 4
PECISNC.C4IE 8 Interrupt Sub-node Enable Control Bit of PEC Channel 4
PECISNC.C3IR 7 Interrupt Sub-node Request Flag of PEC Channel 3
PECISNC.C3IE 6 Interrupt Sub-node Enable Control Bit of PEC Channel 3
PECISNC.C2IR 5 Interrupt Sub-node Request Flag of PEC Channel 2
PECISNC.C2IE 4 Interrupt Sub-node Enable Control Bit of PEC Channel 2
PECISNC.C1IR 3 Interrupt Sub-node Request Flag of PEC Channel 1
PECISNC.C1IE 2 Interrupt Sub-node Enable Control Bit of PEC Channel 1
PECISNC.C0IR 1 Interrupt Sub-node Request Flag of PEC Channel 0
PECISNC.C0IE 0 Interrupt Sub-node Enable Control Bit of PEC Channel 0
TFR 0xFFAC Trap Flag Register
TFR.NMI 15 Non Maskable Interrupt Flag
TFR.STKOF 14 Stack Overflow Flag
TFR.STKUF 13 Stack Underflow Flag
TFR.SOFTBRK 12 Software Break
TFR.UNDOPC 7 Undefined Opcode Flag
TFR.PARFLT 4 Parity Fault
TFR.PRTFLT 3 Protection Fault Flag
TFR.ILLOPA 2 Illegal Word Operand Access Flag
MRW 0xFFDA MAC Repeat Word
MRW.REPEAT_COUNT_15 15 16-bit loop counter - bit 15
MRW.REPEAT_COUNT_14 14 16-bit loop counter - bit 14
MRW.REPEAT_COUNT_13 13 16-bit loop counter - bit 13
MRW.REPEAT_COUNT_12 12 16-bit loop counter - bit 12
MRW.REPEAT_COUNT_11 11 16-bit loop counter - bit 11
MRW.REPEAT_COUNT_10 10 16-bit loop counter - bit 10
MRW.REPEAT_COUNT_9 9 16-bit loop counter - bit 9
MRW.REPEAT_COUNT_8 8 16-bit loop counter - bit 8
MRW.REPEAT_COUNT_7 7 16-bit loop counter - bit 7
MRW.REPEAT_COUNT_6 6 16-bit loop counter - bit 6
MRW.REPEAT_COUNT_5 5 16-bit loop counter - bit 5
MRW.REPEAT_COUNT_4 4 16-bit loop counter - bit 4
MRW.REPEAT_COUNT_3 3 16-bit loop counter - bit 3
MRW.REPEAT_COUNT_2 2 16-bit loop counter - bit 2
MRW.REPEAT_COUNT_1 1 16-bit loop counter - bit 1
MRW.REPEAT_COUNT_0 0 16-bit loop counter - bit 0
MCW 0xFFDC MAC Control Word
MCW.MP 10 One-bit scaler control
MCW.MS 9 Saturation control
MSW 0xFFDE MAC Status Word
MSW.MV 14 Overflow Flag
MSW.MSL 13 Sticky Limit Flag
MSW.ME 12 MAC Extension Flag
MSW.MSV 11 Sticky Overflow Flag
MSW.MC 10 Carry Flag
MSW.MZ 9 Zero Flag
MSW.MN 8 Negative Result
MSW.MAE_7 7 The most significant bits of the 40-bit Accumulator - bit 7
MSW.MAE_6 6 The most significant bits of the 40-bit Accumulator - bit 6
MSW.MAE_5 5 The most significant bits of the 40-bit Accumulator - bit 5
MSW.MAE_4 4 The most significant bits of the 40-bit Accumulator - bit 4
MSW.MAE_3 3 The most significant bits of the 40-bit Accumulator - bit 3
MSW.MAE_2 2 The most significant bits of the 40-bit Accumulator - bit 2
MSW.MAE_1 1 The most significant bits of the 40-bit Accumulator - bit 1
MSW.MAE_0 0 The most significant bits of the 40-bit Accumulator - bit 0
.XC161CJ
; MEMORY MAP
area DATA EXT_MEM 0x0000:0x8000 External Memory
area BSS RESERVED 0x8000:0xC000 Reserved for Internal Data SRAM
area DATA SRAM 0xC000:0xD000 Data SRAM
area BSS RESERVED 0xD000:0xE000
area BSS RESERVED 0xE000:0xE600
area DATA XSFR_1 0xE600:0xEA00 XSFR Area
area BSS RESERVED 0xEA00:0xEC00
area DATA XSFR_2 0xEC00:0xF000 XSFR Area
area DATA E_SFR 0xF000:0xF200
area BSS RESERVED 0xF200:0xF600 Reserved for DPRAM
area DATA DPRAM 0xF600:0xFE00
area DATA SFR 0xFE00:0x10000 SFR Area
; Interrupt and reset vector assignments
entry RESET_ 0x0000 RESET
entry NMITRAP_ 0x0008 Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP_ 0x0010 Stack Overflow (Class A Hardware Traps)
entry STUTRAP_ 0x0018 Stack Underflow (Class A Hardware Traps)
entry SBRKTRAP_ 0x0020 Software Break (Class A Hardware Traps)
entry BTRAP_ 0x0028 BTRAP (Class B Hardware Traps)
entry CC1_CC0IC_ 0x0040 CAPCOM Register 0
entry CC1_CC1IC_ 0x0044 CAPCOM Register 1
entry CC1_CC2IC_ 0x0048 CAPCOM Register 2
entry CC1_CC3IC_ 0x004C CAPCOM Register 3
entry CC1_CC4IC_ 0x0050 CAPCOM Register 4
entry CC1_CC5IC_ 0x0054 CAPCOM Register 5
entry CC1_CC6IC_ 0x0058 CAPCOM Register 6
entry CC1_CC7IC_ 0x005C CAPCOM Register 7
entry CC1_CC8IC_ 0x0060 CAPCOM Register 8
entry CC1_CC9IC_ 0x0064 CAPCOM Register 9
entry CC1_CC10IC_ 0x0068 CAPCOM Register 10
entry CC1_CC11IC_ 0x006C CAPCOM Register 11
entry CC1_CC12IC_ 0x0070 CAPCOM Register 12
entry CC1_CC13IC_ 0x0074 CAPCOM Register 13
entry CC1_CC14IC_ 0x0078 CAPCOM Register 14
entry CC1_CC15IC_ 0x007C CAPCOM Register 15
entry CC1_T0IC_ 0x0080 CAPCOM Timer 0
entry CC1_T1IC_ 0x0084 CAPCOM Timer 1
entry GPT12E_T2IC_ 0x0088 GPT1 Timer 2
entry GPT12E_T3IC_ 0x008C GPT1 Timer 3
entry GPT12E_T4IC_ 0x0090 GPT1 Timer 4
entry GPT12E_T5IC_ 0x0094 GPT2 Timer 5
entry GPT12E_T6IC_ 0x0098 GPT2 Timer 6
entry GPT12E_CRIC_ 0x009C GPT2 CAPREL Reg.
entry ADC_CIC_ 0x00A0 A/D Conversion Compl.
entry ADC_EIC_ 0x00A4 A/D Overrun Error
entry ASC0_TIC_ 0x00A8 ASC0 Transmit
entry ASC0_RIC_ 0x00AC ASC0 Receive
entry ASC0_EIC_ 0x00B0 ASC0 Error
entry SSC0_TIC_ 0x00B4 SSC0 Transmit
entry SSC0_RIC_ 0x00B8 SSC0 Receive
entry SSC0_EIC_ 0x00BC SSC0 Error
entry CC2_CC16IC_ 0x00C0 CAPCOM Register 16
entry CC2_CC17IC_ 0x00C4 CAPCOM Register 17
entry CC2_CC18IC_ 0x00C8 CAPCOM Register 18
entry CC2_CC19IC_ 0x00CC CAPCOM Register 19
entry CC2_CC20IC_ 0x00D0 CAPCOM Register 20
entry CC2_CC21IC_ 0x00D4 CAPCOM Register 21
entry CC2_CC22IC_ 0x00D8 CAPCOM Register 22
entry CC2_CC23IC_ 0x00DC CAPCOM Register 23
entry CC2_CC24IC_ 0x00E0 CAPCOM Register 24
entry CC2_CC25IC_ 0x00E4 CAPCOM Register 25
entry CC2_CC26IC_ 0x00E8 CAPCOM Register 26
entry CC2_CC27IC_ 0x00EC CAPCOM Register 27
entry CC2_CC28IC_ 0x00F0 CAPCOM Register 28
entry CC2_T7IC_ 0x00F4 CAPCOM Timer 7
entry GG2_T8IC_ 0x00F8 CAPCOM Timer 8
entry ASC1_ABIC_ 0x0108 ASC1 Autobaud
entry PLLIC_ 0x010C PLL/OWD
entry CC2_CC29IC_ 0x0110 CAPCOM Register 29
entry CC2_CC30IC_ 0x0114 CAPCOM Register 30
entry CC2_CC31IC_ 0x0118 CAPCOM Register 31
entry ASC0_TBIC_ 0x011C ASC0 Transmit Buffer
entry ASC1_TIC_ 0x0120 ASC1 Transmit 2
entry ASC1_RIC_ 0x0124 ASC1 Receive
entry ASC1_EIC_ 0x0128 ASC1 Error
entry EOPIC_ 0x0130 End of PEC Subch.
entry CCU6_T12IC_ 0x0134 CAPCOM6 Timer T12
entry CCU6_T13IC_ 0x0138 CAPCOM6 Timer T13
entry CCU6_EIC_ 0x013C CAPCOM6 Emergency
entry CCU6_IC_ 0x0140 CAPCOM6
entry SSC1_TIC_ 0x0144 SSC1 Transmit
entry SSC1_RIC_ 0x0148 SSC1 Receive
entry SSC1_EIC_ 0x014C SSC1 Error
entry CAN_0IC_ 0x0150 CAN0
entry CAN_1IC_ 0x0154 CAN1
entry CAN_2IC_ 0x0158 CAN2
entry CAN_3IC_ 0x015C CAN3
entry CAN_4IC_ 0x0164 CAN4
entry CAN_5IC_ 0x0168 CAN5
entry CAN_6IC_ 0x016C CAN6
entry CAN_7IC_ 0x0170 CAN7
entry RTC_IC_ 0x0174 RTC
entry ASC1_TBIC_ 0x0178 ASC1 Transmit Buffer
entry ASC0_ABIC_ 0x017C ASC0 Autobaud
; INPUT/OUTPUT PORTS
; Addressing Modes to Access Word-GPRs (p.100)
; R0 General Purpose Register 0
; R0 General Purpose Register 0
; R1 General Purpose Register 1
; R1 General Purpose Register 1
; R10 General Purpose Register 10
; R10 General Purpose Register 10
; R11 General Purpose Register 11
; R11 General Purpose Register 11
; R12 General Purpose Register 12
; R12 General Purpose Register 12
; R13 General Purpose Register 13
; R13 General Purpose Register 13
; R14 General Purpose Register 14
; R14 General Purpose Register 14
; R15 General Purpose Register 15
; R15 General Purpose Register 15
; R2 General Purpose Register 2
; R2 General Purpose Register 2
; R3 General Purpose Register 3
; R3 General Purpose Register 3
; R4 General Purpose Register 4
; R4 General Purpose Register 4
; R5 General Purpose Register 5
; R5 General Purpose Register 5
; R6 General Purpose Register 6
; R6 General Purpose Register 6
; R7 General Purpose Register 7
; R7 General Purpose Register 7
; R8 General Purpose Register 8
; R8 General Purpose Register 8
; R9 General Purpose Register 9
; R9 General Purpose Register 9
IIC_CFG 0xE600 IIC Configuration Register
IIC_CON 0xE602 IIC Control Register
IIC_ST 0xE604 IIC Status Register
IIC_ADR 0xE606 IIC Address Register
IIC_RTBL 0xE608 IIC Receive/Transmit Buffer Low Register
IIC_RTBH 0xE60A IIC Receive/Transmit Buffer High Register
IIC_ID 0xE60C IIC Module Identification Register
CCU6_T12 0xE890 Timer T12 Counter Register
CCU6_T12PR 0xE892 Timer 12 Period Register
CCU6_T12DTC 0xE894 Dead-Time Control Register for Timer 12
CCU6_CC60R 0xE898 Capture/Compare Register for Channel CC60
CCU6_CC61R 0xE89A Capture/Compare Register for Channel CC61
CCU6_CC62R 0xE89C Capture/Compare Register for Channel CC62
CCU6_CC60SR 0xE8A0 Capture/Compare Shadow Register for Channel 0
CCU6_CC61SR 0xE8A2 Capture/Compare Shadow Register for Channel 1
CCU6_CC62SR 0xE8A4 Capture/Compare Shadow Register for Channel 2
CCU6_TCTR4 0xE8A6 Timer Control Register 4
CCU6_CMPSTAT 0xE8A8 Compare Status Register
CCU6_CMPMODIF 0xE8AA Compare State Modification Register
CCU6_TCTR0 0xE8AC Timer Control Register 0
CCU6_TCTR2 0xE8AE Timer Control Register 2
CCU6_T13 0xE8B0 Timer T13 Counter Register
CCU6_T13PR 0xE8B2 Timer 13 Period Register
CCU6_CC63R 0xE8B4 Compare Register for Channel CC63
CCU6_CC63SR 0xE8B6 Compare Shadow Register for Channel CC63
CCU6_MODCTR 0xE8C0 Modulation Control Register
CCU6_TRPCTR 0xE8C2 Trap Control Register
CCU6_PSLR 0xE8C4 Passive State Level Register
CCU6_T12MSEL 0xE8C6 T12 Capture/Compare Mode Select Register
CCU6_MCMOUTS 0xE8CA Multi-Channel Mode Output Shadow Register
CCU6_MCMOUT 0xE8CC Multi-Channel Mode Output Register
CCU6_MCMCTR 0xE8CE Multi-Channel Mode Control Register
CCU6_IS 0xE8D0 Capture/Compare Interrupt Status Register
CCU6_ISS 0xE8D2 Capture/Compare Interrupt Status Set Register
CCU6_ISR 0xE8D4 Capture/Compare Interrupt Status Reset Register
CCU6_INP 0xE8D6 Capture/Compare Interrupt Node Pointer Register
CCU6_IEN 0xE8D8 Capture/Compare Interrupt Enable Register
SDLM_PISEL 0xE904 SDLM Port Input Select Register
SDLM_ID 0xE908 SDLM Module Identification Register
SDLM_GLOBCON 0xE910 Global Control Register
SDLM_CLKDIV 0xE914 Clock Divider Register
SDLM_TXDELAY 0xE916 Transceiver Delay Register
SDLM_IFRVAL 0xE918 In-Frame Response Value Register
SDLM_BUFFSTAT 0xE91C Buffer Status Register
SDLM_TRANSSTAT 0xE91E Transfer Register
SDLM_BUSSTAT 0xE920 Bus Status Register
SDLM_ERRSTAT 0xE922 Error Status Register
SDLM_BUFFCON 0xE924 Buffer Control Register
SDLM_FLAGRST 0xE928 Flag Reset Register
SDLM_INTCON 0xE92C Interrupt Control Register
SDLM_TXD0 0xE930 Transmit Data Register
SDLM_TXD2 0xE932 Transmit Data Register
SDLM_TXD4 0xE934 Transmit Data Register
SDLM_TXD6 0xE936 Transmit Data Register
SDLM_TXD8 0xE938 Transmit Data Register
SDLM_TXD10 0xE93A Transmit Data Register
SDLM_TXCNT 0xE93C Bus Transmit Byte Counter
SDLM_TXCPU 0xE93E CPU Transmit Byte Counter
SDLM_RXD00 0xE940 Receive Data Register
SDLM_RXD02 0xE942 Receive Data Register
SDLM_RXD04 0xE944 Receive Data Register
SDLM_RXD06 0xE946 Receive Data Register
SDLM_RXD08 0xE948 Receive Data Register
SDLM_RXD010 0xE94A Receive Data Register
SDLM_RXCNT 0xE94C Bus Receive Byte Counter
SDLM_RXCPU 0xE94E CPU Receive Byte Counter
SDLM_RXD10 0xE950 Receive Data Register
SDLM_RXD12 0xE952 Receive Data Register
SDLM_RXD14 0xE954 Receive Data Register
SDLM_RXD16 0xE956 Receive Data Register
SDLM_RXD18 0xE958 Receive Data Register
SDLM_RXD110 0xE95A Receive Data Register
SDLM_RXCNTB 0xE95C Bus Receive Byte Counter Register (on bus side)
SDLM_SOFPTR 0xE960 Start-of-Frame Pointer Register
FINT0CSP 0xEC00 Fast Interrupt Control Register 0
FINT0CSP.EN 15 Fast Interrupt Enable
FINT0CSP.GPX 12 Group Priority Extension
FINT0CSP.ILVL_11 11 Interrupt Priority Level bit 11
FINT0CSP.ILVL_10 10 Interrupt Priority Level bit 10
FINT0CSP.GLVL_9 9 Group Priority Level bit 9
FINT0CSP.GLVL_8 8 Group Priority Level bit 8
FINT0CSP.SEG_7 7 Segment Number of Interrupt Service Routine bit 7
FINT0CSP.SEG_6 6 Segment Number of Interrupt Service Routine bit 6
FINT0CSP.SEG_5 5 Segment Number of Interrupt Service Routine bit 5
FINT0CSP.SEG_4 4 Segment Number of Interrupt Service Routine bit 4
FINT0CSP.SEG_3 3 Segment Number of Interrupt Service Routine bit 3
FINT0CSP.SEG_2 2 Segment Number of Interrupt Service Routine bit 2
FINT0CSP.SEG_1 1 Segment Number of Interrupt Service Routine bit 1
FINT0CSP.SEG_0 0 Segment Number of Interrupt Service Routine bit 0
FINT0ADDR 0xEC02 Fast Interrupt Address Register 0
FINT0ADDR.ADDR_15 15 Address of Interrupt Service Routine bit 15
FINT0ADDR.ADDR_14 14 Address of Interrupt Service Routine bit 14
FINT0ADDR.ADDR_13 13 Address of Interrupt Service Routine bit 13
FINT0ADDR.ADDR_12 12 Address of Interrupt Service Routine bit 12
FINT0ADDR.ADDR_11 11 Address of Interrupt Service Routine bit 11
FINT0ADDR.ADDR_10 10 Address of Interrupt Service Routine bit 10
FINT0ADDR.ADDR_9 9 Address of Interrupt Service Routine bit 9
FINT0ADDR.ADDR_8 8 Address of Interrupt Service Routine bit 8
FINT0ADDR.ADDR_7 7 Address of Interrupt Service Routine bit 7
FINT0ADDR.ADDR_6 6 Address of Interrupt Service Routine bit 6
FINT0ADDR.ADDR_5 5 Address of Interrupt Service Routine bit 5
FINT0ADDR.ADDR_4 4 Address of Interrupt Service Routine bit 4
FINT0ADDR.ADDR_3 3 Address of Interrupt Service Routine bit 3
FINT0ADDR.ADDR_2 2 Address of Interrupt Service Routine bit 2
FINT0ADDR.ADDR_1 1 Address of Interrupt Service Routine bit 1
FINT1CSP 0xEC04 Fast Interrupt Control Register 1
FINT1CSP.EN 15 Fast Interrupt Enable
FINT1CSP.GPX 12 Group Priority Extension
FINT1CSP.ILVL_11 11 Interrupt Priority Level bit 11
FINT1CSP.ILVL_10 10 Interrupt Priority Level bit 10
FINT1CSP.GLVL_9 9 Group Priority Level bit 9
FINT1CSP.GLVL_8 8 Group Priority Level bit 8
FINT1CSP.SEG_7 7 Segment Number of Interrupt Service Routine bit 7
FINT1CSP.SEG_6 6 Segment Number of Interrupt Service Routine bit 6
FINT1CSP.SEG_5 5 Segment Number of Interrupt Service Routine bit 5
FINT1CSP.SEG_4 4 Segment Number of Interrupt Service Routine bit 4
FINT1CSP.SEG_3 3 Segment Number of Interrupt Service Routine bit 3
FINT1CSP.SEG_2 2 Segment Number of Interrupt Service Routine bit 2
FINT1CSP.SEG_1 1 Segment Number of Interrupt Service Routine bit 1
FINT1CSP.SEG_0 0 Segment Number of Interrupt Service Routine bit 0
FINT1ADDR 0xEC06 Fast Interrupt Address Register 1
FINT1ADDR.ADDR_15 15 Address of Interrupt Service Routine bit 15
FINT1ADDR.ADDR_14 14 Address of Interrupt Service Routine bit 14
FINT1ADDR.ADDR_13 13 Address of Interrupt Service Routine bit 13
FINT1ADDR.ADDR_12 12 Address of Interrupt Service Routine bit 12
FINT1ADDR.ADDR_11 11 Address of Interrupt Service Routine bit 11
FINT1ADDR.ADDR_10 10 Address of Interrupt Service Routine bit 10
FINT1ADDR.ADDR_9 9 Address of Interrupt Service Routine bit 9
FINT1ADDR.ADDR_8 8 Address of Interrupt Service Routine bit 8
FINT1ADDR.ADDR_7 7 Address of Interrupt Service Routine bit 7
FINT1ADDR.ADDR_6 6 Address of Interrupt Service Routine bit 6
FINT1ADDR.ADDR_5 5 Address of Interrupt Service Routine bit 5
FINT1ADDR.ADDR_4 4 Address of Interrupt Service Routine bit 4
FINT1ADDR.ADDR_3 3 Address of Interrupt Service Routine bit 3
FINT1ADDR.ADDR_2 2 Address of Interrupt Service Routine bit 2
FINT1ADDR.ADDR_1 1 Address of Interrupt Service Routine bit 1
BNKSEL0 0xEC20 Register Bank Selection Register 0 (??? p.206)
BNKSEL0.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL0.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL0.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL0.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL0.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL0.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL0.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL0.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL0.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL0.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL0.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL0.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL0.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL0.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL0.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL0.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL1 0xEC22 Register Bank Selection Register 1
BNKSEL1.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL1.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL1.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL1.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL1.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL1.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL1.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL1.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL1.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL1.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL1.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL1.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL1.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL1.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL1.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL1.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL2 0xEC24 Register Bank Selection Register 2
BNKSEL2.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL2.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL2.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL2.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL2.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL2.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL2.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL2.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL2.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL2.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL2.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL2.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL2.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL2.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL2.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL2.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL3 0xEC26 Register Bank Selection Register 3
BNKSEL3.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL3.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL3.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL3.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL3.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL3.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL3.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL3.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL3.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL3.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL3.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL3.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL3.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL3.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL3.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL3.GPRSEL0_0 0 Register Bank Selection 0_0
SRCP0 0xEC40 PEC Channel 0 Source Pointer
SRCP0.SRCP0_15 15 Source Pointer Address of Channel 0 bit 15
SRCP0.SRCP0_14 14 Source Pointer Address of Channel 0 bit 14
SRCP0.SRCP0_13 13 Source Pointer Address of Channel 0 bit 13
SRCP0.SRCP0_12 12 Source Pointer Address of Channel 0 bit 12
SRCP0.SRCP0_11 11 Source Pointer Address of Channel 0 bit 11
SRCP0.SRCP0_10 10 Source Pointer Address of Channel 0 bit 10
SRCP0.SRCP0_9 9 Source Pointer Address of Channel 0 bit 9
SRCP0.SRCP0_8 8 Source Pointer Address of Channel 0 bit 8
SRCP0.SRCP0_7 7 Source Pointer Address of Channel 0 bit 7
SRCP0.SRCP0_6 6 Source Pointer Address of Channel 0 bit 6
SRCP0.SRCP0_5 5 Source Pointer Address of Channel 0 bit 5
SRCP0.SRCP0_4 4 Source Pointer Address of Channel 0 bit 4
SRCP0.SRCP0_3 3 Source Pointer Address of Channel 0 bit 3
SRCP0.SRCP0_2 2 Source Pointer Address of Channel 0 bit 2
SRCP0.SRCP0_1 1 Source Pointer Address of Channel 0 bit 1
SRCP0.SRCP0_0 0 Source Pointer Address of Channel 0 bit 0
DSTP0 0xEC42 PEC Channel 0 Destination Pointer
DSTP0.DSTP0_15 15 Destination Pointer Address of Channel 0 bit 15
DSTP0.DSTP0_14 14 Destination Pointer Address of Channel 0 bit 14
DSTP0.DSTP0_13 13 Destination Pointer Address of Channel 0 bit 13
DSTP0.DSTP0_12 12 Destination Pointer Address of Channel 0 bit 12
DSTP0.DSTP0_11 11 Destination Pointer Address of Channel 0 bit 11
DSTP0.DSTP0_10 10 Destination Pointer Address of Channel 0 bit 10
DSTP0.DSTP0_9 9 Destination Pointer Address of Channel 0 bit 9
DSTP0.DSTP0_8 8 Destination Pointer Address of Channel 0 bit 8
DSTP0.DSTP0_7 7 Destination Pointer Address of Channel 0 bit 7
DSTP0.DSTP0_6 6 Destination Pointer Address of Channel 0 bit 6
DSTP0.DSTP0_5 5 Destination Pointer Address of Channel 0 bit 5
DSTP0.DSTP0_4 4 Destination Pointer Address of Channel 0 bit 4
DSTP0.DSTP0_3 3 Destination Pointer Address of Channel 0 bit 3
DSTP0.DSTP0_2 2 Destination Pointer Address of Channel 0 bit 2
DSTP0.DSTP0_1 1 Destination Pointer Address of Channel 0 bit 1
DSTP0.DSTP0_0 0 Destination Pointer Address of Channel 0 bit 0
SRCP1 0xEC44 PEC Channel 1 Source Pointer
SRCP1.SRCP1_15 15 Source Pointer Address of Channel 1 bit 15
SRCP1.SRCP1_14 14 Source Pointer Address of Channel 1 bit 14
SRCP1.SRCP1_13 13 Source Pointer Address of Channel 1 bit 13
SRCP1.SRCP1_12 12 Source Pointer Address of Channel 1 bit 12
SRCP1.SRCP1_11 11 Source Pointer Address of Channel 1 bit 11
SRCP1.SRCP1_10 10 Source Pointer Address of Channel 1 bit 10
SRCP1.SRCP1_9 9 Source Pointer Address of Channel 1 bit 9
SRCP1.SRCP1_8 8 Source Pointer Address of Channel 1 bit 8
SRCP1.SRCP1_7 7 Source Pointer Address of Channel 1 bit 7
SRCP1.SRCP1_6 6 Source Pointer Address of Channel 1 bit 6
SRCP1.SRCP1_5 5 Source Pointer Address of Channel 1 bit 5
SRCP1.SRCP1_4 4 Source Pointer Address of Channel 1 bit 4
SRCP1.SRCP1_3 3 Source Pointer Address of Channel 1 bit 3
SRCP1.SRCP1_2 2 Source Pointer Address of Channel 1 bit 2
SRCP1.SRCP1_1 1 Source Pointer Address of Channel 1 bit 1
SRCP1.SRCP1_0 0 Source Pointer Address of Channel 1 bit 0
DSTP1 0xEC46 PEC Channel 1 Destination Pointer
DSTP1.DSTP1_15 15 Destination Pointer Address of Channel 1 bit 15
DSTP1.DSTP1_14 14 Destination Pointer Address of Channel 1 bit 14
DSTP1.DSTP1_13 13 Destination Pointer Address of Channel 1 bit 13
DSTP1.DSTP1_12 12 Destination Pointer Address of Channel 1 bit 12
DSTP1.DSTP1_11 11 Destination Pointer Address of Channel 1 bit 11
DSTP1.DSTP1_10 10 Destination Pointer Address of Channel 1 bit 10
DSTP1.DSTP1_9 9 Destination Pointer Address of Channel 1 bit 9
DSTP1.DSTP1_8 8 Destination Pointer Address of Channel 1 bit 8
DSTP1.DSTP1_7 7 Destination Pointer Address of Channel 1 bit 7
DSTP1.DSTP1_6 6 Destination Pointer Address of Channel 1 bit 6
DSTP1.DSTP1_5 5 Destination Pointer Address of Channel 1 bit 5
DSTP1.DSTP1_4 4 Destination Pointer Address of Channel 1 bit 4
DSTP1.DSTP1_3 3 Destination Pointer Address of Channel 1 bit 3
DSTP1.DSTP1_2 2 Destination Pointer Address of Channel 1 bit 2
DSTP1.DSTP1_1 1 Destination Pointer Address of Channel 1 bit 1
DSTP1.DSTP1_0 0 Destination Pointer Address of Channel 1 bit 0
SRCP2 0xEC48 PEC Channel 2 Source Pointer
SRCP2.SRCP2_15 15 Source Pointer Address of Channel 2 bit 15
SRCP2.SRCP2_14 14 Source Pointer Address of Channel 2 bit 14
SRCP2.SRCP2_13 13 Source Pointer Address of Channel 2 bit 13
SRCP2.SRCP2_12 12 Source Pointer Address of Channel 2 bit 12
SRCP2.SRCP2_11 11 Source Pointer Address of Channel 2 bit 11
SRCP2.SRCP2_10 10 Source Pointer Address of Channel 2 bit 10
SRCP2.SRCP2_9 9 Source Pointer Address of Channel 2 bit 9
SRCP2.SRCP2_8 8 Source Pointer Address of Channel 2 bit 8
SRCP2.SRCP2_7 7 Source Pointer Address of Channel 2 bit 7
SRCP2.SRCP2_6 6 Source Pointer Address of Channel 2 bit 6
SRCP2.SRCP2_5 5 Source Pointer Address of Channel 2 bit 5
SRCP2.SRCP2_4 4 Source Pointer Address of Channel 2 bit 4
SRCP2.SRCP2_3 3 Source Pointer Address of Channel 2 bit 3
SRCP2.SRCP2_2 2 Source Pointer Address of Channel 2 bit 2
SRCP2.SRCP2_1 1 Source Pointer Address of Channel 2 bit 1
SRCP2.SRCP2_0 0 Source Pointer Address of Channel 2 bit 0
DSTP2 0xEC4A PEC Channel 2 Destination Pointer
DSTP2.DSTP2_15 15 Destination Pointer Address of Channel 2 bit 15
DSTP2.DSTP2_14 14 Destination Pointer Address of Channel 2 bit 14
DSTP2.DSTP2_13 13 Destination Pointer Address of Channel 2 bit 13
DSTP2.DSTP2_12 12 Destination Pointer Address of Channel 2 bit 12
DSTP2.DSTP2_11 11 Destination Pointer Address of Channel 2 bit 11
DSTP2.DSTP2_10 10 Destination Pointer Address of Channel 2 bit 10
DSTP2.DSTP2_9 9 Destination Pointer Address of Channel 2 bit 9
DSTP2.DSTP2_8 8 Destination Pointer Address of Channel 2 bit 8
DSTP2.DSTP2_7 7 Destination Pointer Address of Channel 2 bit 7
DSTP2.DSTP2_6 6 Destination Pointer Address of Channel 2 bit 6
DSTP2.DSTP2_5 5 Destination Pointer Address of Channel 2 bit 5
DSTP2.DSTP2_4 4 Destination Pointer Address of Channel 2 bit 4
DSTP2.DSTP2_3 3 Destination Pointer Address of Channel 2 bit 3
DSTP2.DSTP2_2 2 Destination Pointer Address of Channel 2 bit 2
DSTP2.DSTP2_1 1 Destination Pointer Address of Channel 2 bit 1
DSTP2.DSTP2_0 0 Destination Pointer Address of Channel 2 bit 0
SRCP3 0xEC4C PEC Channel 3 Source Pointer
SRCP3.SRCP3_15 15 Source Pointer Address of Channel 3 bit 15
SRCP3.SRCP3_14 14 Source Pointer Address of Channel 3 bit 14
SRCP3.SRCP3_13 13 Source Pointer Address of Channel 3 bit 13
SRCP3.SRCP3_12 12 Source Pointer Address of Channel 3 bit 12
SRCP3.SRCP3_11 11 Source Pointer Address of Channel 3 bit 11
SRCP3.SRCP3_10 10 Source Pointer Address of Channel 3 bit 10
SRCP3.SRCP3_9 9 Source Pointer Address of Channel 3 bit 9
SRCP3.SRCP3_8 8 Source Pointer Address of Channel 3 bit 8
SRCP3.SRCP3_7 7 Source Pointer Address of Channel 3 bit 7
SRCP3.SRCP3_6 6 Source Pointer Address of Channel 3 bit 6
SRCP3.SRCP3_5 5 Source Pointer Address of Channel 3 bit 5
SRCP3.SRCP3_4 4 Source Pointer Address of Channel 3 bit 4
SRCP3.SRCP3_3 3 Source Pointer Address of Channel 3 bit 3
SRCP3.SRCP3_2 2 Source Pointer Address of Channel 3 bit 2
SRCP3.SRCP3_1 1 Source Pointer Address of Channel 3 bit 1
SRCP3.SRCP3_0 0 Source Pointer Address of Channel 3 bit 0
DSTP3 0xEC4E PEC Channel 3 Destination Pointer
DSTP3.DSTP3_15 15 Destination Pointer Address of Channel 3 bit 15
DSTP3.DSTP3_14 14 Destination Pointer Address of Channel 3 bit 14
DSTP3.DSTP3_13 13 Destination Pointer Address of Channel 3 bit 13
DSTP3.DSTP3_12 12 Destination Pointer Address of Channel 3 bit 12
DSTP3.DSTP3_11 11 Destination Pointer Address of Channel 3 bit 11
DSTP3.DSTP3_10 10 Destination Pointer Address of Channel 3 bit 10
DSTP3.DSTP3_9 9 Destination Pointer Address of Channel 3 bit 9
DSTP3.DSTP3_8 8 Destination Pointer Address of Channel 3 bit 8
DSTP3.DSTP3_7 7 Destination Pointer Address of Channel 3 bit 7
DSTP3.DSTP3_6 6 Destination Pointer Address of Channel 3 bit 6
DSTP3.DSTP3_5 5 Destination Pointer Address of Channel 3 bit 5
DSTP3.DSTP3_4 4 Destination Pointer Address of Channel 3 bit 4
DSTP3.DSTP3_3 3 Destination Pointer Address of Channel 3 bit 3
DSTP3.DSTP3_2 2 Destination Pointer Address of Channel 3 bit 2
DSTP3.DSTP3_1 1 Destination Pointer Address of Channel 3 bit 1
DSTP3.DSTP3_0 0 Destination Pointer Address of Channel 3 bit 0
SRCP4 0xEC50 PEC Channel 4 Source Pointer
SRCP4.SRCP4_15 15 Source Pointer Address of Channel 4 bit 15
SRCP4.SRCP4_14 14 Source Pointer Address of Channel 4 bit 14
SRCP4.SRCP4_13 13 Source Pointer Address of Channel 4 bit 13
SRCP4.SRCP4_12 12 Source Pointer Address of Channel 4 bit 12
SRCP4.SRCP4_11 11 Source Pointer Address of Channel 4 bit 11
SRCP4.SRCP4_10 10 Source Pointer Address of Channel 4 bit 10
SRCP4.SRCP4_9 9 Source Pointer Address of Channel 4 bit 9
SRCP4.SRCP4_8 8 Source Pointer Address of Channel 4 bit 8
SRCP4.SRCP4_7 7 Source Pointer Address of Channel 4 bit 7
SRCP4.SRCP4_6 6 Source Pointer Address of Channel 4 bit 6
SRCP4.SRCP4_5 5 Source Pointer Address of Channel 4 bit 5
SRCP4.SRCP4_4 4 Source Pointer Address of Channel 4 bit 4
SRCP4.SRCP4_3 3 Source Pointer Address of Channel 4 bit 3
SRCP4.SRCP4_2 2 Source Pointer Address of Channel 4 bit 2
SRCP4.SRCP4_1 1 Source Pointer Address of Channel 4 bit 1
SRCP4.SRCP4_0 0 Source Pointer Address of Channel 4 bit 0
DSTP4 0xEC52 PEC Channel 4 Destination Pointer
DSTP4.DSTP4_15 15 Destination Pointer Address of Channel 4 bit 15
DSTP4.DSTP4_14 14 Destination Pointer Address of Channel 4 bit 14
DSTP4.DSTP4_13 13 Destination Pointer Address of Channel 4 bit 13
DSTP4.DSTP4_12 12 Destination Pointer Address of Channel 4 bit 12
DSTP4.DSTP4_11 11 Destination Pointer Address of Channel 4 bit 11
DSTP4.DSTP4_10 10 Destination Pointer Address of Channel 4 bit 10
DSTP4.DSTP4_9 9 Destination Pointer Address of Channel 4 bit 9
DSTP4.DSTP4_8 8 Destination Pointer Address of Channel 4 bit 8
DSTP4.DSTP4_7 7 Destination Pointer Address of Channel 4 bit 7
DSTP4.DSTP4_6 6 Destination Pointer Address of Channel 4 bit 6
DSTP4.DSTP4_5 5 Destination Pointer Address of Channel 4 bit 5
DSTP4.DSTP4_4 4 Destination Pointer Address of Channel 4 bit 4
DSTP4.DSTP4_3 3 Destination Pointer Address of Channel 4 bit 3
DSTP4.DSTP4_2 2 Destination Pointer Address of Channel 4 bit 2
DSTP4.DSTP4_1 1 Destination Pointer Address of Channel 4 bit 1
DSTP4.DSTP4_0 0 Destination Pointer Address of Channel 4 bit 0
SRCP5 0xEC54 PEC Channel 5 Source Pointer
SRCP5.SRCP5_15 15 Source Pointer Address of Channel 5 bit 15
SRCP5.SRCP5_14 14 Source Pointer Address of Channel 5 bit 14
SRCP5.SRCP5_13 13 Source Pointer Address of Channel 5 bit 13
SRCP5.SRCP5_12 12 Source Pointer Address of Channel 5 bit 12
SRCP5.SRCP5_11 11 Source Pointer Address of Channel 5 bit 11
SRCP5.SRCP5_10 10 Source Pointer Address of Channel 5 bit 10
SRCP5.SRCP5_9 9 Source Pointer Address of Channel 5 bit 9
SRCP5.SRCP5_8 8 Source Pointer Address of Channel 5 bit 8
SRCP5.SRCP5_7 7 Source Pointer Address of Channel 5 bit 7
SRCP5.SRCP5_6 6 Source Pointer Address of Channel 5 bit 6
SRCP5.SRCP5_5 5 Source Pointer Address of Channel 5 bit 5
SRCP5.SRCP5_4 4 Source Pointer Address of Channel 5 bit 4
SRCP5.SRCP5_3 3 Source Pointer Address of Channel 5 bit 3
SRCP5.SRCP5_2 2 Source Pointer Address of Channel 5 bit 2
SRCP5.SRCP5_1 1 Source Pointer Address of Channel 5 bit 1
SRCP5.SRCP5_0 0 Source Pointer Address of Channel 5 bit 0
DSTP5 0xEC56 PEC Channel 5 Destination Pointer
DSTP5.DSTP5_15 15 Destination Pointer Address of Channel 5 bit 15
DSTP5.DSTP5_14 14 Destination Pointer Address of Channel 5 bit 14
DSTP5.DSTP5_13 13 Destination Pointer Address of Channel 5 bit 13
DSTP5.DSTP5_12 12 Destination Pointer Address of Channel 5 bit 12
DSTP5.DSTP5_11 11 Destination Pointer Address of Channel 5 bit 11
DSTP5.DSTP5_10 10 Destination Pointer Address of Channel 5 bit 10
DSTP5.DSTP5_9 9 Destination Pointer Address of Channel 5 bit 9
DSTP5.DSTP5_8 8 Destination Pointer Address of Channel 5 bit 8
DSTP5.DSTP5_7 7 Destination Pointer Address of Channel 5 bit 7
DSTP5.DSTP5_6 6 Destination Pointer Address of Channel 5 bit 6
DSTP5.DSTP5_5 5 Destination Pointer Address of Channel 5 bit 5
DSTP5.DSTP5_4 4 Destination Pointer Address of Channel 5 bit 4
DSTP5.DSTP5_3 3 Destination Pointer Address of Channel 5 bit 3
DSTP5.DSTP5_2 2 Destination Pointer Address of Channel 5 bit 2
DSTP5.DSTP5_1 1 Destination Pointer Address of Channel 5 bit 1
DSTP5.DSTP5_0 0 Destination Pointer Address of Channel 5 bit 0
SRCP6 0xEC58 PEC Channel 6 Source Pointer
SRCP6.SRCP6_15 15 Source Pointer Address of Channel 6 bit 15
SRCP6.SRCP6_14 14 Source Pointer Address of Channel 6 bit 14
SRCP6.SRCP6_13 13 Source Pointer Address of Channel 6 bit 13
SRCP6.SRCP6_12 12 Source Pointer Address of Channel 6 bit 12
SRCP6.SRCP6_11 11 Source Pointer Address of Channel 6 bit 11
SRCP6.SRCP6_10 10 Source Pointer Address of Channel 6 bit 10
SRCP6.SRCP6_9 9 Source Pointer Address of Channel 6 bit 9
SRCP6.SRCP6_8 8 Source Pointer Address of Channel 6 bit 8
SRCP6.SRCP6_7 7 Source Pointer Address of Channel 6 bit 7
SRCP6.SRCP6_6 6 Source Pointer Address of Channel 6 bit 6
SRCP6.SRCP6_5 5 Source Pointer Address of Channel 6 bit 5
SRCP6.SRCP6_4 4 Source Pointer Address of Channel 6 bit 4
SRCP6.SRCP6_3 3 Source Pointer Address of Channel 6 bit 3
SRCP6.SRCP6_2 2 Source Pointer Address of Channel 6 bit 2
SRCP6.SRCP6_1 1 Source Pointer Address of Channel 6 bit 1
SRCP6.SRCP6_0 0 Source Pointer Address of Channel 6 bit 0
DSTP6 0xEC5A PEC Channel 6 Destination Pointer
DSTP6.DSTP6_15 15 Destination Pointer Address of Channel 6 bit 15
DSTP6.DSTP6_14 14 Destination Pointer Address of Channel 6 bit 14
DSTP6.DSTP6_13 13 Destination Pointer Address of Channel 6 bit 13
DSTP6.DSTP6_12 12 Destination Pointer Address of Channel 6 bit 12
DSTP6.DSTP6_11 11 Destination Pointer Address of Channel 6 bit 11
DSTP6.DSTP6_10 10 Destination Pointer Address of Channel 6 bit 10
DSTP6.DSTP6_9 9 Destination Pointer Address of Channel 6 bit 9
DSTP6.DSTP6_8 8 Destination Pointer Address of Channel 6 bit 8
DSTP6.DSTP6_7 7 Destination Pointer Address of Channel 6 bit 7
DSTP6.DSTP6_6 6 Destination Pointer Address of Channel 6 bit 6
DSTP6.DSTP6_5 5 Destination Pointer Address of Channel 6 bit 5
DSTP6.DSTP6_4 4 Destination Pointer Address of Channel 6 bit 4
DSTP6.DSTP6_3 3 Destination Pointer Address of Channel 6 bit 3
DSTP6.DSTP6_2 2 Destination Pointer Address of Channel 6 bit 2
DSTP6.DSTP6_1 1 Destination Pointer Address of Channel 6 bit 1
DSTP6.DSTP6_0 0 Destination Pointer Address of Channel 6 bit 0
SRCP7 0xEC5C PEC Channel 7 Source Pointer
SRCP7.SRCP7_15 15 Source Pointer Address of Channel 7 bit 15
SRCP7.SRCP7_14 14 Source Pointer Address of Channel 7 bit 14
SRCP7.SRCP7_13 13 Source Pointer Address of Channel 7 bit 13
SRCP7.SRCP7_12 12 Source Pointer Address of Channel 7 bit 12
SRCP7.SRCP7_11 11 Source Pointer Address of Channel 7 bit 11
SRCP7.SRCP7_10 10 Source Pointer Address of Channel 7 bit 10
SRCP7.SRCP7_9 9 Source Pointer Address of Channel 7 bit 9
SRCP7.SRCP7_8 8 Source Pointer Address of Channel 7 bit 8
SRCP7.SRCP7_7 7 Source Pointer Address of Channel 7 bit 7
SRCP7.SRCP7_6 6 Source Pointer Address of Channel 7 bit 6
SRCP7.SRCP7_5 5 Source Pointer Address of Channel 7 bit 5
SRCP7.SRCP7_4 4 Source Pointer Address of Channel 7 bit 4
SRCP7.SRCP7_3 3 Source Pointer Address of Channel 7 bit 3
SRCP7.SRCP7_2 2 Source Pointer Address of Channel 7 bit 2
SRCP7.SRCP7_1 1 Source Pointer Address of Channel 7 bit 1
SRCP7.SRCP7_0 0 Source Pointer Address of Channel 7 bit 0
DSTP7 0xEC5E PEC Channel 7 Destination
DSTP7.DSTP7_15 15 Destination Pointer Address of Channel 7 bit 15
DSTP7.DSTP7_14 14 Destination Pointer Address of Channel 7 bit 14
DSTP7.DSTP7_13 13 Destination Pointer Address of Channel 7 bit 13
DSTP7.DSTP7_12 12 Destination Pointer Address of Channel 7 bit 12
DSTP7.DSTP7_11 11 Destination Pointer Address of Channel 7 bit 11
DSTP7.DSTP7_10 10 Destination Pointer Address of Channel 7 bit 10
DSTP7.DSTP7_9 9 Destination Pointer Address of Channel 7 bit 9
DSTP7.DSTP7_8 8 Destination Pointer Address of Channel 7 bit 8
DSTP7.DSTP7_7 7 Destination Pointer Address of Channel 7 bit 7
DSTP7.DSTP7_6 6 Destination Pointer Address of Channel 7 bit 6
DSTP7.DSTP7_5 5 Destination Pointer Address of Channel 7 bit 5
DSTP7.DSTP7_4 4 Destination Pointer Address of Channel 7 bit 4
DSTP7.DSTP7_3 3 Destination Pointer Address of Channel 7 bit 3
DSTP7.DSTP7_2 2 Destination Pointer Address of Channel 7 bit 2
DSTP7.DSTP7_1 1 Destination Pointer Address of Channel 7 bit 1
DSTP7.DSTP7_0 0 Destination Pointer Address of Channel 7 bit 0
PECSEG0 0xEC80 PEC Pointer 0 Segment Address Register
PECSEG0.SRCSEG0_15 15 Source Pointer Segment Address of Channel 0 bit 15
PECSEG0.SRCSEG0_14 14 Source Pointer Segment Address of Channel 0 bit 14
PECSEG0.SRCSEG0_13 13 Source Pointer Segment Address of Channel 0 bit 13
PECSEG0.SRCSEG0_12 12 Source Pointer Segment Address of Channel 0 bit 12
PECSEG0.SRCSEG0_11 11 Source Pointer Segment Address of Channel 0 bit 11
PECSEG0.SRCSEG0_10 10 Source Pointer Segment Address of Channel 0 bit 10
PECSEG0.SRCSEG0_9 9 Source Pointer Segment Address of Channel 0 bit 9
PECSEG0.SRCSEG0_8 8 Source Pointer Segment Address of Channel 0 bit 8
PECSEG0.DSTSEG0_7 7 Destination Pointer Segment Address of Channel 0 bit 7
PECSEG0.DSTSEG0_6 6 Destination Pointer Segment Address of Channel 0 bit 6
PECSEG0.DSTSEG0_5 5 Destination Pointer Segment Address of Channel 0 bit 5
PECSEG0.DSTSEG0_4 4 Destination Pointer Segment Address of Channel 0 bit 4
PECSEG0.DSTSEG0_3 3 Destination Pointer Segment Address of Channel 0 bit 3
PECSEG0.DSTSEG0_2 2 Destination Pointer Segment Address of Channel 0 bit 2
PECSEG0.DSTSEG0_1 1 Destination Pointer Segment Address of Channel 0 bit 1
PECSEG0.DSTSEG0_0 0 Destination Pointer Segment Address of Channel 0 bit 0
PECSEG1 0xEC82 PEC Pointer 1 Segment Address Register
PECSEG1.SRCSEG1_15 15 Source Pointer Segment Address of Channel 1 bit 15
PECSEG1.SRCSEG1_14 14 Source Pointer Segment Address of Channel 1 bit 14
PECSEG1.SRCSEG1_13 13 Source Pointer Segment Address of Channel 1 bit 13
PECSEG1.SRCSEG1_12 12 Source Pointer Segment Address of Channel 1 bit 12
PECSEG1.SRCSEG1_11 11 Source Pointer Segment Address of Channel 1 bit 11
PECSEG1.SRCSEG1_10 10 Source Pointer Segment Address of Channel 1 bit 10
PECSEG1.SRCSEG1_9 9 Source Pointer Segment Address of Channel 1 bit 9
PECSEG1.SRCSEG1_8 8 Source Pointer Segment Address of Channel 1 bit 8
PECSEG1.DSTSEG1_7 7 Destination Pointer Segment Address of Channel 1 bit 7
PECSEG1.DSTSEG1_6 6 Destination Pointer Segment Address of Channel 1 bit 6
PECSEG1.DSTSEG1_5 5 Destination Pointer Segment Address of Channel 1 bit 5
PECSEG1.DSTSEG1_4 4 Destination Pointer Segment Address of Channel 1 bit 4
PECSEG1.DSTSEG1_3 3 Destination Pointer Segment Address of Channel 1 bit 3
PECSEG1.DSTSEG1_2 2 Destination Pointer Segment Address of Channel 1 bit 2
PECSEG1.DSTSEG1_1 1 Destination Pointer Segment Address of Channel 1 bit 1
PECSEG1.DSTSEG1_0 0 Destination Pointer Segment Address of Channel 1 bit 0
PECSEG2 0xEC84 PEC Pointer 2 Segment Address Register
PECSEG2.SRCSEG2_15 15 Source Pointer Segment Address of Channel 2 bit 15
PECSEG2.SRCSEG2_14 14 Source Pointer Segment Address of Channel 2 bit 14
PECSEG2.SRCSEG2_13 13 Source Pointer Segment Address of Channel 2 bit 13
PECSEG2.SRCSEG2_12 12 Source Pointer Segment Address of Channel 2 bit 12
PECSEG2.SRCSEG2_11 11 Source Pointer Segment Address of Channel 2 bit 11
PECSEG2.SRCSEG2_10 10 Source Pointer Segment Address of Channel 2 bit 10
PECSEG2.SRCSEG2_9 9 Source Pointer Segment Address of Channel 2 bit 9
PECSEG2.SRCSEG2_8 8 Source Pointer Segment Address of Channel 2 bit 8
PECSEG2.DSTSEG2_7 7 Destination Pointer Segment Address of Channel 2 bit 7
PECSEG2.DSTSEG2_6 6 Destination Pointer Segment Address of Channel 2 bit 6
PECSEG2.DSTSEG2_5 5 Destination Pointer Segment Address of Channel 2 bit 5
PECSEG2.DSTSEG2_4 4 Destination Pointer Segment Address of Channel 2 bit 4
PECSEG2.DSTSEG2_3 3 Destination Pointer Segment Address of Channel 2 bit 3
PECSEG2.DSTSEG2_2 2 Destination Pointer Segment Address of Channel 2 bit 2
PECSEG2.DSTSEG2_1 1 Destination Pointer Segment Address of Channel 2 bit 1
PECSEG2.DSTSEG2_0 0 Destination Pointer Segment Address of Channel 2 bit 0
PECSEG3 0xEC86 PEC Pointer 3 Segment Address Register
PECSEG3.SRCSEG3_15 15 Source Pointer Segment Address of Channel 3 bit 15
PECSEG3.SRCSEG3_14 14 Source Pointer Segment Address of Channel 3 bit 14
PECSEG3.SRCSEG3_13 13 Source Pointer Segment Address of Channel 3 bit 13
PECSEG3.SRCSEG3_12 12 Source Pointer Segment Address of Channel 3 bit 12
PECSEG3.SRCSEG3_11 11 Source Pointer Segment Address of Channel 3 bit 11
PECSEG3.SRCSEG3_10 10 Source Pointer Segment Address of Channel 3 bit 10
PECSEG3.SRCSEG3_9 9 Source Pointer Segment Address of Channel 3 bit 9
PECSEG3.SRCSEG3_8 8 Source Pointer Segment Address of Channel 3 bit 8
PECSEG3.DSTSEG3_7 7 Destination Pointer Segment Address of Channel 3 bit 7
PECSEG3.DSTSEG3_6 6 Destination Pointer Segment Address of Channel 3 bit 6
PECSEG3.DSTSEG3_5 5 Destination Pointer Segment Address of Channel 3 bit 5
PECSEG3.DSTSEG3_4 4 Destination Pointer Segment Address of Channel 3 bit 4
PECSEG3.DSTSEG3_3 3 Destination Pointer Segment Address of Channel 3 bit 3
PECSEG3.DSTSEG3_2 2 Destination Pointer Segment Address of Channel 3 bit 2
PECSEG3.DSTSEG3_1 1 Destination Pointer Segment Address of Channel 3 bit 1
PECSEG3.DSTSEG3_0 0 Destination Pointer Segment Address of Channel 3 bit 0
PECSEG4 0xEC88 PEC Pointer 4 Segment Address Register
PECSEG4.SRCSEG4_15 15 Source Pointer Segment Address of Channel 4 bit 15
PECSEG4.SRCSEG4_14 14 Source Pointer Segment Address of Channel 4 bit 14
PECSEG4.SRCSEG4_13 13 Source Pointer Segment Address of Channel 4 bit 13
PECSEG4.SRCSEG4_12 12 Source Pointer Segment Address of Channel 4 bit 12
PECSEG4.SRCSEG4_11 11 Source Pointer Segment Address of Channel 4 bit 11
PECSEG4.SRCSEG4_10 10 Source Pointer Segment Address of Channel 4 bit 10
PECSEG4.SRCSEG4_9 9 Source Pointer Segment Address of Channel 4 bit 9
PECSEG4.SRCSEG4_8 8 Source Pointer Segment Address of Channel 4 bit 8
PECSEG4.DSTSEG4_7 7 Destination Pointer Segment Address of Channel 4 bit 7
PECSEG4.DSTSEG4_6 6 Destination Pointer Segment Address of Channel 4 bit 6
PECSEG4.DSTSEG4_5 5 Destination Pointer Segment Address of Channel 4 bit 5
PECSEG4.DSTSEG4_4 4 Destination Pointer Segment Address of Channel 4 bit 4
PECSEG4.DSTSEG4_3 3 Destination Pointer Segment Address of Channel 4 bit 3
PECSEG4.DSTSEG4_2 2 Destination Pointer Segment Address of Channel 4 bit 2
PECSEG4.DSTSEG4_1 1 Destination Pointer Segment Address of Channel 4 bit 1
PECSEG4.DSTSEG4_0 0 Destination Pointer Segment Address of Channel 4 bit 0
PECSEG5 0xEC8A PEC Pointer 5 Segment Address Register
PECSEG5.SRCSEG5_15 15 Source Pointer Segment Address of Channel 5 bit 15
PECSEG5.SRCSEG5_14 14 Source Pointer Segment Address of Channel 5 bit 14
PECSEG5.SRCSEG5_13 13 Source Pointer Segment Address of Channel 5 bit 13
PECSEG5.SRCSEG5_12 12 Source Pointer Segment Address of Channel 5 bit 12
PECSEG5.SRCSEG5_11 11 Source Pointer Segment Address of Channel 5 bit 11
PECSEG5.SRCSEG5_10 10 Source Pointer Segment Address of Channel 5 bit 10
PECSEG5.SRCSEG5_9 9 Source Pointer Segment Address of Channel 5 bit 9
PECSEG5.SRCSEG5_8 8 Source Pointer Segment Address of Channel 5 bit 8
PECSEG5.DSTSEG5_7 7 Destination Pointer Segment Address of Channel 5 bit 7
PECSEG5.DSTSEG5_6 6 Destination Pointer Segment Address of Channel 5 bit 6
PECSEG5.DSTSEG5_5 5 Destination Pointer Segment Address of Channel 5 bit 5
PECSEG5.DSTSEG5_4 4 Destination Pointer Segment Address of Channel 5 bit 4
PECSEG5.DSTSEG5_3 3 Destination Pointer Segment Address of Channel 5 bit 3
PECSEG5.DSTSEG5_2 2 Destination Pointer Segment Address of Channel 5 bit 2
PECSEG5.DSTSEG5_1 1 Destination Pointer Segment Address of Channel 5 bit 1
PECSEG5.DSTSEG5_0 0 Destination Pointer Segment Address of Channel 5 bit 0
PECSEG6 0xEC8C PEC Pointer 6 Segment Address Register
PECSEG6.SRCSEG6_15 15 Source Pointer Segment Address of Channel 6 bit 15
PECSEG6.SRCSEG6_14 14 Source Pointer Segment Address of Channel 6 bit 14
PECSEG6.SRCSEG6_13 13 Source Pointer Segment Address of Channel 6 bit 13
PECSEG6.SRCSEG6_12 12 Source Pointer Segment Address of Channel 6 bit 12
PECSEG6.SRCSEG6_11 11 Source Pointer Segment Address of Channel 6 bit 11
PECSEG6.SRCSEG6_10 10 Source Pointer Segment Address of Channel 6 bit 10
PECSEG6.SRCSEG6_9 9 Source Pointer Segment Address of Channel 6 bit 9
PECSEG6.SRCSEG6_8 8 Source Pointer Segment Address of Channel 6 bit 8
PECSEG6.DSTSEG6_7 7 Destination Pointer Segment Address of Channel 6 bit 7
PECSEG6.DSTSEG6_6 6 Destination Pointer Segment Address of Channel 6 bit 6
PECSEG6.DSTSEG6_5 5 Destination Pointer Segment Address of Channel 6 bit 5
PECSEG6.DSTSEG6_4 4 Destination Pointer Segment Address of Channel 6 bit 4
PECSEG6.DSTSEG6_3 3 Destination Pointer Segment Address of Channel 6 bit 3
PECSEG6.DSTSEG6_2 2 Destination Pointer Segment Address of Channel 6 bit 2
PECSEG6.DSTSEG6_1 1 Destination Pointer Segment Address of Channel 6 bit 1
PECSEG6.DSTSEG6_0 0 Destination Pointer Segment Address of Channel 6 bit 0
PECSEG7 0xEC8E PEC Pointer 7 Segment Address Register
PECSEG7.SRCSEG7_15 15 Source Pointer Segment Address of Channel 7 bit 15
PECSEG7.SRCSEG7_14 14 Source Pointer Segment Address of Channel 7 bit 14
PECSEG7.SRCSEG7_13 13 Source Pointer Segment Address of Channel 7 bit 13
PECSEG7.SRCSEG7_12 12 Source Pointer Segment Address of Channel 7 bit 12
PECSEG7.SRCSEG7_11 11 Source Pointer Segment Address of Channel 7 bit 11
PECSEG7.SRCSEG7_10 10 Source Pointer Segment Address of Channel 7 bit 10
PECSEG7.SRCSEG7_9 9 Source Pointer Segment Address of Channel 7 bit 9
PECSEG7.SRCSEG7_8 8 Source Pointer Segment Address of Channel 7 bit 8
PECSEG7.DSTSEG7_7 7 Destination Pointer Segment Address of Channel 7 bit 7
PECSEG7.DSTSEG7_6 6 Destination Pointer Segment Address of Channel 7 bit 6
PECSEG7.DSTSEG7_5 5 Destination Pointer Segment Address of Channel 7 bit 5
PECSEG7.DSTSEG7_4 4 Destination Pointer Segment Address of Channel 7 bit 4
PECSEG7.DSTSEG7_3 3 Destination Pointer Segment Address of Channel 7 bit 3
PECSEG7.DSTSEG7_2 2 Destination Pointer Segment Address of Channel 7 bit 2
PECSEG7.DSTSEG7_1 1 Destination Pointer Segment Address of Channel 7 bit 1
PECSEG7.DSTSEG7_0 0 Destination Pointer Segment Address of Channel 7 bit 0
EBCMOD0 0xEE00 EBC Mode Control Register 0
EBCMOD0.ALEDIS 13 ALE Pin Disable
EBCMOD0.BYTDIS 12 BHE Pin Disable
EBCMOD0.WRCFG 11 Configuration for Pins WR/WRL, BHE/WRH
EBCMOD0.EBCDIS 10 EBC Pins Disable
EBCMOD0.CSPEN_7 7 CSx Pins Enable (only external CSx) bit 7
EBCMOD0.CSPEN_6 6 CSx Pins Enable (only external CSx) bit 6
EBCMOD0.CSPEN_5 5 CSx Pins Enable (only external CSx) bit 5
EBCMOD0.CSPEN_4 4 CSx Pins Enable (only external CSx) bit 4
EBCMOD0.SAPEN_3 3 Segment Address Pins Enable bit 3
EBCMOD0.SAPEN_2 2 Segment Address Pins Enable bit 2
EBCMOD0.SAPEN_1 1 Segment Address Pins Enable bit 1
EBCMOD0.SAPEN_0 0 Segment Address Pins Enable bit 0
EBCMOD1 0xEE02 EBC Mode Control Register 1
EBCMOD1.WRPDIS 7 WR/WRL Pin Disable
EBCMOD1.DHPDIS 6 Data High Port Pins Disable
EBCMOD1.ALPDIS 5 Address Low Pins Disable
EBCMOD1.A0PDIS 4 Address Bit 0 Pin Disable
EBCMOD1.APDIS_3 3 Address Port Pins Disable bit 3
EBCMOD1.APDIS_2 2 Address Port Pins Disable bit 2
EBCMOD1.APDIS_1 1 Address Port Pins Disable bit 1
EBCMOD1.APDIS_0 0 Address Port Pins Disable bit 0
TCONCSMM 0xEE0C Monitor Memory CS Timing Configuration Register
TCONCSSM 0xEE0E Startup Memory CS Timing Configuration Register
TCONCS0 0xEE10 CS0 Timing Configuration Register
TCONCS0.WRPHF_14 14 Write Phase F bit 14
TCONCS0.WRPHF_13 13 Write Phase F bit 13
TCONCS0.RDPHF_12 12 Read Phase F bit 12
TCONCS0.RDPHF_11 11 Read Phase F bit 11
TCONCS0.PHE_10 10 Phase E bit 10
TCONCS0.PHE_9 9 Phase E bit 9
TCONCS0.PHE_8 8 Phase E bit 8
TCONCS0.PHE_7 7 Phase E bit 7
TCONCS0.PHE_6 6 Phase E bit 6
TCONCS0.PHD 5 Phase D
TCONCS0.PHC_4 4 Phase C bit 4
TCONCS0.PHC_3 3 Phase C bit 3
TCONCS0.PHB 2 Phase B
TCONCS0.PHA_1 1 Phase A bit 1
TCONCS0.PHA_0 0 Phase A bit 0
FCONCS0 0xEE12 CS0 Function Configuration Register
FCONCS0.BTYP_5 5 Bus Type Selection bit 5
FCONCS0.BTYP_4 4 Bus Type Selection bit 4
FCONCS0.ENCS 0 Enable Chip Select
TCONCS1 0xEE18 CS1 Timing Configuration Register
TCONCS1.WRPHF_14 14 Write Phase F bit 14
TCONCS1.WRPHF_13 13 Write Phase F bit 13
TCONCS1.RDPHF_12 12 Read Phase F bit 12
TCONCS1.RDPHF_11 11 Read Phase F bit 11
TCONCS1.PHE_10 10 Phase E bit 10
TCONCS1.PHE_9 9 Phase E bit 9
TCONCS1.PHE_8 8 Phase E bit 8
TCONCS1.PHE_7 7 Phase E bit 7
TCONCS1.PHE_6 6 Phase E bit 6
TCONCS1.PHD 5 Phase D
TCONCS1.PHC_4 4 Phase C bit 4
TCONCS1.PHC_3 3 Phase C bit 3
TCONCS1.PHB 2 Phase B
TCONCS1.PHA_1 1 Phase A bit 1
TCONCS1.PHA_0 0 Phase A bit 0
FCONCS1 0xEE1A CS1 Function Configuration Register
FCONCS1.BTYP_5 5 Bus Type Selection bit 5
FCONCS1.BTYP_4 4 Bus Type Selection bit 4
FCONCS1.RDYMOD 2 Ready Mode
FCONCS1.RDYEN 1 Ready enable
FCONCS1.ENCS 0 Enable Chip Select
ADDRSEL1 0xEE1E CS1 Address Range and Size Selection Register
ADDRSEL1.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL1.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL1.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL1.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL1.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL1.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL1.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL1.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL1.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL1.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL1.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL1.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL1.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL1.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL1.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL1.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS2 0xEE20 CS2 Timing Configuration Register
TCONCS2.WRPHF_14 14 Write Phase F bit 14
TCONCS2.WRPHF_13 13 Write Phase F bit 13
TCONCS2.RDPHF_12 12 Read Phase F bit 12
TCONCS2.RDPHF_11 11 Read Phase F bit 11
TCONCS2.PHE_10 10 Phase E bit 10
TCONCS2.PHE_9 9 Phase E bit 9
TCONCS2.PHE_8 8 Phase E bit 8
TCONCS2.PHE_7 7 Phase E bit 7
TCONCS2.PHE_6 6 Phase E bit 6
TCONCS2.PHD 5 Phase D
TCONCS2.PHC_4 4 Phase C bit 4
TCONCS2.PHC_3 3 Phase C bit 3
TCONCS2.PHB 2 Phase B
TCONCS2.PHA_1 1 Phase A bit 1
TCONCS2.PHA_0 0 Phase A bit 0
FCONCS2 0xEE22 CS2 Function Configuration Register
FCONCS2.BTYP_5 5 Bus Type Selection bit 5
FCONCS2.BTYP_4 4 Bus Type Selection bit 4
FCONCS2.RDYMOD 2 Ready Mode
FCONCS2.RDYEN 1 Ready enable
FCONCS2.ENCS 0 Enable Chip Select
ADDRSEL2 0xEE26 CS2 Address Range and Size Selection Register
ADDRSEL2.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL2.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL2.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL2.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL2.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL2.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL2.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL2.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL2.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL2.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL2.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL2.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL2.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL2.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL2.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL2.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS3 0xEE28 CS3 Timing Configuration Register
TCONCS3.WRPHF_14 14 Write Phase F bit 14
TCONCS3.WRPHF_13 13 Write Phase F bit 13
TCONCS3.RDPHF_12 12 Read Phase F bit 12
TCONCS3.RDPHF_11 11 Read Phase F bit 11
TCONCS3.PHE_10 10 Phase E bit 10
TCONCS3.PHE_9 9 Phase E bit 9
TCONCS3.PHE_8 8 Phase E bit 8
TCONCS3.PHE_7 7 Phase E bit 7
TCONCS3.PHE_6 6 Phase E bit 6
TCONCS3.PHD 5 Phase D
TCONCS3.PHC_4 4 Phase C bit 4
TCONCS3.PHC_3 3 Phase C bit 3
TCONCS3.PHB 2 Phase B
TCONCS3.PHA_1 1 Phase A bit 1
TCONCS3.PHA_0 0 Phase A bit 0
FCONCS3 0xEE2A CS3 Function Configuration Register
FCONCS3.BTYP_5 5 Bus Type Selection bit 5
FCONCS3.BTYP_4 4 Bus Type Selection bit 4
FCONCS3.RDYMOD 2 Ready Mode
FCONCS3.RDYEN 1 Ready enable
FCONCS3.ENCS 0 Enable Chip Select
ADDRSEL3 0xEE2E CS3 Address Range and Size Selection Register
ADDRSEL3.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL3.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL3.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL3.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL3.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL3.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL3.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL3.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL3.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL3.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL3.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL3.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL3.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL3.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL3.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL3.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS7 0xEE48 CS7 Timing Configuration Register
TCONCS7.WRPHF_14 14 Write Phase F bit 14
TCONCS7.WRPHF_13 13 Write Phase F bit 13
TCONCS7.RDPHF_12 12 Read Phase F bit 12
TCONCS7.RDPHF_11 11 Read Phase F bit 11
TCONCS7.PHE_10 10 Phase E bit 10
TCONCS7.PHE_9 9 Phase E bit 9
TCONCS7.PHE_8 8 Phase E bit 8
TCONCS7.PHE_7 7 Phase E bit 7
TCONCS7.PHE_6 6 Phase E bit 6
TCONCS7.PHD 5 Phase D
TCONCS7.PHC_4 4 Phase C bit 4
TCONCS7.PHC_3 3 Phase C bit 3
TCONCS7.PHB 2 Phase B
TCONCS7.PHA_1 1 Phase A bit 1
TCONCS7.PHA_0 0 Phase A bit 0
FCONCS7 0xEE4A CS7 Function Configuration Register
FCONCS7.BTYP_5 5 Bus Type Selection bit 5
FCONCS7.BTYP_4 4 Bus Type Selection bit 4
FCONCS7.RDYMOD 2 Ready Mode
FCONCS7.RDYEN 1 Ready enable
FCONCS7.ENCS 0 Enable Chip Select
ADDRSEL7 0xEE4E CS7 Address Range and Size Selection Register
ADDRSEL7.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL7.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL7.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL7.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL7.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL7.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL7.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL7.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL7.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL7.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL7.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL7.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL7.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL7.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL7.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL7.RGSZ_0 0 Address Range Size Selection bit 0
QX0 0xF000 MAC Offset Register
QX0.QX_15 15 Modifiable portion of register QX0 bit 15
QX0.QX_14 14 Modifiable portion of register QX0 bit 14
QX0.QX_13 13 Modifiable portion of register QX0 bit 13
QX0.QX_12 12 Modifiable portion of register QX0 bit 12
QX0.QX_11 11 Modifiable portion of register QX0 bit 11
QX0.QX_10 10 Modifiable portion of register QX0 bit 10
QX0.QX_9 9 Modifiable portion of register QX0 bit 9
QX0.QX_8 8 Modifiable portion of register QX0 bit 8
QX0.QX_7 7 Modifiable portion of register QX0 bit 7
QX0.QX_6 6 Modifiable portion of register QX0 bit 6
QX0.QX_5 5 Modifiable portion of register QX0 bit 5
QX0.QX_4 4 Modifiable portion of register QX0 bit 4
QX0.QX_3 3 Modifiable portion of register QX0 bit 3
QX0.QX_2 2 Modifiable portion of register QX0 bit 2
QX0.QX_1 1 Modifiable portion of register QX0 bit 1
QX1 0xF002 MAC Offset Register
QX1.QX_15 15 Modifiable portion of register QX1 bit 15
QX1.QX_14 14 Modifiable portion of register QX1 bit 14
QX1.QX_13 13 Modifiable portion of register QX1 bit 13
QX1.QX_12 12 Modifiable portion of register QX1 bit 12
QX1.QX_11 11 Modifiable portion of register QX1 bit 11
QX1.QX_10 10 Modifiable portion of register QX1 bit 10
QX1.QX_9 9 Modifiable portion of register QX1 bit 9
QX1.QX_8 8 Modifiable portion of register QX1 bit 8
QX1.QX_7 7 Modifiable portion of register QX1 bit 7
QX1.QX_6 6 Modifiable portion of register QX1 bit 6
QX1.QX_5 5 Modifiable portion of register QX1 bit 5
QX1.QX_4 4 Modifiable portion of register QX1 bit 4
QX1.QX_3 3 Modifiable portion of register QX1 bit 3
QX1.QX_2 2 Modifiable portion of register QX1 bit 2
QX1.QX_1 1 Modifiable portion of register QX1 bit 1
QR0 0xF004 MAC Offset Register
QR0.QR_15 15 Modifiable portion of register QR0 bit 15
QR0.QR_14 14 Modifiable portion of register QR0 bit 14
QR0.QR_13 13 Modifiable portion of register QR0 bit 13
QR0.QR_12 12 Modifiable portion of register QR0 bit 12
QR0.QR_11 11 Modifiable portion of register QR0 bit 11
QR0.QR_10 10 Modifiable portion of register QR0 bit 10
QR0.QR_9 9 Modifiable portion of register QR0 bit 9
QR0.QR_8 8 Modifiable portion of register QR0 bit 8
QR0.QR_7 7 Modifiable portion of register QR0 bit 7
QR0.QR_6 6 Modifiable portion of register QR0 bit 6
QR0.QR_5 5 Modifiable portion of register QR0 bit 5
QR0.QR_4 4 Modifiable portion of register QR0 bit 4
QR0.QR_3 3 Modifiable portion of register QR0 bit 3
QR0.QR_2 2 Modifiable portion of register QR0 bit 2
QR0.QR_1 1 Modifiable portion of register QR0 bit 1
QR1 0xF006 MAC Offset Register
QR1.QR_15 15 Modifiable portion of register QR1 bit 15
QR1.QR_14 14 Modifiable portion of register QR1 bit 14
QR1.QR_13 13 Modifiable portion of register QR1 bit 13
QR1.QR_12 12 Modifiable portion of register QR1 bit 12
QR1.QR_11 11 Modifiable portion of register QR1 bit 11
QR1.QR_10 10 Modifiable portion of register QR1 bit 10
QR1.QR_9 9 Modifiable portion of register QR1 bit 9
QR1.QR_8 8 Modifiable portion of register QR1 bit 8
QR1.QR_7 7 Modifiable portion of register QR1 bit 7
QR1.QR_6 6 Modifiable portion of register QR1 bit 6
QR1.QR_5 5 Modifiable portion of register QR1 bit 5
QR1.QR_4 4 Modifiable portion of register QR1 bit 4
QR1.QR_3 3 Modifiable portion of register QR1 bit 3
QR1.QR_2 2 Modifiable portion of register QR1 bit 2
QR1.QR_1 1 Modifiable portion of register QR1 bit 1
CPUID 0xF00C CPU Identification Register
CC2_T7 0xF050 CAPCOM 2 Timer 7 Register
CC2_T8 0xF052 CAPCOM 2 Timer 8 Register
CC2_T7REL 0xF054 CAPCOM 2 Timer 7 Reload Register
CC2_T8REL 0xF056 CAPCOM 2 Timer 8 Reload Register
SSC1_TB 0xF05A SSC Transmit Buffer (WO)
SSC1_RB 0xF05C SSC Receive Buffer (RO)
SSC1_BR 0xF05E SSC Baudrate Register
CC1_PISEL 0xF060 Port Input Select Register
CC1_IOC 0xF062 CAPCOM1 IO Control
CC2_PISEL 0xF064 Port Input Select Register
CC2_IOC 0xF066 CAPCOM2 IO Control
COMDATA 0xF068 Communication Mode data register (Cerberus)
COMDATA.MTR_ADDR_15 15 Set bit 15 of selected
COMDATA.MTR_ADDR_14 14 Set bit 14 of selected
COMDATA.MTR_ADDR_13 13 Set bit 13 of selected
COMDATA.MTR_ADDR_12 12 Set bit 12 of selected
COMDATA.MTR_ADDR_11 11 Set bit 11 of selected
COMDATA.MTR_ADDR_10 10 Set bit 10 of selected
COMDATA.MTR_ADDR_9 9 Set bit 9 of selected
COMDATA.MTR_ADDR_8 8 Set bit 8 of selected
COMDATA.MTR_ADDR_7 7 Set bit 7 of selected
COMDATA.MTR_ADDR_6 6 Set bit 6 of selected
COMDATA.MTR_ADDR_5 5 Set bit 5 of selected
COMDATA.MTR_ADDR_4 4 Set bit 4 of selected
COMDATA.MTR_ADDR_3 3 Set bit 3 of selected
COMDATA.MTR_ADDR_2 2 Set bit 2 of selected
COMDATA.MTR_ADDR_1 1 Set bit 1 of selected
COMDATA.MTR_ADDR_0 0 Set bit 0 of selected
RWDATA 0xF06A RW mode data reg. (Cerberus)
RWDATA.MTR_SELECT_ADDR_9 9
RWDATA.MTR_SELECT_ADDR_8 8
RWDATA.MTR_ADDR_X_7 7 Set bit of selected 7
RWDATA.MTR_ADDR_X_6 6 Set bit of selected 6
RWDATA.MTR_ADDR_X_5 5 Set bit of selected 5
RWDATA.MTR_ADDR_X_4 4 Set bit of selected 4
RWDATA.MTR_ADDR_X_3 3 Set bit of selected 3
RWDATA.MTR_ADDR_X_2 2 Set bit of selected 2
RWDATA.MTR_ADDR_X_1 1 Set bit of selected 1
RWDATA.MTR_ADDR_X_0 0 Set bit of selected 0
IOSR 0xF06C Cerberus Status and Control Register
IOSR.MTR_CTL_P 15 Bit protection (MTR_CTL unchanged/can be changed)
IOSR.MTR_CTL 14 Monitor controlled tracing disabled/enabled
IOSR.CLNT_ON 9 Client not selected/selected
IOSR.DBG_ON 8 No external debugger present / External debugger present
IOSR.COM_SYNC 7 High level sync bit for Communication Mode
IOSR.CW_ACK 6 Write request acknowledge in Communication Mode
IOSR.CWSYNC 5 Write sync bit for Communication Mode
IOSR.CRSYNC 4 Read sync bit for Communication Mode
IOSR.RW_EN_P 3 Bit protection (RW_ENABLE unchanged / RW_ENABLE can be changed)
IOSR.RW_ENABLED 2 Used by user program for security
IOSR.RW_DIS_P 1 Bit protection (RW_DISABLE unchanged / RW_DISABLE can be changed)
IOSR.RW_DISABLE 0 RW mode protection
IDRT 0xF070 Identifier Silicon Correction
IDMEM2 0xF076 IDMEM2 Identifier
IDPROG 0xF078 IDPROG Identifier
IDMEM 0xF07A IDMEM Identifier
IDCHIP 0xF07C IDCHIP Identifier
IDMANUF 0xF07E IDMANUF Identifier
POCON0L 0xF080 Port 0L Output Control Register
POCON0H 0xF082 Port 0H Output Control Register
POCON1L 0xF084 Port 1L Output Control Register
POCON1H 0xF086 Port 1H Output Control Register
POCON3 0xF08A Port 3 Output Control Register
POCON4 0xF08C Port 4 Output Control Register
POCON6 0xF08E Port P6 Output Control Port
POCON7 0xF090 Port P7 Output Control Port
POCON9 0xF094 Port 9 Output Control Register
ADC_CTR2 0xF09C A/D Converter Control Register 2
ADC_CTR2IN 0xF09E A/D Converter Injection Control Register 2
ADC_DAT2 0xF0A0 A/D Converter Result Register 2
ASC1_TxFCON 0xF0A4 Transmit FIFO Control Register
ASC1_RxFCON 0xF0A6 Receive FIFO Control Register
POCON20 0xF0AA Port 20 Output Control Register
SSC0_TB 0xF0B0 SSC Transmit Buffer (WO)
SSC0_RB 0xF0B2 SSC Receive Buffer (RO)
SSC0_BR 0xF0B4 SSC Baudrate Register
ASC0_ABSTAT 0xF0B8 ASC0 Autobaud Status Register
ASC0_FSTAT 0xF0BA FIFO Status Register
ASC1_ABSTAT 0xF0BC ASC1 Autobaud Status Register
ASC1_FSTAT 0xF0BE FIFO Status Register
SCUSLC 0xF0C0 Security Level Command Reg.
SCUSLC.COMMAND_15 15 Security Level Control Command bit 15
SCUSLC.COMMAND_14 14 Security Level Control Command bit 14
SCUSLC.COMMAND_13 13 Security Level Control Command bit 13
SCUSLC.COMMAND_12 12 Security Level Control Command bit 12
SCUSLC.COMMAND_11 11 Security Level Control Command bit 11
SCUSLC.COMMAND_10 10 Security Level Control Command bit 10
SCUSLC.COMMAND_9 9 Security Level Control Command bit 9
SCUSLC.COMMAND_8 8 Security Level Control Command bit 8
SCUSLC.COMMAND_7 7 Security Level Control Command bit 7
SCUSLC.COMMAND_6 6 Security Level Control Command bit 6
SCUSLC.COMMAND_5 5 Security Level Control Command bit 5
SCUSLC.COMMAND_4 4 Security Level Control Command bit 4
SCUSLC.COMMAND_3 3 Security Level Control Command bit 3
SCUSLC.COMMAND_2 2 Security Level Control Command bit 2
SCUSLC.COMMAND_1 1 Security Level Control Command bit 1
SCUSLC.COMMAND_0 0 Security Level Control Command bit 0
SCUSLS 0xF0C2 Security Level Status Register
SCUSLS.STATE_15 15 Current State of Switching State Machine bit 15
SCUSLS.STATE_14 14 Current State of Switching State Machine bit 14
SCUSLS.STATE_13 13 Current State of Switching State Machine bit 13
SCUSLS.SL_12 12 Security Level bit 12
SCUSLS.SL_11 11 Security Level bit 11
SCUSLS.PASSWORD_7 7 Current Security Control Password bit 7
SCUSLS.PASSWORD_6 6 Current Security Control Password bit 6
SCUSLS.PASSWORD_5 5 Current Security Control Password bit 5
SCUSLS.PASSWORD_4 4 Current Security Control Password bit 4
SCUSLS.PASSWORD_3 3 Current Security Control Password bit 3
SCUSLS.PASSWORD_2 2 Current Security Control Password bit 2
SCUSLS.PASSWORD_1 1 Current Security Control Password bit 1
SCUSLS.PASSWORD_0 0 Current Security Control Password bit 0
ASC0_TxFCON 0xF0C4 Transmit FIFO Control Register
ASC0_RxFCON 0xF0C6 Receive FIFO Control Register
RTC_RELL 0xF0CC RTC Timer Reload Low Register
RTC_RELH 0xF0CE RTC Timer Reload High Register
RTC_T14REL 0xF0D0 Timer 14 Reload Register
RTC_T14 0xF0D2 Timer 14 Register
RTC_RTCL 0xF0D4 RTC Timer Low Register
RTC_RTCH 0xF0D6 RTC Timer High Register
DTIDR 0xF0D8 Task ID register
DTIDR.TASKID_15 15
DTIDR.TASKID_14 14
DTIDR.TASKID_13 13
DTIDR.TASKID_12 12
DTIDR.TASKID_11 11
DTIDR.TASKID_10 10
DTIDR.TASKID_9 9
DTIDR.TASKID_8 8
DTIDR.TASKID_7 7
DTIDR.TASKID_6 6
DTIDR.TASKID_5 5
DTIDR.TASKID_4 4
DTIDR.TASKID_3 3
DTIDR.TASKID_2 2
DTIDR.TASKID_1 1
DTIDR.TASKID_0 0
DCMPSP 0xF0EC Select and Programming Register for DCMPx
DCMPSP.GPR 15 Selects the GPR address format
DCMPSP.SELECT_DCMP_11 11 Select the Comparison Register bit 11
DCMPSP.SELECT_DCMP_10 10 Select the Comparison Register bit 10
DCMPSP.SELECT_DCMP_9 9 Select the Comparison Register bit 9
DCMPSP.SELECT_DCMP_8 8 Select the Comparison Register bit 8
DCMPSP.DCMP_DATA_X_7 7 Sets bit 23 of selected
DCMPSP.DCMP_DATA_X_6 6 Sets bit 22 of selected
DCMPSP.DCMP_DATA_X_5 5 Sets bit 21 of selected
DCMPSP.DCMP_DATA_X_4 4 Sets bit 20 of selected
DCMPSP.DCMP_DATA_X_3 3 Sets bit 19 of selected
DCMPSP.DCMP_DATA_X_2 2 Sets bit 18 of selected
DCMPSP.DCMP_DATA_X_1 1 Sets bit 17 of selected
DCMPSP.DCMP_DATA_X_0 0 Sets bit 16 of selected
DCMPDP 0xF0EE Data programming register for DCMPx
DCMPDP.DCMP_DATA_15 15 Set bit 15 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_14 14 Set bit 14 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_13 13 Set bit 13 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_12 12 Set bit 12 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_11 11 Set bit 11 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_10 10 Set bit 10 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_9 9 Set bit 9 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_8 8 Set bit 8 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_7 7 Set bit 7 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_6 6 Set bit 6 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_5 5 Set bit 5 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_4 4 Set bit 4 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_3 3 Set bit 3 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_2 2 Set bit 2 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_1 1 Set bit 1 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_0 0 Set bit 0 of selected (SELECT_DCMP) DCMP register
DTREVT 0xF0F0 Hardware Trigger Combination Debug Event Control Register
DTREVT.COM_RE 15 Equal and range comparison combination
DTREVT.SELECT_E_14 14 Selects equal/range comparison bit 14
DTREVT.SELECT_E_13 13 Selects equal/range comparison bit 13
DTREVT.MODE_E 12 Controls the complex watch point generation
DTREVT.COM_R_11 11 Select range comparison bit 11
DTREVT.COM_R_10 10 Select range comparison bit 10
DTREVT.MUX_E_9 9 Equal comp. input mux control bit 9
DTREVT.MUX_E_8 8 Equal comp. input mux control bit 8
DTREVT.MUX_R_7 7 Range comparison input mux bit 7
DTREVT.MUX_R_6 6 Range comparison input mux bit 6
DTREVT.ACTIVATE_PIN 5 Identical to ACTIVATE_PIN in DEXEVT
DTREVT.ACT_S_R 4 Activate Second Range for DCMP1 & DCMP2
DTREVT.PERIPHERALS_STOP 3 Identical to PERIPHERALS_STOP in DEXEVT
DTREVT.EVENT_ACTION_1 1 Identical to EVENT_ACTION in DEXEVT bit 1
DTREVT.EVENT_ACTION_0 0 Identical to EVENT_ACTION in DEXEVT bit 0
DEXEVT 0xF0F2 Break Pin Event Control Register
DEXEVT.ACTIVATE_PIN 5
DEXEVT.PERIPHERALS_STOP 3
DEXEVT.EVENT_ACTION_1 1
DEXEVT.EVENT_ACTION_0 0
DSWEVT 0xF0F4 Software Debug Event Control Register
DSWEVT.ACTIVATE_PIN 5
DSWEVT.PERIPHERALS_STOP 3
DSWEVT.EVENT_ACTION_1 1
DSWEVT.EVENT_ACTION_0 0
CMADR 0xF0F8 Call a monitor target address register
CMADR.ADDR_15 15 Bit 15 of the Call A Monitor target address
CMADR.ADDR_14 14 Bit 14 of the Call A Monitor target address
CMADR.ADDR_13 13 Bit 13 of the Call A Monitor target address
CMADR.ADDR_12 12 Bit 12 of the Call A Monitor target address
CMADR.ADDR_11 11 Bit 11 of the Call A Monitor target address
CMADR.ADDR_10 10 Bit 10 of the Call A Monitor target address
CMADR.ADDR_9 9 Bit 9 of the Call A Monitor target address
CMADR.ADDR_8 8 Bit 8 of the Call A Monitor target address
CMADR.ADDR_7 7 Bit 7 of the Call A Monitor target address
CMADR.ADDR_6 6 Bit 6 of the Call A Monitor target address
CMADR.ADDR_5 5 Bit 5 of the Call A Monitor target address
CMADR.ADDR_4 4 Bit 4 of the Call A Monitor target address
CMADR.ADDR_3 3 Bit 3 of the Call A Monitor target address
CMADR.ADDR_2 2 Bit 2 of the Call A Monitor target address
CMADR.ADDR_1 1 Bit 1 of the Call A Monitor target address
CMADR.ADDR_0 0 Bit 0 of the Call A Monitor target address
CMCTR 0xF0FA Call a Monitor Control Register
CMCTR.LEVEL_15 15 Injection Level bit 15
CMCTR.LEVEL_14 14 Injection Level bit 14
CMCTR.LEVEL_13 13 Injection Level bit 13
CMCTR.LEVEL_12 12 Injection Level bit 12
CMCTR.LEVEL_11 11 Injection Level bit 11
CMCTR.BSEL_9 9 Selects the GPR Register Bank bit 9
CMCTR.BSEL_8 8 Selects the GPR Register Bank bit 8
CMCTR.ADDR_7 7 Bit 23 of the Call A Monitor target addres
CMCTR.ADDR_6 6 Bit 22 of the Call A Monitor target addres
CMCTR.ADDR_5 5 Bit 21 of the Call A Monitor target addres
CMCTR.ADDR_4 4 Bit 20 of the Call A Monitor target addres
CMCTR.ADDR_3 3 Bit 19 of the Call A Monitor target addres
CMCTR.ADDR_2 2 Bit 18 of the Call A Monitor target addres
CMCTR.ADDR_1 1 Bit 17 of the Call A Monitor target addres
CMCTR.ADDR_0 0 Bit 16 of the Call A Monitor target addres
DBGSR 0xF0FC Debug Status Register
DBGSR.EVENT_SOURCE_15 15 Reports source of the last debug event bit 15
DBGSR.EVENT_SOURCE_14 14 Reports source of the last debug event bit 14
DBGSR.EVENT_SOURCE_13 13 Reports source of the last debug event bit 13
DBGSR.DBGMOD 11 Specifies the debug mode to be entered in case of a break event
DBGSR.TRGEVT_E_CMP2 10
DBGSR.TRGEVT_E_CMP1 9
DBGSR.TRGEVT_E_CMP0 8
DBGSR.TRGEVT_R_CMP 7
DBGSR.SBRKC 6 Software Break Conflict
DBGSR.CBBM 5 Conditional Break Before Make
DBGSR.OPS 4 OCDS_P_SUSPEND
DBGSR.DEBUG_STATE_3 3 Current debug state bit 3
DBGSR.DEBUG_STATE_2 2 Current debug state bit 2
DBGSR.EXE_ONE_INST 1 Execute one instruction request
DBGSR.DBG_EN 0
IMBCTR 0xF0FE Instruction Memory Block Control Register
IMBCTR.RPA 15 Read Protection Activated
IMBCTR.DDF 9 Disable Data Read from Flas Memory
IMBCTR.DCF 8 Disable Code Fetch from Flas Memory
IMBCTR.WSRAM 2 Wait State Control for programm RAM acsess
IMBCTR.WSFLASH_1 1 Wait States for the Flas Memory bit 1
IMBCTR.WSFLASH_0 0 Wait States for the Flas Memory bit 0
DP0L 0xF100 P0L Direction Control Register
DP0L.P7 7
DP0L.P6 6
DP0L.P5 5
DP0L.P4 4
DP0L.P3 3
DP0L.P2 2
DP0L.P1 1
DP0L.P0 0
DP0H 0xF102 P0H Direction Control Register
DP0H.P7 7
DP0H.P6 6
DP0H.P5 5
DP0H.P4 4
DP0H.P3 3
DP0H.P2 2
DP0H.P1 1
DP0H.P0 0
DP1L 0xF104 P1L Direction Control Register
DP1L.P7 7
DP1L.P6 6
DP1L.P5 5
DP1L.P4 4
DP1L.P3 3
DP1L.P2 2
DP1L.P1 1
DP1L.P0 0
DP1H 0xF106 P1H Direction Control Register
DP1H.P7 7
DP1H.P6 6
DP1H.P5 5
DP1H.P4 4
DP1H.P3 3
DP1H.P2 2
DP1H.P1 1
DP1H.P0 0
RSTCFG 0xF108 Reset Configuration Register
RSTCFG.CLKCFG_15 15 Clock Generation Mode Configuration bit 15
RSTCFG.CLKCFG_14 14 Clock Generation Mode Configuration bit 14
RSTCFG.CLKCFG_13 13 Clock Generation Mode Configuration bit 13
RSTCFG.SALSEL_12 12 Segment Address Line Select bit 12
RSTCFG.SALSEL_11 11 Segment Address Line Select bit 11
RSTCFG.CSSEL_10 10 Chip Select Line Select bit
RSTCFG.CSSEL_9 9 Chip Select Line Select bit
RSTCFG.WRC 8 Write Configuration
RSTCFG.BUSTYP_7 7 External Bus Type bit 7
RSTCFG.BUSTYP_6 6 External Bus Type bit 6
RSTCFG.SMOD_5 5 Special Modes bit 5
RSTCFG.SMOD_4 4 Special Modes bit 4
RSTCFG.SMOD_3 3 Special Modes bit 3
RSTCFG.SMOD_2 2 Special Modes bit 2
RSTCFG.ADP 1 Adapt Mode
RSTCFG.ROC 0 RSTOUT Control
RTC_ISNC 0xF10C RTC Interrupt Sub Node Control Register Low
RTC_ISNC.CNT3IR 9
RTC_ISNC.CNT3IE 8
RTC_ISNC.CNT2IR 7
RTC_ISNC.CNT2IE 6
RTC_ISNC.CNT1IR 5
RTC_ISNC.CNT1IE 4
RTC_ISNC.CNT0IR 3
RTC_ISNC.CNT0IE 2
RTC_ISNC.T14IR 1
RTC_ISNC.T14IE 0
RTC_ISNCH 0xF10E RTC Interrupt Sub Node Control Register High
RTC_CONL 0xF110 RTC Control Register Low
RTC_CONL.ACCPOS 15
RTC_CONL.REFCLK 4
RTC_CONL.T14INC 3
RTC_CONL.T14DEC 2
RTC_CONL.PRE 1
RTC_CONL.RUN 0
RTC_CONH 0xF112 RTC Control Register High
ALTSEL0P1H 0xF120 Alternate I/O Source 0 Port P1H
ALTSEL0P1H.P7 7
ALTSEL0P1H.P6 6
ALTSEL0P1H.P5 5
ALTSEL0P1H.P4 4
ALTSEL0P1H.P3 3
ALTSEL0P1H.P2 2
ALTSEL0P1H.P1 1
ALTSEL0P1H.P0 0
ALTSEL0P3 0xF126 Alternate I/O Source Port 3 Selection
ALTSEL0P3.P13 13
ALTSEL0P3.P11 11
ALTSEL0P3.P10 10
ALTSEL0P3.P9 9
ALTSEL0P3.P8 8
ALTSEL0P3.P3 3
ALTSEL0P3.P1 1
ALTSEL1P3 0xF128 Alternate I/O Source 1 Port P3
ALTSEL1P3.P1 1
ALTSEL0P4 0xF12A Alternate I/O Source 0 Port P4
ALTSEL0P4.P7 7
ALTSEL0P4.P6 6
ALTSEL0P6 0xF12C Alternate I/O Source 0 Port P6
ALTSEL0P1L 0xF130 P1L Alternate Select Register 0
ALTSEL0P1L.P7 7
ALTSEL0P1L.P6 6
ALTSEL0P1L.P5 5
ALTSEL0P1L.P4 4
ALTSEL0P1L.P3 3
ALTSEL0P1L.P2 2
ALTSEL0P1L.P1 1
ALTSEL0P1L.P0 0
ALTSEL1P4 0xF136 Alternate I/O Source 1 Port P4
ALTSEL1P4.P7 7
ALTSEL0P9 0xF138 Alternate I/O Source 0 Port P9
ALTSEL0P9.P5 5
ALTSEL0P9.P4 4
ALTSEL0P9.P3 3
ALTSEL0P9.P2 2
ALTSEL0P9.P1 1
ALTSEL0P9.P0 0
ALTSEL1P9 0xF13A Alternate I/O Source 1 Port P9
ALTSEL1P9.P5 5
ALTSEL1P9.P4 4
ALTSEL1P9.P3 3
ALTSEL1P9.P2 2
ALTSEL1P9.P1 1
ALTSEL1P9.P0 0
ALTSEL0P7 0xF13C Alternate I/O Source 0 Port P7
ALTSEL1P7 0xF13E Alternate I/O Source 1 Port P7
CCU6_IC 0xF140 CAPCOM 6 Interrupt Control Register
CCU6_IC.GPX 8 Group Priority Extension
CCU6_IC.IR 7 Interrupt Request Flag
CCU6_IC.IE 6 Interrupt Enable Control Bit
CCU6_IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_IC.GLVL_1 1 Group Priority Level bit 1
CCU6_IC.GLVL_0 0 Group Priority Level bit 0
CAN_1IC 0xF142 CAN Mode 1 Interrupt Control register
CAN_1IC.GPX 8 Group Priority Extension
CAN_1IC.IR 7 Interrupt Request Flag
CAN_1IC.IE 6 Interrupt Enable Control Bit
CAN_1IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_1IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_1IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_1IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_1IC.GLVL_1 1 Group Priority Level bit 1
CAN_1IC.GLVL_0 0 Group Priority Level bit 0
CAN_2IC 0xF144 CAN Mode 2 Interrupt Control register
CAN_2IC.GPX 8 Group Priority Extension
CAN_2IC.IR 7 Interrupt Request Flag
CAN_2IC.IE 6 Interrupt Enable Control Bit
CAN_2IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_2IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_2IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_2IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_2IC.GLVL_1 1 Group Priority Level bit 1
CAN_2IC.GLVL_0 0 Group Priority Level bit 0
CAN_3IC 0xF146 CAN Mode 3 Interrupt Control register
CAN_3IC.GPX 8 Group Priority Extension
CAN_3IC.IR 7 Interrupt Request Flag
CAN_3IC.IE 6 Interrupt Enable Control Bit
CAN_3IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_3IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_3IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_3IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_3IC.GLVL_1 1 Group Priority Level bit 1
CAN_3IC.GLVL_0 0 Group Priority Level bit 0
CAN_4IC 0xF148 CAN Mode 4 Interrupt Control register
CAN_4IC.GPX 8 Group Priority Extension
CAN_4IC.IR 7 Interrupt Request Flag
CAN_4IC.IE 6 Interrupt Enable Control Bit
CAN_4IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_4IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_4IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_4IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_4IC.GLVL_1 1 Group Priority Level bit 1
CAN_4IC.GLVL_0 0 Group Priority Level bit 0
CAN_5IC 0xF14A CAN Mode 5 Interrupt Control register
CAN_5IC.GPX 8 Group Priority Extension
CAN_5IC.IR 7 Interrupt Request Flag
CAN_5IC.IE 6 Interrupt Enable Control Bit
CAN_5IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_5IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_5IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_5IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_5IC.GLVL_1 1 Group Priority Level bit 1
CAN_5IC.GLVL_0 0 Group Priority Level bit 0
CAN_6IC 0xF14C CAN Mode 6 Interrupt Control register
CAN_6IC.GPX 8 Group Priority Extension
CAN_6IC.IR 7 Interrupt Request Flag
CAN_6IC.IE 6 Interrupt Enable Control Bit
CAN_6IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_6IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_6IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_6IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_6IC.GLVL_1 1 Group Priority Level bit 1
CAN_6IC.GLVL_0 0 Group Priority Level bit 0
CAN_7IC 0xF14E CAN Mode 7 Interrupt Control register
CAN_7IC.GPX 8 Group Priority Extension
CAN_7IC.IR 7 Interrupt Request Flag
CAN_7IC.IE 6 Interrupt Enable Control Bit
CAN_7IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_7IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_7IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_7IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_7IC.GLVL_1 1 Group Priority Level bit 1
CAN_7IC.GLVL_0 0 Group Priority Level bit 0
ASC1_TBIC 0xF150 ASC1 Transmit Buffer Interrupt Control Register
ASC1_TBIC.GPX 8 Group Priority Extension
ASC1_TBIC.IR 7 Interrupt Request Flag
ASC1_TBIC.IE 6 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_TBIC.GLVL_1 1 Group Priority Level bit 1
ASC1_TBIC.GLVL_0 0 Group Priority Level bit 0
ASC0_ABIC 0xF15C ASC0 Autobaud Interrupt Control Register
ASC0_ABIC.GPX 8 Group Priority Extension
ASC0_ABIC.IR 7 Interrupt Request Flag
ASC0_ABIC.IE 6 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_ABIC.GLVL_1 1 Group Priority Level bit 1
ASC0_ABIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC16IC 0xF160 CAPCOM Channel 16 Interrupt Control Register
CC2_CC16IC.GPX 8 Group Priority Extension
CC2_CC16IC.IR 7 Interrupt Request Flag
CC2_CC16IC.IE 6 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC16IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC16IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC17IC 0xF162 CAPCOM Channel 17 Interrupt Control Register
CC2_CC17IC.GPX 8 Group Priority Extension
CC2_CC17IC.IR 7 Interrupt Request Flag
CC2_CC17IC.IE 6 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC17IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC17IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC18IC 0xF164 CAPCOM Channel 18 Interrupt Control Register
CC2_CC18IC.GPX 8 Group Priority Extension
CC2_CC18IC.IR 7 Interrupt Request Flag
CC2_CC18IC.IE 6 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC18IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC18IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC19IC 0xF166 CAPCOM Channel 19 Interrupt Control Register
CC2_CC19IC.GPX 8 Group Priority Extension
CC2_CC19IC.IR 7 Interrupt Request Flag
CC2_CC19IC.IE 6 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC19IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC19IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC20IC 0xF168 CAPCOM Channel 20 Interrupt Control Register
CC2_CC20IC.GPX 8 Group Priority Extension
CC2_CC20IC.IR 7 Interrupt Request Flag
CC2_CC20IC.IE 6 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC20IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC20IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC21IC 0xF16A CAPCOM Channel 21 Interrupt Control Register
CC2_CC21IC.GPX 8 Group Priority Extension
CC2_CC21IC.IR 7 Interrupt Request Flag
CC2_CC21IC.IE 6 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC21IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC21IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC22IC 0xF16C CAPCOM Channel 22 Interrupt Control Register
CC2_CC22IC.GPX 8 Group Priority Extension
CC2_CC22IC.IR 7 Interrupt Request Flag
CC2_CC22IC.IE 6 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC22IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC22IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC23IC 0xF16E CAPCOM Channel 23 Interrupt Control Register
CC2_CC23IC.GPX 8 Group Priority Extension
CC2_CC23IC.IR 7 Interrupt Request Flag
CC2_CC23IC.IE 6 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC23IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC23IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC24IC 0xF170 CAPCOM Channel 24 Interrupt Control Register
CC2_CC24IC.GPX 8 Group Priority Extension
CC2_CC24IC.IR 7 Interrupt Request Flag
CC2_CC24IC.IE 6 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC24IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC24IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC25IC 0xF172 CAPCOM Channel 25 Interrupt Control Register
CC2_CC25IC.GPX 8 Group Priority Extension
CC2_CC25IC.IR 7 Interrupt Request Flag
CC2_CC25IC.IE 6 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC25IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC25IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC26IC 0xF174 CAPCOM Channel 26 Interrupt Control Register
CC2_CC26IC.GPX 8 Group Priority Extension
CC2_CC26IC.IR 7 Interrupt Request Flag
CC2_CC26IC.IE 6 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC26IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC26IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC27IC 0xF176 CAPCOM Channel 27 Interrupt Control Register
CC2_CC27IC.GPX 8 Group Priority Extension
CC2_CC27IC.IR 7 Interrupt Request Flag
CC2_CC27IC.IE 6 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC27IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC27IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC28IC 0xF178 CAPCOM Channel 28 Interrupt Control Register
CC2_CC28IC.GPX 8 Group Priority Extension
CC2_CC28IC.IR 7 Interrupt Request Flag
CC2_CC28IC.IE 6 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC28IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC28IC.GLVL_0 0 Group Priority Level bit 0
CC2_T7IC 0xF17A CAPCOM 2 Timer 7 Interrupt Control Register
CC2_T7IC.GPX 8 Group Priority Extension
CC2_T7IC.IR 7 Interrupt Request Flag
CC2_T7IC.IE 6 Interrupt Enable Control Bit
CC2_T7IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_T7IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_T7IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_T7IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_T7IC.GLVL_1 1 Group Priority Level bit 1
CC2_T7IC.GLVL_0 0 Group Priority Level bit 0
CC2_T8IC 0xF17C CAPCOM 2 Timer 8 Interrupt Control Register
CC2_T8IC.GPX 8 Group Priority Extension
CC2_T8IC.IR 7 Interrupt Request Flag
CC2_T8IC.IE 6 Interrupt Enable Control Bit
CC2_T8IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_T8IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_T8IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_T8IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_T8IC.GLVL_1 1 Group Priority Level bit 1
CC2_T8IC.GLVL_0 0 Group Priority Level bit 0
EOPIC 0xF180 End of PEC Interrupt Control Register
EOPIC.GPX 8 Group Priority Extension
EOPIC.IR 7 Interrupt Request Flag
EOPIC.IE 6 Interrupt Enable Control Bit
EOPIC.ILVL_5 5 Interrupt Enable Control Bit
EOPIC.ILVL_4 4 Interrupt Enable Control Bit
EOPIC.ILVL_3 3 Interrupt Enable Control Bit
EOPIC.ILVL_2 2 Interrupt Enable Control Bit
EOPIC.GLVL_1 1 Group Priority Level bit 1
EOPIC.GLVL_0 0 Group Priority Level bit 0
ASC1_TIC 0xF182 ASC1 Transmit Interrupt Control Register
ASC1_TIC.GPX 8 Group Priority Extension
ASC1_TIC.IR 7 Interrupt Request Flag
ASC1_TIC.IE 6 Interrupt Enable Control Bit
ASC1_TIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_TIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_TIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_TIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_TIC.GLVL_1 1 Group Priority Level bit 1
ASC1_TIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC29IC 0xF184 CAPCOM Channel 29 Interrupt Control Register
CC2_CC29IC.GPX 8 Group Priority Extension
CC2_CC29IC.IR 7 Interrupt Request Flag
CC2_CC29IC.IE 6 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC29IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC29IC.GLVL_0 0 Group Priority Level bit 0
IIC_DIC 0xF186 IIC Data Interrupt Control Register
CCU6_EIC 0xF188 CAPCOM 6 Emergency Interrupt Control Register
CCU6_EIC.GPX 8 Group Priority Extension
CCU6_EIC.IR 7 Interrupt Request Flag
CCU6_EIC.IE 6 Interrupt Enable Control Bit
CCU6_EIC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_EIC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_EIC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_EIC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_EIC.GLVL_1 1 Group Priority Level bit 1
CCU6_EIC.GLVL_0 0 Group Priority Level bit 0
ASC1_RIC 0xF18A ASC1 Receive Interrupt Control Register
ASC1_RIC.GPX 8 Group Priority Extension
ASC1_RIC.IR 7 Interrupt Request Flag
ASC1_RIC.IE 6 Interrupt Enable Control Bit
ASC1_RIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_RIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_RIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_RIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_RIC.GLVL_1 1 Group Priority Level bit 1
ASC1_RIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC30IC 0xF18C CAPCOM Channel 30 Interrupt Control Register
CC2_CC30IC.GPX 8 Group Priority Extension
CC2_CC30IC.IR 7 Interrupt Request Flag
CC2_CC30IC.IE 6 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC30IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC30IC.GLVL_0 0 Group Priority Level bit 0
IIC_PEIC 0xF18E IIC Protocol Event Interrupt Control Register
CCU6_T12IC 0xF190 CAPCOM 6 Timer 12 Interrupt Control Register
CCU6_T12IC.GPX 8 Group Priority Extension
CCU6_T12IC.IR 7 Interrupt Request Flag
CCU6_T12IC.IE 6 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_T12IC.GLVL_1 1 Group Priority Level bit 1
CCU6_T12IC.GLVL_0 0 Group Priority Level bit 0
ASC1_EIC 0xF192 ASC1 Error Interrupt Control Register
ASC1_EIC.GPX 8 Group Priority Extension
ASC1_EIC.IR 7 Interrupt Request Flag
ASC1_EIC.IE 6 Interrupt Enable Control Bit
ASC1_EIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_EIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_EIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_EIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_EIC.GLVL_1 1 Group Priority Level bit 1
ASC1_EIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC31IC 0xF194 CAPCOM Channel 31 Interrupt Control Register
CC2_CC31IC.GPX 8 Group Priority Extension
CC2_CC31IC.IR 7 Interrupt Request Flag
CC2_CC31IC.IE 6 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC31IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC31IC.GLVL_0 0 Group Priority Level bit 0
CAN_0IC 0xF196 CAN Mode 0 Interrupt Control register
CAN_0IC.GPX 8 Group Priority Extension
CAN_0IC.IR 7 Interrupt Request Flag
CAN_0IC.IE 6 Interrupt Enable Control Bit
CAN_0IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_0IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_0IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_0IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_0IC.GLVL_1 1 Group Priority Level bit 1
CAN_0IC.GLVL_0 0 Group Priority Level bit 0
CCU6_T13IC 0xF198 CAPCOM 6 Timer 13 Interrupt Control Register
CCU6_T13IC.GPX 8 Group Priority Extension
CCU6_T13IC.IR 7 Interrupt Request Flag
CCU6_T13IC.IE 6 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_T13IC.GLVL_1 1 Group Priority Level bit 1
CCU6_T13IC.GLVL_0 0 Group Priority Level bit 0
SDLM_IC 0xF19A SDLM Interrupt Control Register
ASC0_TBIC 0xF19C ASC0 Transmit Buffer Interrupt Control Register
ASC0_TBIC.GPX 8 Group Priority Extension
ASC0_TBIC.IR 7 Interrupt Request Flag
ASC0_TBIC.IE 6 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_TBIC.GLVL_1 1 Group Priority Level bit 1
ASC0_TBIC.GLVL_0 0 Group Priority Level bit 0
PLLIC 0xF19E PLL Interrupt Control Register
PLLIC.GPX 8 Group Priority Extension
PLLIC.IR 7 Interrupt Request Flag
PLLIC.IE 6 Interrupt Enable Control Bit
PLLIC.ILVL_5 5 Interrupt Enable Control Bit
PLLIC.ILVL_4 4 Interrupt Enable Control Bit
PLLIC.ILVL_3 3 Interrupt Enable Control Bit
PLLIC.ILVL_2 2 Interrupt Enable Control Bit
PLLIC.GLVL_1 1 Group Priority Level bit 1
PLLIC.GLVL_0 0 Group Priority Level bit 0
RTC_IC 0xF1A0 RTC Interrupt Control Register
RTC_IC.GPX 8 Group Priority Extension
RTC_IC.IR 7 Interrupt Request Flag
RTC_IC.IE 6 Interrupt Enable Control Bit
RTC_IC.ILVL_5 5 Interrupt Enable Control Bit
RTC_IC.ILVL_4 4 Interrupt Enable Control Bit
RTC_IC.ILVL_3 3 Interrupt Enable Control Bit
RTC_IC.ILVL_2 2 Interrupt Enable Control Bit
RTC_IC.GLVL_1 1 Group Priority Level bit 1
RTC_IC.GLVL_0 0 Group Priority Level bit 0
SSC1_TIC 0xF1AA SSC1 Transmit Interrupt Control Register
SSC1_TIC.GPX 8 Group Priority Extension
SSC1_TIC.IR 7 Interrupt Request Flag
SSC1_TIC.IE 6 Interrupt Enable Control Bit
SSC1_TIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_TIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_TIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_TIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_TIC.GLVL_1 1 Group Priority Level bit 1
SSC1_TIC.GLVL_0 0 Group Priority Level bit 0
SSC1_RIC 0xF1AC SSC1 Receive Interrupt Control Register
SSC1_RIC.GPX 8 Group Priority Extension
SSC1_RIC.IR 7 Interrupt Request Flag
SSC1_RIC.IE 6 Interrupt Enable Control Bit
SSC1_RIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_RIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_RIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_RIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_RIC.GLVL_1 1 Group Priority Level bit 1
SSC1_RIC.GLVL_0 0 Group Priority Level bit 0
SSC1_EIC 0xF1AE SSC Error Interrupt Control Register
SSC1_EIC.GPX 8 Group Priority Extension
SSC1_EIC.IR 7 Interrupt Request Flag
SSC1_EIC.IE 6 Interrupt Enable Control Bit
SSC1_EIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_EIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_EIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_EIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_EIC.GLVL_1 1 Group Priority Level bit 1
SSC1_EIC.GLVL_0 0 Group Priority Level bit 0
ASC0_ABCON 0xF1B8 ASC0 Autobaud Control Register
ASC1_ABIC 0xF1BA ASC1 Autobaud Interrupt Control Register
ASC1_ABIC.GPX 8 Group Priority Extension
ASC1_ABIC.IR 7 Interrupt Request Flag
ASC1_ABIC.IE 6 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_ABIC.GLVL_1 1 Group Priority Level bit 1
ASC1_ABIC.GLVL_0 0 Group Priority Level bit 0
ASC1_ABCON 0xF1BC ASC1 Autobaud Control Register
ASC1_ABCON.RXINV 11
ASC1_ABCON.TXINV 10
ASC1_ABCON.FCDETEN 4
ASC1_ABCON.ABDETEN 3
ASC1_ABCON.ABSTEN 2
ASC1_ABCON.AUREN 1
ASC1_ABCON.ABEN 0
SYSCON0 0xF1BE General System Control Register
SYSCON0.RTCRST 15 RTC Reset Trigger
SYSCON0.RTCCM 14 RTC Clocking Mode
EXICON 0xF1C0 External Interrupt Control Register
EXICON.EXI7ES_15 15 External Interrupt 7 Edge Selection Field bit 15
EXICON.EXI7ES_14 14 External Interrupt 7 Edge Selection Field bit 14
EXICON.EXI6ES_13 13 External Interrupt 6 Edge Selection Field bit 13
EXICON.EXI6ES_12 12 External Interrupt 6 Edge Selection Field bit 12
EXICON.EXI5ES_11 11 External Interrupt 5 Edge Selection Field bit 11
EXICON.EXI5ES_10 10 External Interrupt 5 Edge Selection Field bit 10
EXICON.EXI4ES_9 9 External Interrupt 4 Edge Selection Field bit 9
EXICON.EXI4ES_8 8 External Interrupt 4 Edge Selection Field bit 8
EXICON.EXI3ES_7 7 External Interrupt 3 Edge Selection Field bit 7
EXICON.EXI3ES_6 6 External Interrupt 3 Edge Selection Field bit 6
EXICON.EXI2ES_5 5 External Interrupt 2 Edge Selection Field bit 5
EXICON.EXI2ES_4 4 External Interrupt 2 Edge Selection Field bit 4
EXICON.EXI1ES_3 3 External Interrupt 1 Edge Selection Field bit 3
EXICON.EXI1ES_2 2 External Interrupt 1 Edge Selection Field bit 2
EXICON.EXI0ES_1 1 External Interrupt 0 Edge Selection Field bit 1
EXICON.EXI0ES_0 0 External Interrupt 0 Edge Selection Field bit 0
ODP2 0xF1C2 Port 2 Open Drain Control Register
PICON 0xF1C4 Port Input Control Register
PICON.P20HIN 9
PICON.P20LIN 8
PICON.P9LIN 7
PICON.P4LIN 4
PICON.P3HIN 3
PICON.P3LIN 2
ODP3 0xF1C6 Port 3 Open Drain Control Register
ODP3.P13 13
ODP3.P12 12
ODP3.P11 11
ODP3.P10 10
ODP3.P9 9
ODP3.P8 8
ODP3.P7 7
ODP3.P6 6
ODP3.P5 5
ODP3.P4 4
ODP3.P3 3
ODP3.P2 2
ODP3.P1 1
ODP3.P0 0
ODP4 0xF1CA Port 4 Open Drain Control Register
ODP4.P7 7
ODP4.P6 6
ODP4.P5 5
ODP4.P4 4
ODP4.P3 3
ODP4.P2 2
ODP4.P1 1
ODP4.P0 0
ODP6 0xF1CE Port 6 Open Drain Control Register
ODP6.P7 7
ODP6.P6 6
ODP6.P5 5
ODP6.P4 4
ODP6.P3 3
ODP6.P2 2
ODP6.P1 1
ODP6.P0 0
PLLCON 0xF1D0 PLL Control Register
PLLCON.PLLWRI 15 PLLCON Write Ignore Flag
PLLCON.PLLCTRL_14 14 PLL Operation Control bit 14
PLLCON.PLLCTRL_13 13 PLL Operation Control bit 13
PLLCON.PLLMUL_12 12 PLL Multiplication Factor bit 12
PLLCON.PLLMUL_11 11 PLL Multiplication Factor bit 11
PLLCON.PLLMUL_10 10 PLL Multiplication Factor bit 10
PLLCON.PLLMUL_9 9 PLL Multiplication Factor bit 9
PLLCON.PLLMUL_8 8 PLL Multiplication Factor bit 8
PLLCON.PLLVB_7 7 PLL VCO Band Select bit 7
PLLCON.PLLVB_6 6 PLL VCO Band Select bit 6
PLLCON.PLLIDIV_5 5 PLL Input Divider bit 5
PLLCON.PLLIDIV_4 4 PLL Input Divider bit 4
PLLCON.PLLODIV_3 3 PLL Output Divider bit 3
PLLCON.PLLODIV_2 2 PLL Output Divider bit 2
PLLCON.PLLODIV_1 1 PLL Output Divider bit 1
PLLCON.PLLODIV_0 0 PLL Output Divider bit 0
ODP7 0xF1D2 Port 7 Open Drain Control Register
ODP7.P7 7
ODP7.P6 6
ODP7.P5 5
ODP7.P4 4
SYSCON3 0xF1D4 System Control Register 3
SYSCON3.SSC1DIS 15 Synchronous Serial Channel SSC1
SYSCON3.RTCDIS 14 Real Time Clock
SYSCON3.CANDIS 13 On-chip CAN Module
SYSCON3.SDLMDIS 12 On-chip SDLM (J1850 Module)
SYSCON3.I2CDIS 11 On-chip IIC Bus Module
SYSCON3.ASC1DIS 10 USART ASC1
SYSCON3.CC6DIS 8 CAPCOM6 Unit
SYSCON3.CC2DIS 7 CAPCOM Unit 2
SYSCON3.CC1DIS 6 CAPCOM Unit 1
SYSCON3.PFMDIS 5 Program Flash Module
SYSCON3.GPTDIS 3 General Purpose Timer Blocks
SYSCON3.SSC0DIS 2 Synchronous Serial Channel SSC0
SYSCON3.ASC0DIS 1 USART ASC0
SYSCON3.ADCDIS 0 Analog/Digital Converter
EXISEL1 0xF1D8 External Interrupt Input Select Register
EXISEL1.EXI7SS_15 15 External Interrupt 7 Source Selection Field bit 15
EXISEL1.EXI7SS_14 14 External Interrupt 7 Source Selection Field bit 14
EXISEL1.EXI7SS_13 13 External Interrupt 7 Source Selection Field bit 13
EXISEL1.EXI7SS_12 12 External Interrupt 7 Source Selection Field bit 12
EXISEL1.EXI6SS_11 11 External Interrupt 6 Source Selection Field bit 11
EXISEL1.EXI6SS_10 10 External Interrupt 6 Source Selection Field bit 10
EXISEL1.EXI6SS_9 9 External Interrupt 6 Source Selection Field bit 9
EXISEL1.EXI6SS_8 8 External Interrupt 6 Source Selection Field bit 8
EXISEL1.EXI5SS_7 7 External Interrupt 5 Source Selection Field bit 7
EXISEL1.EXI5SS_6 6 External Interrupt 5 Source Selection Field bit 6
EXISEL1.EXI5SS_5 5 External Interrupt 5 Source Selection Field bit 5
EXISEL1.EXI5SS_4 4 External Interrupt 5 Source Selection Field bit 4
EXISEL1.EXI4SS_3 3 External Interrupt 4 Source Selection Field bit 3
EXISEL1.EXI4SS_2 2 External Interrupt 4 Source Selection Field bit 2
EXISEL1.EXI4SS_1 1 External Interrupt 4 Source Selection Field bit 1
EXISEL1.EXI4SS_0 0 External Interrupt 4 Source Selection Field bit 0
EXISEL0 0xF1DA External Interrupt Input Select Register
EXISEL0.EXI3SS_15 15 External Interrupt 3 Source Selection Field bit 15
EXISEL0.EXI3SS_14 14 External Interrupt 3 Source Selection Field bit 14
EXISEL0.EXI3SS_13 13 External Interrupt 3 Source Selection Field bit 13
EXISEL0.EXI3SS_12 12 External Interrupt 3 Source Selection Field bit 12
EXISEL0.EXI2SS_11 11 External Interrupt 2 Source Selection Field bit 11
EXISEL0.EXI2SS_10 10 External Interrupt 2 Source Selection Field bit 10
EXISEL0.EXI2SS_9 9 External Interrupt 2 Source Selection Field bit 9
EXISEL0.EXI2SS_8 8 External Interrupt 2 Source Selection Field bit 8
EXISEL0.EXI1SS_7 7 External Interrupt 1 Source Selection Field bit 7
EXISEL0.EXI1SS_6 6 External Interrupt 1 Source Selection Field bit 6
EXISEL0.EXI1SS_5 5 External Interrupt 1 Source Selection Field bit 5
EXISEL0.EXI1SS_4 4 External Interrupt 1 Source Selection Field bit 4
EXISEL0.EXI0SS_3 3 External Interrupt 0 Source Selection Field bit 3
EXISEL0.EXI0SS_2 2 External Interrupt 0 Source Selection Field bit 2
EXISEL0.EXI0SS_1 1 External Interrupt 0 Source Selection Field bit 1
EXISEL0.EXI0SS_0 0 External Interrupt 0 Source Selection Field bit 0
SYSCON1 0xF1DC System Control Register 1
SYSCON1.CPSYS 8 Clock Prescaler for System
SYSCON1.PFCFG_5 5 Program Flash Configuration bit 5
SYSCON1.PFCFG_4 4 Program Flash Configuration bit 4
SYSCON1.PDCFG_3 3 Port Driver Configuration bit 3
SYSCON1.PDCFG_2 2 Port Driver Configuration bit 2
SYSCON1.SLEEPCON_1 1 SLEEP Mode Configuration bit 1
SYSCON1.SLEEPCON_0 0 SLEEP Mode Configuration bit 0
RSTCON 0xF1E0 Reset Control Register
RSTCON.RODIS 7 RSTOUT Disable Control
RSTCON.ROCON 6 RSTOUT Control Switching ON
RSTCON.ROCOFF 5 RSTOUT Control Switching Off
RSTCON.RORMV 4 RSTOUT Remove Control
RSTCON.RSTLEN_2 2 Reset Length Control bit 2
RSTCON.RSTLEN_1 1 Reset Length Control bit 1
RSTCON.RSTLEN_0 0 Reset Length Control bit 0
SYSSTAT 0xF1E4 System Status Register
SYSSTAT.OSCLOCK 15 Oscillator Signal Status Bit
SYSSTAT.PLLLOCK 14 PLL Signal Status Bit
SYSSTAT.CLKHIX 13 Input Clock High Limit Exceeded
SYSSTAT.CLKLOX 12 Input Clock Low Limit Exceeded
SYSSTAT.PLLEM 10 PLL Emergency Mode Flag
SYSSTAT.HWR 2 Hardware Reset Indication Flag
SYSSTAT.SWR 1 Software Reset Indication Flag
SYSSTAT.WDTR 0 Watchdog Timer Reset Indication Flag
DPP0 0xFE00 Data Page Pointer 0 Register
DPP0.PN_9 9 Data Page Number of DPP bit 9
DPP0.PN_8 8 Data Page Number of DPP bit 8
DPP0.PN_7 7 Data Page Number of DPP bit 7
DPP0.PN_6 6 Data Page Number of DPP bit 6
DPP0.PN_5 5 Data Page Number of DPP bit 5
DPP0.PN_4 4 Data Page Number of DPP bit 4
DPP0.PN_3 3 Data Page Number of DPP bit 3
DPP0.PN_2 2 Data Page Number of DPP bit 2
DPP0.PN_1 1 Data Page Number of DPP bit 1
DPP0.PN_0 0 Data Page Number of DPP bit 0
DPP1 0xFE02 Data Page Pointer 1 Register
DPP1.PN_9 9 Data Page Number of DPP bit 9
DPP1.PN_8 8 Data Page Number of DPP bit 8
DPP1.PN_7 7 Data Page Number of DPP bit 7
DPP1.PN_6 6 Data Page Number of DPP bit 6
DPP1.PN_5 5 Data Page Number of DPP bit 5
DPP1.PN_4 4 Data Page Number of DPP bit 4
DPP1.PN_3 3 Data Page Number of DPP bit 3
DPP1.PN_2 2 Data Page Number of DPP bit 2
DPP1.PN_1 1 Data Page Number of DPP bit 1
DPP1.PN_0 0 Data Page Number of DPP bit 0
DPP2 0xFE04 Data Page Pointer 2 Register
DPP2.PN_9 9 Data Page Number of DPP bit 9
DPP2.PN_8 8 Data Page Number of DPP bit 8
DPP2.PN_7 7 Data Page Number of DPP bit 7
DPP2.PN_6 6 Data Page Number of DPP bit 6
DPP2.PN_5 5 Data Page Number of DPP bit 5
DPP2.PN_4 4 Data Page Number of DPP bit 4
DPP2.PN_3 3 Data Page Number of DPP bit 3
DPP2.PN_2 2 Data Page Number of DPP bit 2
DPP2.PN_1 1 Data Page Number of DPP bit 1
DPP2.PN_0 0 Data Page Number of DPP bit 0
DPP3 0xFE06 Data Page Pointer 3 Register
DPP3.PN_9 9 Data Page Number of DPP bit 9
DPP3.PN_8 8 Data Page Number of DPP bit 8
DPP3.PN_7 7 Data Page Number of DPP bit 7
DPP3.PN_6 6 Data Page Number of DPP bit 6
DPP3.PN_5 5 Data Page Number of DPP bit 5
DPP3.PN_4 4 Data Page Number of DPP bit 4
DPP3.PN_3 3 Data Page Number of DPP bit 3
DPP3.PN_2 2 Data Page Number of DPP bit 2
DPP3.PN_1 1 Data Page Number of DPP bit 1
DPP3.PN_0 0 Data Page Number of DPP bit 0
CSP 0xFE08 Code Segment Pointer Register
CSP.SEGNR_7 7
CSP.SEGNR_6 6
CSP.SEGNR_5 5
CSP.SEGNR_4 4
CSP.SEGNR_3 3
CSP.SEGNR_2 2
CSP.SEGNR_1 1
CSP.SEGNR_0 0
EMUCON 0xFE0A Emulation Control Reg.
EMUCON.OCEN 2 OCDS/Cerberus Enable
EMUCON.OCDSIOEN 1 OCDS Break Input/Output Enable
MDH 0xFE0C Multiply Divide Register - High Word
MDH.MDH_15 15 High part of MD bit 15
MDH.MDH_14 14 High part of MD bit 14
MDH.MDH_13 13 High part of MD bit 13
MDH.MDH_12 12 High part of MD bit 12
MDH.MDH_11 11 High part of MD bit 11
MDH.MDH_10 10 High part of MD bit 10
MDH.MDH_9 9 High part of MD bit 9
MDH.MDH_8 8 High part of MD bit 8
MDH.MDH_7 7 High part of MD bit 7
MDH.MDH_6 6 High part of MD bit 6
MDH.MDH_5 5 High part of MD bit 5
MDH.MDH_4 4 High part of MD bit 4
MDH.MDH_3 3 High part of MD bit 3
MDH.MDH_2 2 High part of MD bit 2
MDH.MDH_1 1 High part of MD bit 1
MDH.MDH_0 0 High part of MD bit 0
MDL 0xFE0E Multiply Divide Register - Low Word
MDL.MDL_15 15 Low part of MD bit 15
MDL.MDL_14 14 Low part of MD bit 14
MDL.MDL_13 13 Low part of MD bit 13
MDL.MDL_12 12 Low part of MD bit 12
MDL.MDL_11 11 Low part of MD bit 11
MDL.MDL_10 10 Low part of MD bit 10
MDL.MDL_9 9 Low part of MD bit 9
MDL.MDL_8 8 Low part of MD bit 8
MDL.MDL_7 7 Low part of MD bit 7
MDL.MDL_6 6 Low part of MD bit 6
MDL.MDL_5 5 Low part of MD bit 5
MDL.MDL_4 4 Low part of MD bit 4
MDL.MDL_3 3 Low part of MD bit 3
MDL.MDL_2 2 Low part of MD bit 2
MDL.MDL_1 1 Low part of MD bit 1
MDL.MDL_0 0 Low part of MD bit 0
CP 0xFE10 Context Pointer Register
CP.CONTEXT_POINTER_11 11 Modifiable Portion of register CP bit 11
CP.CONTEXT_POINTER_10 10 Modifiable Portion of register CP bit 10
CP.CONTEXT_POINTER_9 9 Modifiable Portion of register CP bit 9
CP.CONTEXT_POINTER_8 8 Modifiable Portion of register CP bit 8
CP.CONTEXT_POINTER_7 7 Modifiable Portion of register CP bit 7
CP.CONTEXT_POINTER_6 6 Modifiable Portion of register CP bit 6
CP.CONTEXT_POINTER_5 5 Modifiable Portion of register CP bit 5
CP.CONTEXT_POINTER_4 4 Modifiable Portion of register CP bit 4
CP.CONTEXT_POINTER_3 3 Modifiable Portion of register CP bit 3
CP.CONTEXT_POINTER_2 2 Modifiable Portion of register CP bit 2
CP.CONTEXT_POINTER_1 1 Modifiable Portion of register CP bit 1
SP 0xFE12 Stack Pointer Register
SP.SP_15 15 Modifiable portion of register SP bit 15
SP.SP_14 14 Modifiable portion of register SP bit 14
SP.SP_13 13 Modifiable portion of register SP bit 13
SP.SP_12 12 Modifiable portion of register SP bit 12
SP.SP_11 11 Modifiable portion of register SP bit 11
SP.SP_10 10 Modifiable portion of register SP bit 10
SP.SP_9 9 Modifiable portion of register SP bit 9
SP.SP_8 8 Modifiable portion of register SP bit 8
SP.SP_7 7 Modifiable portion of register SP bit 7
SP.SP_6 6 Modifiable portion of register SP bit 6
SP.SP_5 5 Modifiable portion of register SP bit 5
SP.SP_4 4 Modifiable portion of register SP bit 4
SP.SP_3 3 Modifiable portion of register SP bit 3
SP.SP_2 2 Modifiable portion of register SP bit 2
SP.SP_1 1 Modifiable portion of register SP bit 1
STKOV 0xFE14 Stack Overflow Pointer Register
STKOV.STKOV_15 15 Modifiable portion of register STKOV bit 15
STKOV.STKOV_14 14 Modifiable portion of register STKOV bit 14
STKOV.STKOV_13 13 Modifiable portion of register STKOV bit 13
STKOV.STKOV_12 12 Modifiable portion of register STKOV bit 12
STKOV.STKOV_11 11 Modifiable portion of register STKOV bit 11
STKOV.STKOV_10 10 Modifiable portion of register STKOV bit 10
STKOV.STKOV_9 9 Modifiable portion of register STKOV bit 9
STKOV.STKOV_8 8 Modifiable portion of register STKOV bit 8
STKOV.STKOV_7 7 Modifiable portion of register STKOV bit 7
STKOV.STKOV_6 6 Modifiable portion of register STKOV bit 6
STKOV.STKOV_5 5 Modifiable portion of register STKOV bit 5
STKOV.STKOV_4 4 Modifiable portion of register STKOV bit 4
STKOV.STKOV_3 3 Modifiable portion of register STKOV bit 3
STKOV.STKOV_2 2 Modifiable portion of register STKOV bit 2
STKOV.STKOV_1 1 Modifiable portion of register STKOV bit 1
STKUN 0xFE16 Stack Underflow Pointer Register
STKUN.STKUN_15 15 Modifiable portion of register STKUN bit 15
STKUN.STKUN_14 14 Modifiable portion of register STKUN bit 14
STKUN.STKUN_13 13 Modifiable portion of register STKUN bit 13
STKUN.STKUN_12 12 Modifiable portion of register STKUN bit 12
STKUN.STKUN_11 11 Modifiable portion of register STKUN bit 11
STKUN.STKUN_10 10 Modifiable portion of register STKUN bit 10
STKUN.STKUN_9 9 Modifiable portion of register STKUN bit 9
STKUN.STKUN_8 8 Modifiable portion of register STKUN bit 8
STKUN.STKUN_7 7 Modifiable portion of register STKUN bit 7
STKUN.STKUN_6 6 Modifiable portion of register STKUN bit 6
STKUN.STKUN_5 5 Modifiable portion of register STKUN bit 5
STKUN.STKUN_4 4 Modifiable portion of register STKUN bit 4
STKUN.STKUN_3 3 Modifiable portion of register STKUN bit 3
STKUN.STKUN_2 2 Modifiable portion of register STKUN bit 2
STKUN.STKUN_1 1 Modifiable portion of register STKUN bit 1
CPUCON1 0xFE18 CPU Control Register 1
CPUCON1.VECSC_6 6 Scaling factor of Vector Table bit 6
CPUCON1.VECSC_5 5 Scaling factor of Vector Table bit 5
CPUCON1.WDTCTL 4 Configuration of Watch Dog Timer
CPUCON1.SGTDIS 3 Segmentation Disable/Enable Control
CPUCON1.INTSCXT 2 Enable Interruptibility of Switch Context
CPUCON1.BP 1 Enable Branch Prediction Unit
CPUCON1.ZCJ 0 Enable Zero Cycle Jump function
CPUCON2 0xFE1A CPU Control Register 2
CPUCON2.FIFODEPTH_15 15 FIFO Depth configuration bit 15
CPUCON2.FIFODEPTH_14 14 FIFO Depth configuration bit 14
CPUCON2.FIFODEPTH_13 13 FIFO Depth configuration bit 13
CPUCON2.FIFODEPTH_12 12 FIFO Depth configuration bit 12
CPUCON2.FIFOFED_11 11 FIFO Fed configuration bit 11
CPUCON2.FIFOFED_10 10 FIFO Fed configuration bit 10
CPUCON2.BYPPF 9 Prefetch Bypass control
CPUCON2.BYPF 8 Fetch Bypass control
CPUCON2.EIOIAEN 7 Early IO Injection Acknowledge Enable
CPUCON2.STEN 6 Stall Instruction Enable
CPUCON2.LFIC 5 Linear Follower Instruction Cache
CPUCON2.OVRUN 4 Pipeline control
CPUCON2.RETST 3 Enable return Stack
CPUCON2.DAID 1 Disable Atomic Injection Deny
CPUCON2.SL 0 Enables short loop mode
CC2_SEM 0xFE28 CAPCOM 2 Single Event Control Register
CC2_SEE 0xFE2A CAPCOM 2 Single Event Enable Register
CC1_SEM 0xFE2C CAPCOM 1 Single Event Control Register
CC1_SEE 0xFE2E CAPCOM 1 Single Event Enable Register
GPT12E_T2 0xFE40 GPT1 Timer 2 Register
GPT12E_T3 0xFE42 GPT1 Timer 3 Register
GPT12E_T4 0xFE44 GPT1 Timer 4 Register
GPT12E_T5 0xFE46 GPT2 Timer 5 Register
GPT12E_T6 0xFE48 GPT2 Timer 6 Register
GPT12E_CAPREL 0xFE4A GPT12 Capture/Reload Register
GPT12E_PISEL 0xFE4C Port Input Select Register
CC1_T0 0xFE50 CAPCOM 1 Timer 0 Register
CC1_T1 0xFE52 CAPCOM 1 Timer 1 Register
CC1_T0REL 0xFE54 CAPCOM 1 Timer 0 Reload Register
CC1_T1REL 0xFE56 CC Timer 1 Reloed Register
OPSEN 0xFE58 OCE/OCDS P-Susp. En. Reg
OPSEN.SSC1SEN 15 Module xx Suspend Enable
OPSEN.RTCSEN 14 Module xx Suspend Enable
OPSEN.CC6SEN 8 Module xx Suspend Enable
OPSEN.CC2SEN 7 Module xx Suspend Enable
OPSEN.CC1SEN 6 Module xx Suspend Enable
OPSEN.GPTSEN 2 Module xx Suspend Enable
OPSEN.SSC0SEN 1 Module xx Suspend Enable
OPSEN.ASC0SEN 0 Module xx Suspend Enable
TSTMOD 0xFE5A Test-Mode Register
MAL 0xFE5C MAC Accumulator Low Word
MAL.MAL_15 15 Low part of Accumulator bit 15
MAL.MAL_14 14 Low part of Accumulator bit 14
MAL.MAL_13 13 Low part of Accumulator bit 13
MAL.MAL_12 12 Low part of Accumulator bit 12
MAL.MAL_11 11 Low part of Accumulator bit 11
MAL.MAL_10 10 Low part of Accumulator bit 10
MAL.MAL_9 9 Low part of Accumulator bit 9
MAL.MAL_8 8 Low part of Accumulator bit 8
MAL.MAL_7 7 Low part of Accumulator bit 7
MAL.MAL_6 6 Low part of Accumulator bit 6
MAL.MAL_5 5 Low part of Accumulator bit 5
MAL.MAL_4 4 Low part of Accumulator bit 4
MAL.MAL_3 3 Low part of Accumulator bit 3
MAL.MAL_2 2 Low part of Accumulator bit 2
MAL.MAL_1 1 Low part of Accumulator bit 1
MAL.MAL_0 0 Low part of Accumulator bit 0
MAH 0xFE5E MAC Accumulator High Word
MAH.MAH_15 15 High part of Accumulator bit 15
MAH.MAH_14 14 High part of Accumulator bit 14
MAH.MAH_13 13 High part of Accumulator bit 13
MAH.MAH_12 12 High part of Accumulator bit 12
MAH.MAH_11 11 High part of Accumulator bit 11
MAH.MAH_10 10 High part of Accumulator bit 10
MAH.MAH_9 9 High part of Accumulator bit 9
MAH.MAH_8 8 High part of Accumulator bit 8
MAH.MAH_7 7 High part of Accumulator bit 7
MAH.MAH_6 6 High part of Accumulator bit 6
MAH.MAH_5 5 High part of Accumulator bit 5
MAH.MAH_4 4 High part of Accumulator bit 4
MAH.MAH_3 3 High part of Accumulator bit 3
MAH.MAH_2 2 High part of Accumulator bit 2
MAH.MAH_1 1 High part of Accumulator bit 1
MAH.MAH_0 0 High part of Accumulator bit 0
CC2_CC16 0xFE60 CAPCOM 2 Register 16
CC2_CC17 0xFE62 CAPCOM 2 Register 17
CC2_CC18 0xFE64 CAPCOM 2 Register 18
CC2_CC19 0xFE66 CAPCOM 2 Register 19
CC2_CC20 0xFE68 CAPCOM 2 Register 20
CC2_CC21 0xFE6A CAPCOM 2 Register 21
CC2_CC22 0xFE6C CAPCOM 2 Register 22
CC2_CC23 0xFE6E CAPCOM 2 Register 23
CC2_CC24 0xFE70 CAPCOM 2 Register 24
CC2_CC25 0xFE72 CAPCOM 2 Register 25
CC2_CC26 0xFE74 CAPCOM 2 Register 26
CC2_CC27 0xFE76 CAPCOM 2 Register 27
CC2_CC28 0xFE78 CAPCOM 2 Register 28
CC2_CC29 0xFE7A CAPCOM 2 Register 29
CC2_CC30 0xFE7C CAPCOM 2 Register 30
CC2_CC31 0xFE7E CAPCOM 2 Register 31
CC1_CC0 0xFE80 CAPCOM 1 Register 0
CC1_CC1 0xFE82 CAPCOM 1 Register 1
CC1_CC2 0xFE84 CAPCOM 1 Register 2
CC1_CC3 0xFE86 CAPCOM 1 Register 3
CC1_CC4 0xFE88 CAPCOM 1 Register 4
CC1_CC5 0xFE8A CAPCOM 1 Register 5
CC1_CC6 0xFE8C CAPCOM 1 Register 6
CC1_CC7 0xFE8E CAPCOM 1 Register 7
CC1_CC8 0xFE90 CAPCOM 1 Register 8
CC1_CC9 0xFE92 CAPCOM 1 Register 9
CC1_CC10 0xFE94 CAPCOM 1 Register 10
CC1_CC11 0xFE96 CAPCOM 1 Register 11
CC1_CC12 0xFE98 CAPCOM 1 Register 12
CC1_CC13 0xFE9A CAPCOM 1 Register 13
CC1_CC14 0xFE9C CAPCOM 1 Register 14
CC1_CC15 0xFE9E CAPCOM 1 Register 15
ADC_DAT 0xFEA0 A/D Converter Result Register
ADC_ID 0xFEA8 A/D Converter ID Register
ASC0_PMW 0xFEAA ASC0 IrDA Pulse Mode and Width Reg.
ASC1_PMW 0xFEAC ASC1 IrDA Pulse Mode and Width Reg.
WDT 0xFEAE Watchdog Timer Register (RO)
ASC0_TBUF 0xFEB0 Serial Channel 0 Transmitter Buffer Register (WO)
ASC0_RBUF 0xFEB2 Serial Channel 0 Receiver Buffer Register (RO)
ASC0_BG 0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
ASC0_FDV 0xFEB6 Fractional Divider Register
ASC1_TBUF 0xFEB8 Serial Channel 1 Transmitter Buffer Register (WO)
ASC1_RBUF 0xFEBA Serial Channel 1 Receiver Buffer Register (RO)
ASC1_BG 0xFEBC Serial Channel 1 Baud Rate Generator Reload Register
ASC1_FDV 0xFEBE Fractional Divider Register
PECC0 0xFEC0 PEC Channel 0 Control Register
PECC0.EOPINT 14 End of PEC Interrupt Selection
PECC0.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC0.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC0.CL 11 Channel Link Control
PECC0.INC_10 10 Increment Control bit 10
PECC0.INC_9 9 Increment Control bit 9
PECC0.BWT 8 Byte/Word Transfer Selection
PECC0.COUNT_7 7 PEC Transfer Count bit 7
PECC0.COUNT_6 6 PEC Transfer Count bit 6
PECC0.COUNT_5 5 PEC Transfer Count bit 5
PECC0.COUNT_4 4 PEC Transfer Count bit 4
PECC0.COUNT_3 3 PEC Transfer Count bit 3
PECC0.COUNT_2 2 PEC Transfer Count bit 2
PECC0.COUNT_1 1 PEC Transfer Count bit 1
PECC0.COUNT_0 0 PEC Transfer Count bit 0
PECC1 0xFEC2 PEC Channel 1 Control Register
PECC1.EOPINT 14 End of PEC Interrupt Selection
PECC1.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC1.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC1.CL 11 Channel Link Control
PECC1.INC_10 10 Increment Control bit 10
PECC1.INC_9 9 Increment Control bit 9
PECC1.BWT 8 Byte/Word Transfer Selection
PECC1.COUNT_7 7 PEC Transfer Count bit 7
PECC1.COUNT_6 6 PEC Transfer Count bit 6
PECC1.COUNT_5 5 PEC Transfer Count bit 5
PECC1.COUNT_4 4 PEC Transfer Count bit 4
PECC1.COUNT_3 3 PEC Transfer Count bit 3
PECC1.COUNT_2 2 PEC Transfer Count bit 2
PECC1.COUNT_1 1 PEC Transfer Count bit 1
PECC1.COUNT_0 0 PEC Transfer Count bit 0
PECC2 0xFEC4 PEC Channel 2 Control Register
PECC2.EOPINT 14 End of PEC Interrupt Selection
PECC2.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC2.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC2.CL 11 Channel Link Control
PECC2.INC_10 10 Increment Control bit 10
PECC2.INC_9 9 Increment Control bit 9
PECC2.BWT 8 Byte/Word Transfer Selection
PECC2.COUNT_7 7 PEC Transfer Count bit 7
PECC2.COUNT_6 6 PEC Transfer Count bit 6
PECC2.COUNT_5 5 PEC Transfer Count bit 5
PECC2.COUNT_4 4 PEC Transfer Count bit 4
PECC2.COUNT_3 3 PEC Transfer Count bit 3
PECC2.COUNT_2 2 PEC Transfer Count bit 2
PECC2.COUNT_1 1 PEC Transfer Count bit 1
PECC2.COUNT_0 0 PEC Transfer Count bit 0
PECC3 0xFEC6 PEC Channel 3 Control Register
PECC3.EOPINT 14 End of PEC Interrupt Selection
PECC3.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC3.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC3.CL 11 Channel Link Control
PECC3.INC_10 10 Increment Control bit 10
PECC3.INC_9 9 Increment Control bit 9
PECC3.BWT 8 Byte/Word Transfer Selection
PECC3.COUNT_7 7 PEC Transfer Count bit 7
PECC3.COUNT_6 6 PEC Transfer Count bit 6
PECC3.COUNT_5 5 PEC Transfer Count bit 5
PECC3.COUNT_4 4 PEC Transfer Count bit 4
PECC3.COUNT_3 3 PEC Transfer Count bit 3
PECC3.COUNT_2 2 PEC Transfer Count bit 2
PECC3.COUNT_1 1 PEC Transfer Count bit 1
PECC3.COUNT_0 0 PEC Transfer Count bit 0
PECC4 0xFEC8 PEC Channel 4 Control Register
PECC4.EOPINT 14 End of PEC Interrupt Selection
PECC4.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC4.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC4.CL 11 Channel Link Control
PECC4.INC_10 10 Increment Control bit 10
PECC4.INC_9 9 Increment Control bit 9
PECC4.BWT 8 Byte/Word Transfer Selection
PECC4.COUNT_7 7 PEC Transfer Count bit 7
PECC4.COUNT_6 6 PEC Transfer Count bit 6
PECC4.COUNT_5 5 PEC Transfer Count bit 5
PECC4.COUNT_4 4 PEC Transfer Count bit 4
PECC4.COUNT_3 3 PEC Transfer Count bit 3
PECC4.COUNT_2 2 PEC Transfer Count bit 2
PECC4.COUNT_1 1 PEC Transfer Count bit 1
PECC4.COUNT_0 0 PEC Transfer Count bit 0
PECC5 0xFECA PEC Channel 5 Control Register
PECC5.EOPINT 14 End of PEC Interrupt Selection
PECC5.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC5.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC5.CL 11 Channel Link Control
PECC5.INC_10 10 Increment Control bit 10
PECC5.INC_9 9 Increment Control bit 9
PECC5.BWT 8 Byte/Word Transfer Selection
PECC5.COUNT_7 7 PEC Transfer Count bit 7
PECC5.COUNT_6 6 PEC Transfer Count bit 6
PECC5.COUNT_5 5 PEC Transfer Count bit 5
PECC5.COUNT_4 4 PEC Transfer Count bit 4
PECC5.COUNT_3 3 PEC Transfer Count bit 3
PECC5.COUNT_2 2 PEC Transfer Count bit 2
PECC5.COUNT_1 1 PEC Transfer Count bit 1
PECC5.COUNT_0 0 PEC Transfer Count bit 0
PECC6 0xFECC PEC Channel 6 Control Register
PECC6.EOPINT 14 End of PEC Interrupt Selection
PECC6.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC6.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC6.CL 11 Channel Link Control
PECC6.INC_10 10 Increment Control bit 10
PECC6.INC_9 9 Increment Control bit 9
PECC6.BWT 8 Byte/Word Transfer Selection
PECC6.COUNT_7 7 PEC Transfer Count bit 7
PECC6.COUNT_6 6 PEC Transfer Count bit 6
PECC6.COUNT_5 5 PEC Transfer Count bit 5
PECC6.COUNT_4 4 PEC Transfer Count bit 4
PECC6.COUNT_3 3 PEC Transfer Count bit 3
PECC6.COUNT_2 2 PEC Transfer Count bit 2
PECC6.COUNT_1 1 PEC Transfer Count bit 1
PECC6.COUNT_0 0 PEC Transfer Count bit 0
PECC7 0xFECE PEC Channel 7 Control Register
PECC7.EOPINT 14 End of PEC Interrupt Selection
PECC7.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC7.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC7.CL 11 Channel Link Control
PECC7.INC_10 10 Increment Control bit 10
PECC7.INC_9 9 Increment Control bit 9
PECC7.BWT 8 Byte/Word Transfer Selection
PECC7.COUNT_7 7 PEC Transfer Count bit 7
PECC7.COUNT_6 6 PEC Transfer Count bit 6
PECC7.COUNT_5 5 PEC Transfer Count bit 5
PECC7.COUNT_4 4 PEC Transfer Count bit 4
PECC7.COUNT_3 3 PEC Transfer Count bit 3
PECC7.COUNT_2 2 PEC Transfer Count bit 2
PECC7.COUNT_1 1 PEC Transfer Count bit 1
PECC7.COUNT_0 0 PEC Transfer Count bit 0
P0L 0xFF00 PORT0 Low Register
P0L.P7 7
P0L.P6 6
P0L.P5 5
P0L.P4 4
P0L.P3 3
P0L.P2 2
P0L.P1 1
P0L.P0 0
P0H 0xFF02 Port 0 High Register (Upper half)
P0H.P7 7
P0H.P6 6
P0H.P5 5
P0H.P4 4
P0H.P3 3
P0H.P2 2
P0H.P1 1
P0H.P0 0
P1L 0xFF04 Port 1 Low Register
P1L.P7 7
P1L.P6 6
P1L.P5 5
P1L.P4 4
P1L.P3 3
P1L.P2 2
P1L.P1 1
P1L.P0 0
P1H 0xFF06 Port 1 High Register
P1H.P7 7
P1H.P6 6
P1H.P5 5
P1H.P4 4
P1H.P3 3
P1H.P2 2
P1H.P1 1
P1H.P0 0
IDX0 0xFF08 MAC Unit Address Pointer
IDX0.IDX_15 15 Modifiable portion of register IDX0 bit 15
IDX0.IDX_14 14 Modifiable portion of register IDX0 bit 14
IDX0.IDX_13 13 Modifiable portion of register IDX0 bit 13
IDX0.IDX_12 12 Modifiable portion of register IDX0 bit 12
IDX0.IDX_11 11 Modifiable portion of register IDX0 bit 11
IDX0.IDX_10 10 Modifiable portion of register IDX0 bit 10
IDX0.IDX_9 9 Modifiable portion of register IDX0 bit 9
IDX0.IDX_8 8 Modifiable portion of register IDX0 bit 8
IDX0.IDX_7 7 Modifiable portion of register IDX0 bit 7
IDX0.IDX_6 6 Modifiable portion of register IDX0 bit 6
IDX0.IDX_5 5 Modifiable portion of register IDX0 bit 5
IDX0.IDX_4 4 Modifiable portion of register IDX0 bit 4
IDX0.IDX_3 3 Modifiable portion of register IDX0 bit 3
IDX0.IDX_2 2 Modifiable portion of register IDX0 bit 2
IDX0.IDX_1 1 Modifiable portion of register IDX0 bit 1
IDX1 0xFF0A MAC Unit Address Pointer
IDX1.IDX_15 15 Modifiable portion of register IDX1 bit 15
IDX1.IDX_14 14 Modifiable portion of register IDX1 bit 14
IDX1.IDX_13 13 Modifiable portion of register IDX1 bit 13
IDX1.IDX_12 12 Modifiable portion of register IDX1 bit 12
IDX1.IDX_11 11 Modifiable portion of register IDX1 bit 11
IDX1.IDX_10 10 Modifiable portion of register IDX1 bit 10
IDX1.IDX_9 9 Modifiable portion of register IDX1 bit 9
IDX1.IDX_8 8 Modifiable portion of register IDX1 bit 8
IDX1.IDX_7 7 Modifiable portion of register IDX1 bit 7
IDX1.IDX_6 6 Modifiable portion of register IDX1 bit 6
IDX1.IDX_5 5 Modifiable portion of register IDX1 bit 5
IDX1.IDX_4 4 Modifiable portion of register IDX1 bit 4
IDX1.IDX_3 3 Modifiable portion of register IDX1 bit 3
IDX1.IDX_2 2 Modifiable portion of register IDX1 bit 2
IDX1.IDX_1 1 Modifiable portion of register IDX1 bit 1
SPSEG 0xFF0C Stack Pointer Segment Register
SPSEG.SPSEGNR_7 7 Stack Pointer Segment Number bit 7
SPSEG.SPSEGNR_6 6 Stack Pointer Segment Number bit 6
SPSEG.SPSEGNR_5 5 Stack Pointer Segment Number bit 5
SPSEG.SPSEGNR_4 4 Stack Pointer Segment Number bit 4
SPSEG.SPSEGNR_3 3 Stack Pointer Segment Number bit 3
SPSEG.SPSEGNR_2 2 Stack Pointer Segment Number bit 2
SPSEG.SPSEGNR_1 1 Stack Pointer Segment Number bit 1
SPSEG.SPSEGNR_0 0 Stack Pointer Segment Number bit 0
MDC 0xFF0E Multiply Divide Control Register
MDC.MDRIU 4 Multiply/Divide Register In Use
PSW 0xFF10 Processor Status Word
PSW.ILVL_15 15 CPU Priority Level bit 15
PSW.ILVL_14 14 CPU Priority Level bit 14
PSW.ILVL_13 13 CPU Priority Level bit 13
PSW.ILVL_12 12 CPU Priority Level bit 12
PSW.IEN 11 Interrupt/PEC Enable Bit (globally)
PSW.HLDEN 10 Hold Enable
PSW.BANK_9 9 Reserved for Register File Bank Selection bit 9
PSW.BANK_8 8 Reserved for Register File Bank Selection bit 8
PSW.USR1 7 General Purpose Flag
PSW.USR0 6 General Purpose Flag
PSW.MULIP 5 Multiplication/Division in progress
PSW.E 4 End of Table Flag
PSW.Z 3 Zero Flag
PSW.V 2 Overflow Flag
PSW.C 1 Carry Flag
PSW.N 0 Negative Result
VECSEG 0xFF12 Vector Segment Pointer
VECSEG.vecseg_7 7 Segment number of the Vector Table bit 7
VECSEG.vecseg_6 6 Segment number of the Vector Table bit 6
VECSEG.vecseg_5 5 Segment number of the Vector Table bit 5
VECSEG.vecseg_4 4 Segment number of the Vector Table bit 4
VECSEG.vecseg_3 3 Segment number of the Vector Table bit 3
VECSEG.vecseg_2 2 Segment number of the Vector Table bit 2
VECSEG.vecseg_1 1 Segment number of the Vector Table bit 1
VECSEG.vecseg_0 0 Segment number of the Vector Table bit 0
P9 0xFF16 Port 9 Data Register
P9.P5 5
P9.P4 4
P9.P3 3
P9.P2 2
P9.P1 1
P9.P0 0
DP9 0xFF18 Port 9 Direction Control Register
DP9.P5 5
DP9.P4 4
DP9.P3 3
DP9.P2 2
DP9.P1 1
DP9.P0 0
ODP9 0xFF1A Port 9 Open Drain Control Register
ODP9.P5 5
ODP9.P4 4
ODP9.P3 3
ODP9.P2 2
ODP9.P1 1
ODP9.P0 0
ZEROS 0xFF1C Constant Zeros Register
ONES 0xFF1E Constant Ones Register
CC2_T78CON 0xFF20 CAPCOM 2 Timer 7 and Timer 8 Control Register
CC2_T78CON.T8R 14
CC2_T78CON.T8M 11
CC2_T78CON.T7R 6
CC2_T78CON.T7M 3
CC2_M4 0xFF22 CC Mode Control Register 4
CC2_M4.ACC19 15
CC2_M4.ACC18 11
CC2_M4.ACC17 7
CC2_M4.ACC16 3
CC2_M5 0xFF24 CC Mode Control Register 5
CC2_M5.ACC23 15
CC2_M5.ACC22 11
CC2_M5.ACC21 7
CC2_M5.ACC20 3
CC2_M6 0xFF26 CC Mode Control Register 6
CC2_M6.ACC27 15
CC2_M6.ACC26 11
CC2_M6.ACC25 7
CC2_M6.ACC24 3
CC2_M7 0xFF28 CC Mode Control Register 7
CC2_M7.ACC31 15
CC2_M7.ACC30 11
CC2_M7.ACC29 7
CC2_M7.ACC28 3
CC2_DRM 0xFF2A CAPCOM 2 Double Register Mode Register
CC2_OUT 0xFF2C CAPCOM 2 Output Register
CC2_OUT.CC15IO 15
CC2_OUT.CC14IO 14
CC2_OUT.CC13IO 13
CC2_OUT.CC12IO 12
CC2_OUT.CC11IO 11
CC2_OUT.CC10IO 10
CC2_OUT.CC9IO 9
CC2_OUT.CC8IO 8
CC2_OUT.CC7IO 7
CC2_OUT.CC6IO 6
CC2_OUT.CC5IO 5
CC2_OUT.CC4IO 4
CC2_OUT.CC3IO 3
CC2_OUT.CC2IO 2
CC2_OUT.CC1IO 1
CC2_OUT.CC0IO 0
GPT12E_T2CON 0xFF40 GPT1 Timer 2 Control Register
GPT12E_T2CON.T2RDIR 15
GPT12E_T2CON.T2CHDIR 14
GPT12E_T2CON.T2EDGE 13
GPT12E_T2CON.T2IRDIS 12
GPT12E_T2CON.T2RC 9
GPT12E_T2CON.T2UDE 8
GPT12E_T2CON.T2UD 7
GPT12E_T2CON.T2R 6
GPT12E_T3CON 0xFF42 GPT1 Timer 3 Control Register
GPT12E_T3CON.T3RDIR 15
GPT12E_T3CON.T3CHDIR 14
GPT12E_T3CON.T3EDGE 13
GPT12E_T3CON.T3OTL 10
GPT12E_T3CON.T3OE 9
GPT12E_T3CON.T3UDE 8
GPT12E_T3CON.T3UD 7
GPT12E_T3CON.T3R 6
GPT12E_T4CON 0xFF44 GPT1 Timer 4 Control Register
GPT12E_T4CON.T4RDIR 15
GPT12E_T4CON.T4CHDIR 14
GPT12E_T4CON.T4EDGE 13
GPT12E_T4CON.T4IRDIS 12
GPT12E_T4CON.T4RC 9
GPT12E_T4CON.T4UDE 8
GPT12E_T4CON.T4UD 7
GPT12E_T4CON.T4R 6
GPT12E_T5CON 0xFF46 GPT2 Timer 5 Control Register
GPT12E_T5CON.T5SC 15
GPT12E_T5CON.T5CLR 14
GPT12E_T5CON.T5CC 11
GPT12E_T5CON.CT3 10
GPT12E_T5CON.T5RC 9
GPT12E_T5CON.T5UDE 8
GPT12E_T5CON.T5UD 7
GPT12E_T5CON.T5R 6
GPT12E_T6CON 0xFF48 GPT2 Timer 6 Control Register
GPT12E_T6CON.T6SR 15
GPT12E_T6CON.T6CLR 14
GPT12E_T6CON.T6OTL 10
GPT12E_T6CON.T6OE 9
GPT12E_T6CON.T6UDE 8
GPT12E_T6CON.T6UD 7
GPT12E_T6CON.T6R 6
CC1_T01CON 0xFF50 Timer 0/1 Control Register
CC1_T01CON.T1R 14
CC1_T01CON.T1M 11
CC1_T01CON.T0R 6
CC1_T01CON.T0M 3
CC1_M0 0xFF52 Capture/Compare Mode Registers for the CAPCOM Unit (CC0...CC3)
CC1_M0.ACC3 15
CC1_M0.ACC2 11
CC1_M0.ACC1 7
CC1_M0.ACC0 3
CC1_M1 0xFF54 Capture/Compare Mode Register for the CAPCOM Unit (CC4...CC79)
CC1_M1.ACC7 15
CC1_M1.ACC6 11
CC1_M1.ACC5 7
CC1_M1.ACC4 3
CC1_M2 0xFF56 Capture/Compare Mode Registers for the CAPCOM Unit (CC8...CC11)
CC1_M2.ACC11 15
CC1_M2.ACC10 11
CC1_M2.ACC9 7
CC1_M2.ACC8 3
CC1_M3 0xFF58 Capture/Compare Mode Registers for the CAPCOM Unit (CC12...CC15)
CC1_M3.ACC15 15
CC1_M3.ACC14 11
CC1_M3.ACC13 7
CC1_M3.ACC12 3
CC1_DRM 0xFF5A CAPCOM1 Double Register Mode Register
CC1_OUT 0xFF5C CAPCOM1 Output Register
CC1_OUT.CC0I15 15
CC1_OUT.CC0I14 14
CC1_OUT.CC0I13 13
CC1_OUT.CC0I12 12
CC1_OUT.CC0I11 11
CC1_OUT.CC0I10 10
CC1_OUT.CC0I9 9
CC1_OUT.CC0I8 8
CC1_OUT.CC0I7 7
CC1_OUT.CC0I6 6
CC1_OUT.CC0I5 5
CC1_OUT.CC0I4 4
CC1_OUT.CC0I3 3
CC1_OUT.CC0I2 2
CC1_OUT.CC0I1 1
CC1_OUT.CC0I0 0
SSC1_CON 0xFF5E SSC1 Control Register
SSC1_CON.EN 15
SSC1_CON.MS 14
SSC1_CON.AREN 12
SSC1_CON.BEN 11
SSC1_CON.PEN 10
SSC1_CON.REN 9
SSC1_CON.TEN 8
SSC1_CON.LB 7
SSC1_CON.PO 6
SSC1_CON.PH 5
SSC1_CON.HB 4
GPT12E_T2IC 0xFF60 GPT1 Timer 2 Interrupt Control Register
GPT12E_T2IC.GPX 8 Group Priority Extension
GPT12E_T2IC.IR 7 Interrupt Request Flag
GPT12E_T2IC.IE 6 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T2IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T2IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T3IC 0xFF62 GPT1 Timer 3 Interrupt Control Register
GPT12E_T3IC.GPX 8 Group Priority Extension
GPT12E_T3IC.IR 7 Interrupt Request Flag
GPT12E_T3IC.IE 6 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T3IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T3IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T4IC 0xFF64 GPT1 Timer 4 Interrupt Control Register
GPT12E_T4IC.GPX 8 Group Priority Extension
GPT12E_T4IC.IR 7 Interrupt Request Flag
GPT12E_T4IC.IE 6 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T4IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T4IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T5IC 0xFF66 GPT2 Timer 5 Interrupt Control Register
GPT12E_T5IC.GPX 8 Group Priority Extension
GPT12E_T5IC.IR 7 Interrupt Request Flag
GPT12E_T5IC.IE 6 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T5IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T5IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T6IC 0xFF68 GPT2 Timer 6 Interrupt Control Register
GPT12E_T6IC.GPX 8 Group Priority Extension
GPT12E_T6IC.IR 7 Interrupt Request Flag
GPT12E_T6IC.IE 6 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T6IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T6IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_CRIC 0xFF6A GPT2 CAPREL Interrupt Control Register
GPT12E_CRIC.GPX 8 Group Priority Extension
GPT12E_CRIC.IR 7 Interrupt Request Flag
GPT12E_CRIC.IE 6 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_CRIC.GLVL_1 1 Group Priority Level bit 1
GPT12E_CRIC.GLVL_0 0 Group Priority Level bit 0
ASC0_TIC 0xFF6C ASC0 Transmit Interrupt Control Register
ASC0_TIC.GPX 8 Group Priority Extension
ASC0_TIC.IR 7 Interrupt Request Flag
ASC0_TIC.IE 6 Interrupt Enable Control Bit
ASC0_TIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_TIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_TIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_TIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_TIC.GLVL_1 1 Group Priority Level bit 1
ASC0_TIC.GLVL_0 0 Group Priority Level bit 0
ASC0_RIC 0xFF6E ASC0 Receive Interrupt Control Register
ASC0_RIC.GPX 8 Group Priority Extension
ASC0_RIC.IR 7 Interrupt Request Flag
ASC0_RIC.IE 6 Interrupt Enable Control Bit
ASC0_RIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_RIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_RIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_RIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_RIC.GLVL_1 1 Group Priority Level bit 1
ASC0_RIC.GLVL_0 0 Group Priority Level bit 0
ASC0_EIC 0xFF70 ASC0 Error Interrupt Control Register
ASC0_EIC.GPX 8 Group Priority Extension
ASC0_EIC.IR 7 Interrupt Request Flag
ASC0_EIC.IE 6 Interrupt Enable Control Bit
ASC0_EIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_EIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_EIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_EIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_EIC.GLVL_1 1 Group Priority Level bit 1
ASC0_EIC.GLVL_0 0 Group Priority Level bit 0
SSC0_TIC 0xFF72 SSC0 Transmit Interrupt Control Register
SSC0_TIC.GPX 8 Group Priority Extension
SSC0_TIC.IR 7 Interrupt Request Flag
SSC0_TIC.IE 6 Interrupt Enable Control Bit
SSC0_TIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_TIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_TIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_TIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_TIC.GLVL_1 1 Group Priority Level bit 1
SSC0_TIC.GLVL_0 0 Group Priority Level bit 0
SSC0_RIC 0xFF74 SSC0 Receive Interrupt Control Register
SSC0_RIC.GPX 8 Group Priority Extension
SSC0_RIC.IR 7 Interrupt Request Flag
SSC0_RIC.IE 6 Interrupt Enable Control Bit
SSC0_RIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_RIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_RIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_RIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_RIC.GLVL_1 1 Group Priority Level bit 1
SSC0_RIC.GLVL_0 0 Group Priority Level bit 0
SSC0_EIC 0xFF76 SSC0 Error Interrupt Control Register
SSC0_EIC.GPX 8 Group Priority Extension
SSC0_EIC.IR 7 Interrupt Request Flag
SSC0_EIC.IE 6 Interrupt Enable Control Bit
SSC0_EIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_EIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_EIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_EIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_EIC.GLVL_1 1 Group Priority Level bit 1
SSC0_EIC.GLVL_0 0 Group Priority Level bit 0
CC1_CC0IC 0xFF78 CAPCOM Channel 0 Interrupt Control Register
CC1_CC0IC.GPX 8 Group Priority Extension
CC1_CC0IC.IR 7 Interrupt Request Flag
CC1_CC0IC.IE 6 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC0IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC0IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC1IC 0xFF7A CAPCOM Channel 1 Interrupt Control Register
CC1_CC1IC.GPX 8 Group Priority Extension
CC1_CC1IC.IR 7 Interrupt Request Flag
CC1_CC1IC.IE 6 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC1IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC1IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC2IC 0xFF7C CAPCOM Channel 2 Interrupt Control Register
CC1_CC2IC.GPX 8 Group Priority Extension
CC1_CC2IC.IR 7 Interrupt Request Flag
CC1_CC2IC.IE 6 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC2IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC2IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC3IC 0xFF7E CAPCOM Channel 3 Interrupt Control Register
CC1_CC3IC.GPX 8 Group Priority Extension
CC1_CC3IC.IR 7 Interrupt Request Flag
CC1_CC3IC.IE 6 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC3IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC3IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC4IC 0xFF80 CAPCOM Channel 4 Interrupt Control Register
CC1_CC4IC.GPX 8 Group Priority Extension
CC1_CC4IC.IR 7 Interrupt Request Flag
CC1_CC4IC.IE 6 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC4IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC4IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC5IC 0xFF82 CAPCOM Channel 5 Interrupt Control Register
CC1_CC5IC.GPX 8 Group Priority Extension
CC1_CC5IC.IR 7 Interrupt Request Flag
CC1_CC5IC.IE 6 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC5IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC5IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC6IC 0xFF84 CAPCOM Channel 6 Interrupt Control Register
CC1_CC6IC.GPX 8 Group Priority Extension
CC1_CC6IC.IR 7 Interrupt Request Flag
CC1_CC6IC.IE 6 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC6IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC6IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC7IC 0xFF86 CC Register 7 Interrupt Control Register
CC1_CC7IC.GPX 8 Group Priority Extension
CC1_CC7IC.IR 7 Interrupt Request Flag
CC1_CC7IC.IE 6 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC7IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC7IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC8IC 0xFF88 CC Register 8 Interrupt Control Register
CC1_CC8IC.GPX 8 Group Priority Extension
CC1_CC8IC.IR 7 Interrupt Request Flag
CC1_CC8IC.IE 6 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC8IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC8IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC9IC 0xFF8A CC Register 9 Interrupt Control Register
CC1_CC9IC.GPX 8 Group Priority Extension
CC1_CC9IC.IR 7 Interrupt Request Flag
CC1_CC9IC.IE 6 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC9IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC9IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC10IC 0xFF8C CAPCOM Channel 10 Interrupt Control Register
CC1_CC10IC.GPX 8 Group Priority Extension
CC1_CC10IC.IR 7 Interrupt Request Flag
CC1_CC10IC.IE 6 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC10IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC10IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC11IC 0xFF8E CAPCOM Channel 11 Interrupt Control Register
CC1_CC11IC.GPX 8 Group Priority Extension
CC1_CC11IC.IR 7 Interrupt Request Flag
CC1_CC11IC.IE 6 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC11IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC11IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC12IC 0xFF90 CAPCOM Channel 12 Interrupt Control Register
CC1_CC12IC.GPX 8 Group Priority Extension
CC1_CC12IC.IR 7 Interrupt Request Flag
CC1_CC12IC.IE 6 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC12IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC12IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC13IC 0xFF92 CAPCOM Channel 13 Interrupt Control Register
CC1_CC13IC.GPX 8 Group Priority Extension
CC1_CC13IC.IR 7 Interrupt Request Flag
CC1_CC13IC.IE 6 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC13IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC13IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC14IC 0xFF94 CAPCOM Channel 14 Interrupt Control Register
CC1_CC14IC.GPX 8 Group Priority Extension
CC1_CC14IC.IR 7 Interrupt Request Flag
CC1_CC14IC.IE 6 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC14IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC14IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC15IC 0xFF96 CAPCOM Channel 15 Interrupt Control Register
CC1_CC15IC.GPX 8 Group Priority Extension
CC1_CC15IC.IR 7 Interrupt Request Flag
CC1_CC15IC.IE 6 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC15IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC15IC.GLVL_0 0 Group Priority Level bit 0
ADC_CIC 0xFF98 ADC End of Conversion Interrupt Control Register
ADC_CIC.GPX 8 Group Priority Extension
ADC_CIC.IR 7 Interrupt Request Flag
ADC_CIC.IE 6 Interrupt Enable Control Bit
ADC_CIC.ILVL_5 5 Interrupt Enable Control Bit
ADC_CIC.ILVL_4 4 Interrupt Enable Control Bit
ADC_CIC.ILVL_3 3 Interrupt Enable Control Bit
ADC_CIC.ILVL_2 2 Interrupt Enable Control Bit
ADC_CIC.GLVL_1 1 Group Priority Level bit 1
ADC_CIC.GLVL_0 0 Group Priority Level bit 0
ADC_EIC 0xFF9A ADC Overrun Error Control Register
ADC_EIC.GPX 8
ADC_EIC.IR 7
ADC_EIC.IE 6
CC1_T0IC 0xFF9C CAPCOM 1 Timer 0 Interrupt Control Register
CC1_T0IC.GPX 8 Group Priority Extension
CC1_T0IC.IR 7 Interrupt Request Flag
CC1_T0IC.IE 6 Interrupt Enable Control Bit
CC1_T0IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_T0IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_T0IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_T0IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_T0IC.GLVL_1 1 Group Priority Level bit 1
CC1_T0IC.GLVL_0 0 Group Priority Level bit 0
CC1_T1IC 0xFF9E CC Timer 1 Interrupt Control Register
CC1_T1IC.GPX 8 Group Priority Extension
CC1_T1IC.IR 7 Interrupt Request Flag
CC1_T1IC.IE 6 Interrupt Enable Control Bit
CC1_T1IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_T1IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_T1IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_T1IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_T1IC.GLVL_1 1 Group Priority Level bit 1
CC1_T1IC.GLVL_0 0 Group Priority Level bit 0
ADC_CON 0xFFA0 A/D Converter Control Register
P5 0xFFA2 Port 5 Data Register
P5.P15 15
P5.P14 14
P5.P13 13
P5.P12 12
P5.P11 11
P5.P10 10
P5.P7 7
P5.P6 6
P5.P5 5
P5.P4 4
P5.P3 3
P5.P2 2
P5.P1 1
P5.P0 0
P5DIDIS 0xFFA4 Port 5 Digital Input Disable
P5DIDIS.P15 15
P5DIDIS.P14 14
P5DIDIS.P13 13
P5DIDIS.P12 12
P5DIDIS.P11 11
P5DIDIS.P10 10
P5DIDIS.P7 7
P5DIDIS.P6 6
P5DIDIS.P5 5
P5DIDIS.P4 4
P5DIDIS.P3 3
P5DIDIS.P2 2
P5DIDIS.P1 1
P5DIDIS.P0 0
ADC_CON1 0xFFA6 A/D Converter Control Register 1
PECISNC 0xFFA8 PEC Interrupt Subnode Control Register
PECISNC.C7IR 15 Interrupt Sub Node Request Flag of PEC Channel 7
PECISNC.C7IE 14 Interrupt Sub Node Enable Control Bit of PEC Channel 7
PECISNC.C6IR 13 Interrupt Sub Node Request Flag of PEC Channel 6
PECISNC.C6IE 12 Interrupt Sub Node Enable Control Bit of PEC Channel 6
PECISNC.C5IR 11 Interrupt Sub Node Request Flag of PEC Channel 5
PECISNC.C5IE 10 Interrupt Sub Node Enable Control Bit of PEC Channel 5
PECISNC.C4IR 9 Interrupt Sub Node Request Flag of PEC Channel 4
PECISNC.C4IE 8 Interrupt Sub Node Enable Control Bit of PEC Channel 4
PECISNC.C3IR 7 Interrupt Sub Node Request Flag of PEC Channel 3
PECISNC.C3IE 6 Interrupt Sub Node Enable Control Bit of PEC Channel 3
PECISNC.C2IR 5 Interrupt Sub Node Request Flag of PEC Channel 2
PECISNC.C2IE 4 Interrupt Sub Node Enable Control Bit of PEC Channel 2
PECISNC.C1IR 3 Interrupt Sub Node Request Flag of PEC Channel 1
PECISNC.C1IE 2 Interrupt Sub Node Enable Control Bit of PEC Channel 1
PECISNC.C0IR 1 Interrupt Sub Node Request Flag of PEC Channel 0
PECISNC.C0IE 0 Interrupt Sub Node Enable Control Bit of PEC Channel 0
FOCON 0xFFAA Frequency Output Control Register
FOCON.FOEN 15 Frequency Output Enable
FOCON.FOSS 14 Frequency Output Signal Select
FOCON.FORV_13 13 Frequency Output Reload Value bit 13
FOCON.FORV_12 12 Frequency Output Reload Value bit 12
FOCON.FORV_11 11 Frequency Output Reload Value bit 11
FOCON.FORV_10 10 Frequency Output Reload Value bit 10
FOCON.FORV_9 9 Frequency Output Reload Value bit 9
FOCON.FORV_8 8 Frequency Output Reload Value bit 8
FOCON.CLKEN 7 CLKOUT Enable
FOCON.FOTL 6 Frequency Output Toggle Latch
FOCON.FOCNT_5 5 Frequency Output Counter bit 5
FOCON.FOCNT_4 4 Frequency Output Counter bit 4
FOCON.FOCNT_3 3 Frequency Output Counter bit 3
FOCON.FOCNT_2 2 Frequency Output Counter bit 2
FOCON.FOCNT_1 1 Frequency Output Counter bit 1
FOCON.FOCNT_0 0 Frequency Output Counter bit 0
TFR 0xFFAC Trap Flag Register
TFR.NMI 15 Non maskable interrupt flag
TFR.STKOF 14 Stack overflow flag
TFR.STKUF 13 Stack underflow flag
TFR.SOFTBRK 12 Software Break
TFR.UNDOPC 7 Undefined Opcode
TFR.PACER 4 Program Memory Interface Access Error
TFR.PRTFLT 3 Protection Fault
TFR.ILLOPA 2 Illegal word operand access
WDTCON 0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL_15 15 Watchdog Timer Reload Value bit 15
WDTCON.WDTREL_14 14 Watchdog Timer Reload Value bit 14
WDTCON.WDTREL_13 13 Watchdog Timer Reload Value bit 13
WDTCON.WDTREL_12 12 Watchdog Timer Reload Value bit 12
WDTCON.WDTREL_11 11 Watchdog Timer Reload Value bit 11
WDTCON.WDTREL_10 10 Watchdog Timer Reload Value bit 10
WDTCON.WDTREL_9 9 Watchdog Timer Reload Value bit 9
WDTCON.WDTREL_8 8 Watchdog Timer Reload Value bit 8
WDTCON.WDTIN_1 1 Watchdog Timer Input Frequency Select bit 1
WDTCON.WDTIN_0 0 Watchdog Timer Input Frequency Select bit 0
ASC0_CON 0xFFB0 Serial Channel 0 Control Register
SSC0_CON 0xFFB2 SSC Control Register
SSC0_CON.EN 15
SSC0_CON.MS 14
SSC0_CON.AREN 12
SSC0_CON.BEN 11
SSC0_CON.PEN 10
SSC0_CON.REN 9
SSC0_CON.TEN 8
SSC0_CON.LB 7
SSC0_CON.PO 6
SSC0_CON.PH 5
SSC0_CON.HB 4
P20 0xFFB4 Port 20 Data Register
P20.P12 12
P20.P5 5
P20.P4 4
P20.P1 1
P20.P0 0
DP20 0xFFB6 Port 20 Direction Control Register
DP20.P12 12
DP20.P5 5
DP20.P4 4
DP20.P1 1
DP20.P0 0
ASC1_CON 0xFFB8 DCH Serial Channel 1 Control Register
ASC1_CON.R 15
ASC1_CON.LB 14
ASC1_CON.BRS 13
ASC1_CON.ODD 12
ASC1_CON.S0FDE 11
ASC1_CON.OE 10
ASC1_CON.FE 9
ASC1_CON.PE 8
ASC1_CON.OEN 7
ASC1_CON.FEN 6
ASC1_CON.PEN 5
ASC1_CON.REN 4
ASC1_CON.STP 3
ADC_CTR0 0xFFBE DFH A/D Converter Control Register 0
P2 0xFFC0 Port 2 Data Register
P2.P15 15
P2.P14 14
P2.P13 13
P2.P12 12
P2.P11 11
P2.P10 10
P2.P9 9
P2.P8 8
DP2 0xFFC2 Port 2 Direction Control Register
DP2.P15 15
DP2.P14 14
DP2.P13 13
DP2.P12 12
DP2.P11 11
DP2.P10 10
DP2.P9 9
DP2.P8 8
P3 0xFFC4 E2H Port 3 Data Register
P3.P15 15
P3.P13 13
P3.P12 12
P3.P11 11
P3.P10 10
P3.P9 9
P3.P8 8
P3.P7 7
P3.P6 6
P3.P5 5
P3.P4 4
P3.P3 3
P3.P2 2
P3.P1 1
P3.P0 0
DP3 0xFFC6 E3H Port 3 Direction Control Register
DP3.P15 15
DP3.P13 13
DP3.P12 12
DP3.P11 11
DP3.P10 10
DP3.P9 9
DP3.P8 8
DP3.P7 7
DP3.P6 6
DP3.P5 5
DP3.P4 4
DP3.P3 3
DP3.P2 2
DP3.P1 1
DP3.P0 0
P4 0xFFC8 E4H Port 4 Data Register
P4.P7 7
P4.P6 6
P4.P5 5
P4.P4 4
P4.P3 3
P4.P2 2
P4.P1 1
P4.P0 0
DP4 0xFFCA E5H Port 4 Direction Control Register
DP4.P7 7
DP4.P6 6
DP4.P5 5
DP4.P4 4
DP4.P3 3
DP4.P2 2
DP4.P1 1
DP4.P0 0
P6 0xFFCC Port 6 Data Register
P6.P7 7
P6.P6 6
P6.P5 5
P6.P4 4
P6.P3 3
P6.P2 2
P6.P1 1
P6.P0 0
DP6 0xFFCE Port 6 Direction Control Register
DP6.P7 7
DP6.P6 6
DP6.P5 5
DP6.P4 4
DP6.P3 3
DP6.P2 2
DP6.P1 1
DP6.P0 0
P7 0xFFD0 Port 7 Data Register
P7.P7 7
P7.P6 6
P7.P5 5
P7.P4 4
DP7 0xFFD2 Port 7 Direction Control Register
DP7.P7 7
DP7.P6 6
DP7.P5 5
DP7.P4 4
MRW 0xFFDA EDH MAC Repeat Word
MRW.REPEAT_COUNT_15 15 16-bit loop counter bit 15
MRW.REPEAT_COUNT_14 14 16-bit loop counter bit 14
MRW.REPEAT_COUNT_13 13 16-bit loop counter bit 13
MRW.REPEAT_COUNT_12 12 16-bit loop counter bit 12
MRW.REPEAT_COUNT_11 11 16-bit loop counter bit 11
MRW.REPEAT_COUNT_10 10 16-bit loop counter bit 10
MRW.REPEAT_COUNT_9 9 16-bit loop counter bit 9
MRW.REPEAT_COUNT_8 8 16-bit loop counter bit 8
MRW.REPEAT_COUNT_7 7 16-bit loop counter bit 7
MRW.REPEAT_COUNT_6 6 16-bit loop counter bit 6
MRW.REPEAT_COUNT_5 5 16-bit loop counter bit 5
MRW.REPEAT_COUNT_4 4 16-bit loop counter bit 4
MRW.REPEAT_COUNT_3 3 16-bit loop counter bit 3
MRW.REPEAT_COUNT_2 2 16-bit loop counter bit 2
MRW.REPEAT_COUNT_1 1 16-bit loop counter bit 1
MRW.REPEAT_COUNT_0 0 16-bit loop counter bit 0
MCW 0xFFDC EEH MAC Control Word
MCW.MP 10 One-bit scaler control
MCW.MS 9 Saturation control
MSW 0xFFDE EFH MAC Unit Status Word
MSW.MV 14 Overflow Flag
MSW.MSL 13 Sticky Limit Flag
MSW.ME 12 MAC Extension Flag
MSW.ME 11 Sticky Overflow Flag
MSW.MC 10 Carry Flag
MSW.MZ 9 Zero Flag
MSW.MN 8 Negative Result
MSW.MAE_7 7 The most significant bits of the 40-bit Accumulator bit 7
MSW.MAE_6 6 The most significant bits of the 40-bit Accumulator bit 6
MSW.MAE_5 5 The most significant bits of the 40-bit Accumulator bit 5
MSW.MAE_4 4 The most significant bits of the 40-bit Accumulator bit 4
MSW.MAE_3 3 The most significant bits of the 40-bit Accumulator bit 3
MSW.MAE_2 2 The most significant bits of the 40-bit Accumulator bit 2
MSW.MAE_1 1 The most significant bits of the 40-bit Accumulator bit 1
MSW.MAE_0 0 The most significant bits of the 40-bit Accumulator bit 0
ASC0_ID 0xFFE2 ASC0 Identification Register
SSC0_ID 0xFFE4 SSC0 Module Identification Register
GPT12E_ID 0xFFE6 GPT Identification Register
CC1_ID 0xFFEC CAPCOM1 Module Identification Register
CC2_ID 0xFFEE CAPCOM2 Module Identification Register
SSC1_ID 0xFFF6 Module Identification Register
RTC_IDH 0xFFFA RTC Identification Register High
; TWINCAN-16BIT
CAN_PISEL 0x200004 TwinCAN Port Input Select Register
CAN_ID 0x200008 CAN Module Identification Register
CAN_ACR 0x200200 Node A Control Register
CAN_ASR 0x200204 Node A Status Register
CAN_AIR 0x200208 Node A Interrupt Pending Register
CAN_ABTRL 0x20020C Node A Bit Timing Register Low
CAN_ABTRH 0x20020E Node A Bit Timing Register High
CAN_AGINP 0x200210 Node A Global Interrupt Node Pointer Register
CAN_AFCRL 0x200214 Node A Frame Counter Register Low
CAN_AFCRH 0x200216 Node A Frame Counter Register High
CAN_AIMRL0 0x200218 Node A INTID Mask Register 0 Low
CAN_AIMRH0 0x20021A Node A INTID Mask Register 0 High
CAN_AIMR4 0x20021C Node A INTID Mask Register 4 Low
CAN_AECNTL 0x200220 Node A Error Counter Register Low
CAN_AECNTH 0x200222 Node A Error Counter Register High
CAN_BCR 0x200240 Node B Control Register
CAN_BSR 0x200244 Node B Status Register
CAN_BIR 0x200248 Node B Interrupt Pending Register
CAN_BBTRL 0x20024C Node B Bit Timing Register Low
CAN_BBTRH 0x20024E Node B Bit Timing Register High
CAN_BGINP 0x200250 Node B Global Interrupt Node Pointer Register
CAN_BFCRL 0x200254 Node B Frame Counter Register Low
CAN_BFCRH 0x200256 Node B Frame Counter Register High
CAN_BIMRL0 0x200258 Node B INTID Mask Register 0 Low
CAN_BIMRH0 0x20025A Node B INTID Mask Register 0 High
CAN_BIMR4 0x20025C Node B INTID Mask Register 4 Low
CAN_BECNTL 0x200260 Node B Error Counter Register Low
CAN_BECNTH 0x200262 Node B Error Counter Register High
CAN_RXIPNDL 0x200284 Receive Interrupt Pending Register Low
CAN_RXIPNDH 0x200286 Receive Interrupt Pending Register High
CAN_TXIPNDL 0x200288 Transmit Interrupt Pending Register Low
CAN_TXIPNDH 0x20028A Transmit Interrupt Pending Register High
CAN_MSGDRL00 0x200300 Message Object 0 Data Register 0 Low
CAN_MSGDRH00 0x200302 Message Object 0 Data Register 0 High
CAN_MSGDRL04 0x200304 Message Object 0 Data Register 4 Low
CAN_MSGDRH04 0x200306 Message Object 0 Data Register 4 High
CAN_MSGARL0 0x200308 Message Object 0 Arbitration Register Low
CAN_MSGARH0 0x20030A Message Object 0 Arbitration Register High
CAN_MSGAMRL0 0x20030C Message Object 0 Arbitration Mask Register Low
CAN_MSGAMRH0 0x20030E Message Object 0 Arbitration Mask Register High
CAN_MSGCTRL0 0x200310 Message Object 0 Message Control Register Low
CAN_MSGCTRH0 0x200312 Message Object 0 Message Control Register High
CAN_MSGCFGL0 0x200314 Message Object 0 Message Configuration Register Low
CAN_MSGCFGH0 0x200316 Message Object 0 Message Configuration Register High
CAN_MSGFGCRL0 0x200318 Message Object 0 FIFO/Gateway Control Register Low
CAN_MSGFGCRH0 0x20031A Message Object 0 FIFO/Gateway Control Register High
CAN_MSGDRL10 0x200320 Message Object 1 Data Register 0 Low
CAN_MSGDRH10 0x200322 Message Object 1 Data Register 0 High
CAN_MSGDRL14 0x200324 Message Object 1 Data Register 4 Low
CAN_MSGDRH14 0x200326 Message Object 1 Data Register 4 High
CAN_MSGARL1 0x200328 Message Object 1 Arbitration Register Low
CAN_MSGARH1 0x20032A Message Object 1 Arbitration Register High
CAN_MSGAMRL1 0x20032C Message Object 1 Arbitration Mask Register Low
CAN_MSGAMRH1 0x20032E Message Object 1 Arbitration Mask Register High
CAN_MSGCTRL1 0x200330 Message Object 1 Message Control Register Low
CAN_MSGCTRH1 0x200332 Message Object 1 Message Control Register High
CAN_MSGCFGL1 0x200334 Message Object 1 Message Configuration Register Low
CAN_MSGCFGH1 0x200336 Message Object 1 Message Configuration Register High
CAN_MSGFGCRL1 0x200338 Message Object 1 FIFO/Gateway Control Register Low
CAN_MSGFGCRH1 0x20033A Message Object 1 FIFO/Gateway Control Register High
CAN_MSGDRL20 0x200340 Message Object 2 Data Register 0 Low
CAN_MSGDRH20 0x200342 Message Object 2 Data Register 0 High
CAN_MSGDRL24 0x200344 Message Object 2 Data Register 4 Low
CAN_MSGDRH24 0x200346 Message Object 2 Data Register 4 High
CAN_MSGARL2 0x200348 Message Object 2 Arbitration Register Low
CAN_MSGARH2 0x20034A Message Object 2 Arbitration Register High
CAN_MSGAMRL2 0x20034C Message Object 2 Arbitration Mask Register Low
CAN_MSGAMRH2 0x20034E Message Object 2 Arbitration Mask Register High
CAN_MSGCTRL2 0x200350 Message Object 2 Message Control Register Low
CAN_MSGCTRH2 0x200352 Message Object 2 Message Control Register High
CAN_MSGCFGL2 0x200354 Message Object 2 Message Configuration Register Low
CAN_MSGCFGH2 0x200356 Message Object 2 Message Configuration Register High
CAN_MSGFGCRL2 0x200358 Message Object 2 FIFO/Gateway Control Register Low
CAN_MSGFGCRH2 0x20035A Message Object 2 FIFO/Gateway Control Register High
CAN_MSGDRL30 0x200360 Message Object 3 Data Register 0 Low
CAN_MSGDRH30 0x200362 Message Object 3 Data Register 0 High
CAN_MSGDRL34 0x200364 Message Object 3 Data Register 4 Low
CAN_MSGDRH34 0x200366 Message Object 3 Data Register 4 High
CAN_MSGARL3 0x200368 Message Object 3 Arbitration Register Low
CAN_MSGARH3 0x20036A Message Object 3 Arbitration Register High
CAN_MSGAMRL3 0x20036C Message Object 3 Arbitration Mask Register Low
CAN_MSGAMRH3 0x20036E Message Object 3 Arbitration Mask Register High
CAN_MSGCTRL3 0x200370 Message Object 3 Message Control Register Low
CAN_MSGCTRH3 0x200372 Message Object 3 Message Control Register High
CAN_MSGCFGL3 0x200374 Message Object 3 Message Configuration Register Low
CAN_MSGCFGH3 0x200376 Message Object 3 Message Configuration Register High
CAN_MSGFGCRL3 0x200378 Message Object 3 FIFO/Gateway Control Register Low
CAN_MSGFGCRH3 0x20037A Message Object 3 FIFO/Gateway Control Register High
CAN_MSGDRL40 0x200380 Message Object 4 Data Register 0 Low
CAN_MSGDRH40 0x200382 Message Object 4 Data Register 0 High
CAN_MSGDRL44 0x200384 Message Object 4 Data Register 4 Low
CAN_MSGDRH44 0x200386 Message Object 4 Data Register 4 High
CAN_MSGARL4 0x200388 Message Object 4 Arbitration Register Low
CAN_MSGARH4 0x20038A Message Object 4 Arbitration Register High
CAN_MSGAMRL4 0x20038C Message Object 4 Arbitration Mask Register Low
CAN_MSGAMRH4 0x20038E Message Object 4 Arbitration Mask Register High
CAN_MSGCTRL4 0x200390 Message Object 4 Message Control Register Low
CAN_MSGCTRH4 0x200392 Message Object 4 Message Control Register High
CAN_MSGCFGL4 0x200394 Message Object 4 Message Configuration Register Low
CAN_MSGCFGH4 0x200396 Message Object 4 Message Configuration Register High
CAN_MSGFGCRL4 0x200398 Message Object 4 FIFO/Gateway Control Register Low
CAN_MSGFGCRH4 0x20039A Message Object 4 FIFO/Gateway Control Register High
CAN_MSGDRL50 0x2003A0 Message Object 5 Data Register 0 Low
CAN_MSGDRH50 0x2003A2 Message Object 5 Data Register 0 High
CAN_MSGDRL54 0x2003A4 Message Object 5 Data Register 4 Low
CAN_MSGDRH54 0x2003A6 Message Object 5 Data Register 4 High
CAN_MSGARL5 0x2003A8 Message Object 5 Arbitration Register Low
CAN_MSGARH5 0x2003AA Message Object 5 Arbitration Register High
CAN_MSGAMRL5 0x2003AC Message Object 5 Arbitration Mask Register Low
CAN_MSGAMRH5 0x2003AE Message Object 5 Arbitration Mask Register High
CAN_MSGCTRL5 0x2003B0 Message Object 5 Message Control Register Low
CAN_MSGCTRH5 0x2003B2 Message Object 5 Message Control Register High
CAN_MSGCFGL5 0x2003B4 Message Object 5 Message Configuration Register Low
CAN_MSGCFGH5 0x2003B6 Message Object 5 Message Configuration Register High
CAN_MSGFGCRL5 0x2003B8 Message Object 5 FIFO/Gateway Control Register Low
CAN_MSGFGCRH5 0x2003BA Message Object 5 FIFO/Gateway Control Register High
CAN_MSGDRL60 0x2003C0 Message Object 6 Data Register 0 Low
CAN_MSGDRH60 0x2003C2 Message Object 6 Data Register 0 High
CAN_MSGDRL64 0x2003C4 Message Object 6 Data Register 4 Low
CAN_MSGDRH64 0x2003C6 Message Object 6 Data Register 4 High
CAN_MSGARL6 0x2003C8 Message Object 6 Arbitration Register Low
CAN_MSGARH6 0x2003CA Message Object 6 Arbitration Register High
CAN_MSGAMRL6 0x2003CC Message Object 6 Arbitration Mask Register Low
CAN_MSGAMRH6 0x2003CE Message Object 6 Arbitration Mask Register High
CAN_MSGCTRL6 0x2003D0 Message Object 6 Message Control Register Low
CAN_MSGCTRH6 0x2003D2 Message Object 6 Message Control Register High
CAN_MSGCFGL6 0x2003D4 Message Object 6 Message Configuration Register Low
CAN_MSGCFGH6 0x2003D6 Message Object 6 Message Configuration Register High
CAN_MSGFGCRL6 0x2003D8 Message Object 6 FIFO/Gateway Control Register Low
CAN_MSGFGCRH6 0x2003DA Message Object 6 FIFO/Gateway Control Register High
CAN_MSGDRL70 0x2003E0 Message Object 7 Data Register 0 Low
CAN_MSGDRH70 0x2003E2 Message Object 7 Data Register 0 High
CAN_MSGDRL74 0x2003E4 Message Object 7 Data Register 4 Low
CAN_MSGDRH74 0x2003E6 Message Object 7 Data Register 4 High
CAN_MSGARL7 0x2003E8 Message Object 7 Arbitration Register Low
CAN_MSGARH7 0x2003EA Message Object 7 Arbitration Register High
CAN_MSGAMRL7 0x2003EC Message Object 7 Arbitration Mask Register Low
CAN_MSGAMRH7 0x2003EE Message Object 7 Arbitration Mask Register High
CAN_MSGCTRL7 0x2003F0 Message Object 7 Message Control Register Low
CAN_MSGCTRH7 0x2003F2 Message Object 7 Message Control Register High
CAN_MSGCFGL7 0x2003F4 Message Object 7 Message Configuration Register Low
CAN_MSGCFGH7 0x2003F6 Message Object 7 Message Configuration Register High
CAN_MSGFGCRL7 0x2003F8 Message Object 7 FIFO/Gateway Control Register Low
CAN_MSGFGCRH7 0x2003FA Message Object 7 FIFO/Gateway Control Register High
CAN_MSGDRL80 0x200400 Message Object 8 Data Register 0 Low
CAN_MSGDRH80 0x200402 Message Object 8 Data Register 0 High
CAN_MSGDRL84 0x200404 Message Object 8 Data Register 4 Low
CAN_MSGDRH84 0x200406 Message Object 8 Data Register 4 High
CAN_MSGARL8 0x200408 Message Object 8 Arbitration Register Low
CAN_MSGARH8 0x20040A Message Object 8 Arbitration Register High
CAN_MSGAMRL8 0x20040C Message Object 8 Arbitration Mask Register Low
CAN_MSGAMRH8 0x20040E Message Object 8 Arbitration Mask Register High
CAN_MSGCTRL8 0x200410 Message Object 8 Message Control Register Low
CAN_MSGCTRH8 0x200412 Message Object 8 Message Control Register High
CAN_MSGCFGL8 0x200414 Message Object 8 Message Configuration Register Low
CAN_MSGCFGH8 0x200416 Message Object 8 Message Configuration Register High
CAN_MSGFGCRL8 0x200418 Message Object 8 FIFO/Gateway Control Register Low
CAN_MSGFGCRH8 0x20041A Message Object 8 FIFO/Gateway Control Register High
CAN_MSGDRL90 0x200420 Message Object 9 Data Register 0 Low
CAN_MSGDRH90 0x200422 Message Object 9 Data Register 0 High
CAN_MSGDRL94 0x200424 Message Object 9 Data Register 4 Low
CAN_MSGDRH94 0x200426 Message Object 9 Data Register 4 High
CAN_MSGARL9 0x200428 Message Object 9 Arbitration Register Low
CAN_MSGARH9 0x20042A Message Object 9 Arbitration Register High
CAN_MSGAMRL9 0x20042C Message Object 9 Arbitration Mask Register Low
CAN_MSGAMRH9 0x20042E Message Object 9 Arbitration Mask Register High
CAN_MSGCTRL9 0x200430 Message Object 9 Message Control Register Low
CAN_MSGCTRH9 0x200432 Message Object 9 Message Control Register High
CAN_MSGCFGL9 0x200434 Message Object 9 Message Configuration Register Low
CAN_MSGCFGH9 0x200436 Message Object 9 Message Configuration Register High
CAN_MSGFGCRL9 0x200438 Message Object 9 FIFO/Gateway Control Register Low
CAN_MSGFGCRH9 0x20043A Message Object 9 FIFO/Gateway Control Register High
CAN_MSGDRL100 0x200440 Message Object 10 Data Register 0 Low
CAN_MSGDRH100 0x200442 Message Object 10 Data Register 0 High
CAN_MSGDRL104 0x200444 Message Object 10 Data Register 4 Low
CAN_MSGDRH104 0x200446 Message Object 10 Data Register 4 High
CAN_MSGARL10 0x200448 Message Object 10 Arbitration Register Low
CAN_MSGARH10 0x20044A Message Object 10 Arbitration Register High
CAN_MSGAMRL10 0x20044C Message Object 10 Arbitration Mask Register Low
CAN_MSGAMRH10 0x20044E Message Object 10 Arbitration Mask Register High
CAN_MSGCTRL10 0x200450 Message Object 10 Message Control Register Low
CAN_MSGCTRH10 0x200452 Message Object 10 Message Control Register High
CAN_MSGCFGL10 0x200454 Message Object 10 Message Configuration Register Low
CAN_MSGCFGH10 0x200456 Message Object 10 Message Configuration Register High
CAN_MSGFGCRL10 0x200458 Message Object 10 FIFO/Gateway Control Register Low
CAN_MSGFGCRH10 0x20045A Message Object 10 FIFO/Gateway Control Register High
CAN_MSGDRL110 0x200460 Message Object 11 Data Register 0 Low
CAN_MSGDRH110 0x200462 Message Object 11 Data Register 0 High
CAN_MSGDRL114 0x200464 Message Object 11 Data Register 4 Low
CAN_MSGDRH114 0x200466 Message Object 11 Data Register 4 High
CAN_MSGARL11 0x200468 Message Object 11 Arbitration Register Low
CAN_MSGARH11 0x20046A Message Object 11 Arbitration Register High
CAN_MSGAMRL11 0x20046C Message Object 11 Arbitration Mask Register Low
CAN_MSGAMRH11 0x20046E Message Object 11 Arbitration Mask Register High
CAN_MSGCTRL11 0x200470 Message Object 11 Message Control Register Low
CAN_MSGCTRH11 0x200472 Message Object 11 Message Control Register High
CAN_MSGCFGL11 0x200474 Message Object 11 Message Configuration Register Low
CAN_MSGCFGH11 0x200476 Message Object 11 Message Configuration Register High
CAN_MSGFGCRL11 0x200478 Message Object 11 FIFO/Gateway Control Register Low
CAN_MSGFGCRH11 0x20047A Message Object 11 FIFO/Gateway Control Register High
CAN_MSGDRL120 0x200480 Message Object 12 Data Register 0 Low
CAN_MSGDRH120 0x200482 Message Object 12 Data Register 0 High
CAN_MSGDRL124 0x200484 Message Object 12 Data Register 4 Low
CAN_MSGDRH124 0x200486 Message Object 12 Data Register 4 High
CAN_MSGARL12 0x200488 Message Object 12 Arbitration Register Low
CAN_MSGARH12 0x20048A Message Object 12 Arbitration Register High
CAN_MSGAMRL12 0x20048C Message Object 12 Arbitration Mask Register Low
CAN_MSGAMRH12 0x20048E Message Object 12 Arbitration Mask Register High
CAN_MSGCTRL12 0x200490 Message Object 12 Message Control Register Low
CAN_MSGCTRH12 0x200492 Message Object 12 Message Control Register High
CAN_MSGCFGL12 0x200494 Message Object 12 Message Configuration Register Low
CAN_MSGCFGH12 0x200496 Message Object 12 Message Configuration Register High
CAN_MSGFGCRL12 0x200498 Message Object 12 FIFO/Gateway Control Register Low
CAN_MSGFGCRH12 0x20049A Message Object 12 FIFO/Gateway Control Register High
CAN_MSGDRL130 0x2004A0 Message Object 13 Data Register 0 Low
CAN_MSGDRH130 0x2004A2 Message Object 13 Data Register 0 High
CAN_MSGDRL134 0x2004A4 Message Object 13 Data Register 4 Low
CAN_MSGDRH134 0x2004A6 Message Object 13 Data Register 4 High
CAN_MSGARL13 0x2004A8 Message Object 13 Arbitration Register Low
CAN_MSGARH13 0x2004AA Message Object 13 Arbitration Register High
CAN_MSGAMRL13 0x2004AC Message Object 13 Arbitration Mask Register Low
CAN_MSGAMRH13 0x2004AE Message Object 13 Arbitration Mask Register High
CAN_MSGCTRL13 0x2004B0 Message Object 13 Message Control Register Low
CAN_MSGCTRH13 0x2004B2 Message Object 13 Message Control Register High
CAN_MSGCFGL13 0x2004B4 Message Object 13 Message Configuration Register Low
CAN_MSGCFGH13 0x2004B6 Message Object 13 Message Configuration Register High
CAN_MSGFGCRL13 0x2004B8 Message Object 13 FIFO/Gateway Control Register Low
CAN_MSGFGCRH13 0x2004BA Message Object 13 FIFO/Gateway Control Register High
CAN_MSGDRL140 0x2004C0 Message Object 14 Data Register 0 Low
CAN_MSGDRH140 0x2004C2 Message Object 14 Data Register 0 High
CAN_MSGDRL144 0x2004C4 Message Object 14 Data Register 4 Low
CAN_MSGDRH144 0x2004C6 Message Object 14 Data Register 4 High
CAN_MSGARL14 0x2004C8 Message Object 14 Arbitration Register Low
CAN_MSGARH14 0x2004CA Message Object 14 Arbitration Register High
CAN_MSGAMRL14 0x2004CC Message Object 14 Arbitration Mask Register Low
CAN_MSGAMRH14 0x2004CE Message Object 14 Arbitration Mask Register High
CAN_MSGCTRL14 0x2004D0 Message Object 14 Message Control Register Low
CAN_MSGCTRH14 0x2004D2 Message Object 14 Message Control Register High
CAN_MSGCFGL14 0x2004D4 Message Object 14 Message Configuration Reg Low
CAN_MSGCFGH14 0x2004D6 Message Object 14 Message Configuration Register High
CAN_MSGFGCRL14 0x2004D8 Message Object 14 FIFO/Gateway Control Register Low
CAN_MSGFGCRH14 0x2004DA Message Object 14 FIFO/Gateway Control Register High
CAN_MSGDRL150 0x2004E0 Message Object 15 Data Register 0 Low
CAN_MSGDRH150 0x2004E2 Message Object 15 Data Register 0 High
CAN_MSGDRL154 0x2004E4 Message Object 15 Data Register 4 Low
CAN_MSGDRH154 0x2004E6 Message Object 15 Data Register 4 High
CAN_MSGARL15 0x2004E8 Message Object 15 Arbitration Register Low
CAN_MSGARH15 0x2004EA Message Object 15 Arbitration Register High
CAN_MSGAMRL15 0x2004EC Message Object 15 Arbitration Mask Register Low
CAN_MSGAMRH15 0x2004EE Message Object 15 Arbitration Mask Register High
CAN_MSGCTRL15 0x2004F0 Message Object 15 Message Control Register Low
CAN_MSGCTRH15 0x2004F2 Message Object 15 Message Control Register High
CAN_MSGCFGL15 0x2004F4 Message Object 15 Message Configuration Register Low
CAN_MSGCFGH15 0x2004F6 Message Object 15 Message Configuration Register High
CAN_MSGFGCRL15 0x2004F8 Message Object 15 FIFO/Gateway Control Register Low
CAN_MSGFGCRH15 0x2004FA Message Object 15 FIFO/Gateway Control Register High
CAN_MSGDRL160 0x200500 Message Object 16 Data Register 0 Low
CAN_MSGDRH160 0x200502 Message Object 16 Data Register 0 High
CAN_MSGDRL164 0x200504 Message Object 16 Data Register 4 Low
CAN_MSGDRH164 0x200506 Message Object 16 Data Register 4 High
CAN_MSGARL16 0x200508 Message Object 16 Arbitration Register Low
CAN_MSGARH16 0x20050A Message Object 16 Arbitration Register High
CAN_MSGAMRL16 0x20050C Message Object 16 Arbitration Mask Register Low
CAN_MSGAMRH16 0x20050E Message Object 16 Arbitration Mask Register High
CAN_MSGCTRL16 0x200510 Message Object 16 Message Control Register Low
CAN_MSGCTRH16 0x200512 Message Object 16 Message Control Register High
CAN_MSGCFGL16 0x200514 Message Object 16 Message Configuration Register Low
CAN_MSGCFGH16 0x200516 Message Object 16 Message Configuration Register High
CAN_MSGFGCRL16 0x200518 Message Object 16 FIFO/Gateway Control Register Low
CAN_MSGFGCRH16 0x20051A Message Object 16 FIFO/Gateway Control Register High
CAN_MSGDRL170 0x200520 Message Object 17 Data Register 0 Low
CAN_MSGDRH170 0x200522 Message Object 17 Data Register 0 High
CAN_MSGDRL174 0x200524 Message Object 17 Data Register 4 Low
CAN_MSGDRH174 0x200526 Message Object 17 Data Register 4 High
CAN_MSGARL17 0x200528 Message Object 17 Arbitration Register Low
CAN_MSGARH17 0x20052A Message Object 17 Arbitration Register High
CAN_MSGAMRL17 0x20052C Message Object 17 Arbitration Mask Register Low
CAN_MSGAMRH17 0x20052E Message Object 17 Arbitration Mask Register High
CAN_MSGCTRL17 0x200530 Message Object 17 Message Control Register Low
CAN_MSGCTRH17 0x200532 Message Object 17 Message Control Register High
CAN_MSGCFGL17 0x200534 Message Object 17 Message Configuration Register Low
CAN_MSGCFGH17 0x200536 Message Object 17 Message Configuration Register High
CAN_MSGFGCRL17 0x200538 Message Object 17 FIFO/Gateway Control Register Low
CAN_MSGFGCRH17 0x20053A Message Object 17 FIFO/Gateway Control Register High
CAN_MSGDRL180 0x200540 Message Object 18 Data Register 0 Low
CAN_MSGDRH180 0x200542 Message Object 18 Data Register 0 High
CAN_MSGDRL184 0x200544 Message Object 18 Data Register 4 Low
CAN_MSGDRH184 0x200546 Message Object 18 Data Register 4 High
CAN_MSGARL18 0x200548 Message Object 18 Arbitration Register Low
CAN_MSGARH18 0x20054A Message Object 18 Arbitration Register High
CAN_MSGAMRL18 0x20054C Message Object 18 Arbitration Mask Register Low
CAN_MSGAMRH18 0x20054E Message Object 18 Arbitration Mask Register High
CAN_MSGCTRL18 0x200550 Message Object 18 Message Control Register Low
CAN_MSGCTRH18 0x200552 Message Object 18 Message Control Register High
CAN_MSGCFGL18 0x200554 Message Object 18 Message Configuration Register Low
CAN_MSGCFGH18 0x200556 Message Object 18 Message Configuration Register High
CAN_MSGFGCRL18 0x200558 Message Object 18 FIFO/Gateway Control Register Low
CAN_MSGFGCRH18 0x20055A Message Object 18 FIFO/Gateway Control Register High
CAN_MSGDRL190 0x200560 Message Object 19 Data Register 0 Low
CAN_MSGDRH190 0x200562 Message Object 19 Data Register 0 High
CAN_MSGDRL194 0x200564 Message Object 19 Data Register 4 Low
CAN_MSGDRH194 0x200566 Message Object 19 Data Register 4 High
CAN_MSGARL19 0x200568 Message Object 19 Arbitration Register Low
CAN_MSGARH19 0x20056A Message Object 19 Arbitration Register High
CAN_MSGAMRL19 0x20056C Message Object 19 Arbitration Mask Register Low
CAN_MSGAMRH19 0x20056E Message Object 19 Arbitration Mask Register High
CAN_MSGCTRL19 0x200570 Message Object 19 Message Control Register Low
CAN_MSGCTRH19 0x200572 Message Object 19 Message Control Register High
CAN_MSGCFGL19 0x200574 Message Object 19 Message Configuration Register Low
CAN_MSGCFGH19 0x200576 Message Object 19 Message Configuration Register High
CAN_MSGFGCRL19 0x200578 Message Object 19 FIFO/Gateway Control Register Low
CAN_MSGFGCRH19 0x20057A Message Object 19 FIFO/Gateway Control Register High
CAN_MSGDRL200 0x200580 Message Object 20 Data Register 0 Low
CAN_MSGDRH200 0x200582 Message Object 20 Data Register 0 High
CAN_MSGDRL204 0x200584 Message Object 20 Data Register 4 Low
CAN_MSGDRH204 0x200586 Message Object 20 Data Register 4 High
CAN_MSGARL20 0x200588 Message Object 20 Arbitration Register Low
CAN_MSGARH20 0x20058A Message Object 20 Arbitration Register High
CAN_MSGAMRL20 0x20058C Message Object 20 Arbitration Mask Register Low
CAN_MSGAMRH20 0x20058E Message Object 20 Arbitration Mask Register High
CAN_MSGCTRL20 0x200590 Message Object 20 Message Control Register Low
CAN_MSGCTRH20 0x200592 Message Object 20 Message Control Register High
CAN_MSGCFGL20 0x200594 Message Object 20 Message Configuration Register Low
CAN_MSGCFGH20 0x200596 Message Object 20 Message Configuration Register High
CAN_MSGFGCRL20 0x200598 Message Object 20 FIFO/Gateway Control Register Low
CAN_MSGFGCRH20 0x20059A Message Object 20 FIFO/Gateway Control Register High
CAN_MSGDRL210 0x2005A0 Message Object 21 Data Register 0 Low
CAN_MSGDRH210 0x2005A2 Message Object 21 Data Register 0 High
CAN_MSGDRL214 0x2005A4 Message Object 21 Data Register 4 Low
CAN_MSGDRH214 0x2005A6 Message Object 21 Data Register 4 High
CAN_MSGARL21 0x2005A8 Message Object 21 Arbitration Register Low
CAN_MSGARH21 0x2005AA Message Object 21 Arbitration Register High
CAN_MSGAMRL21 0x2005AC Message Object 21 Arbitration Mask Register Low
CAN_MSGAMRH21 0x2005AE Message Object 21 Arbitration Mask Register High
CAN_MSGCTRL21 0x2005B0 Message Object 21 Message Control Register Low
CAN_MSGCTRH21 0x2005B2 Message Object 21 Message Control Register High
CAN_MSGCFGL21 0x2005B4 Message Object 21 Message Configuration Register Low
CAN_MSGCFGH21 0x2005B6 Message Object 21 Message Configuration Register High
CAN_MSGFGCRL21 0x2005B8 Message Object 21 FIFO/Gateway Control Register Low
CAN_MSGFGCRH21 0x2005BA Message Object 21 FIFO/Gateway Control Register High
CAN_MSGDRL220 0x2005C0 Message Object 22 Data Register 0 Low
CAN_MSGDRH220 0x2005C2 Message Object 22 Data Register 0 High
CAN_MSGDRL224 0x2005C4 Message Object 22 Data Register 4 Low
CAN_MSGDRH224 0x2005C6 Message Object 22 Data Register 4 High
CAN_MSGARL22 0x2005C8 Message Object 22 Arbitration Register Low
CAN_MSGARH22 0x2005CA Message Object 22 Arbitration Register High
CAN_MSGAMRL22 0x2005CC Message Object 22 Arbitration Mask Register Low
CAN_MSGAMRH22 0x2005CE Message Object 22 Arbitration Mask Register High
CAN_MSGCTRL22 0x2005D0 Message Object 22 Message Control Register Low
CAN_MSGCTRH22 0x2005D2 Message Object 22 Message Control Register High
CAN_MSGCFGL22 0x2005D4 Message Object 22 Message Configuration Register Low
CAN_MSGCFGH22 0x2005D6 Message Object 22 Message Configuration Register High
CAN_MSGFGCRL22 0x2005D8 Message Object 22 FIFO/Gateway Control Register Low
CAN_MSGFGCRH22 0x2005DA Message Object 22 FIFO/Gateway Control Register High
CAN_MSGDRL230 0x2005E0 Message Object 23 Data Register 0 Low
CAN_MSGDRH230 0x2005E2 Message Object 23 Data Register 0 High
CAN_MSGDRL234 0x2005E4 Message Object 23 Data Register 4 Low
CAN_MSGDRH234 0x2005E6 Message Object 23 Data Register 4 High
CAN_MSGARL23 0x2005E8 Message Object 23 Arbitration Register Low
CAN_MSGARH23 0x2005EA Message Object 23 Arbitration Register High
CAN_MSGAMRL23 0x2005EC Message Object 23 Arbitration Mask Register Low
CAN_MSGAMRH23 0x2005EE Message Object 23 Arbitration Mask Register High
CAN_MSGCTRL23 0x2005F0 Message Object 23 Message Control Register Low
CAN_MSGCTRH23 0x2005F2 Message Object 23 Message Control Register High
CAN_MSGCFGL23 0x2005F4 Message Object 23 Message Configuration Register Low
CAN_MSGCFGH23 0x2005F6 Message Object 23 Message Configuration Register High
CAN_MSGFGCRL23 0x2005F8 Message Object 23 FIFO/Gateway Control Register Low
CAN_MSGFGCRH23 0x2005FA Message Object 23 FIFO/Gateway Control Register High
CAN_MSGDRL240 0x200600 Message Object 24 Data Register 0 Low
CAN_MSGDRH240 0x200602 Message Object 24 Data Register 0 High
CAN_MSGDRL244 0x200604 Message Object 24 Data Register 4 Low
CAN_MSGDRH244 0x200606 Message Object 24 Data Register 4 High
CAN_MSGARL24 0x200608 Message Object 24 Arbitration Register Low
CAN_MSGARH24 0x20060A Message Object 24 Arbitration Register High
CAN_MSGAMRL24 0x20060C Message Object 24 Arbitration Mask Register Low
CAN_MSGAMRH24 0x20060E Message Object 24 Arbitration Mask Register High
CAN_MSGCTRL24 0x200610 Message Object 24 Message Control Register Low
CAN_MSGCTRH24 0x200612 Message Object 24 Message Control Register High
CAN_MSGCFGL24 0x200614 Message Object 24 Message Configuration Register Low
CAN_MSGCFGH24 0x200616 Message Object 24 Message Configuration Register High
CAN_MSGFGCRL24 0x200618 Message Object 24 FIFO/Gateway Control Register Low
CAN_MSGFGCRH24 0x20061A Message Object 24 FIFO/Gateway Control Register High
CAN_MSGDRL250 0x200620 Message Object 25 Data Register 0 Low
CAN_MSGDRH250 0x200622 Message Object 25 Data Register 0 High
CAN_MSGDRL254 0x200624 Message Object 25 Data Register 4 Low
CAN_MSGDRH254 0x200626 Message Object 25 Data Register 4 High
CAN_MSGARL25 0x200628 Message Object 25 Arbitration Register Low
CAN_MSGARH25 0x20062A Message Object 25 Arbitration Register High
CAN_MSGAMRL25 0x20062C Message Object 25 Arbitration Mask Register Low
CAN_MSGAMRH25 0x20062E Message Object 25 Arbitration Mask Register High
CAN_MSGCTRL25 0x200630 Message Object 25 Message Control Register Low
CAN_MSGCTRH25 0x200632 Message Object 25 Message Control Register High
CAN_MSGCFGL25 0x200634 Message Object 25 Message Configuration Register Low
CAN_MSGCFGH25 0x200636 Message Object 25 Message Configuration Register High
CAN_MSGFGCRL25 0x200638 Message Object 25 FIFO/Gateway Control Register Low
CAN_MSGFGCRH25 0x20063A Message Object 25 FIFO/Gateway Control Register High
CAN_MSGDRL260 0x200640 Message Object 26 Data Register 0 Low
CAN_MSGDRH260 0x200642 Message Object 26 Data Register 0 High
CAN_MSGDRL264 0x200644 Message Object 26 Data Register 4 Low
CAN_MSGDRH264 0x200646 Message Object 26 Data Register 4 High
CAN_MSGARL26 0x200648 Message Object 26 Arbitration Register Low
CAN_MSGARH26 0x20064A Message Object 26 Arbitration Register High
CAN_MSGAMRL26 0x20064C Message Object 26 Arbitration Mask Register Low
CAN_MSGAMRH26 0x20064E Message Object 26 Arbitration Mask Register High
CAN_MSGCTRL26 0x200650 Message Object 26 Message Control Register Low
CAN_MSGCTRH26 0x200652 Message Object 26 Message Control Register High
CAN_MSGCFGL26 0x200654 Message Object 26 Message Configuration Register Low
CAN_MSGCFGH26 0x200656 Message Object 26 Message Configuration Register High
CAN_MSGFGCRL26 0x200658 Message Object 26 FIFO/Gateway Control Register Low
CAN_MSGFGCRH26 0x20065A Message Object 26 FIFO/Gateway Control Register High
CAN_MSGDRL270 0x200660 Message Object 27 Data Register 0 Low
CAN_MSGDRH270 0x200662 Message Object 27 Data Register 0 High
CAN_MSGDRL274 0x200664 Message Object 27 Data Register 4 Low
CAN_MSGDRH274 0x200666 Message Object 27 Data Register 4 High
CAN_MSGARL27 0x200668 Message Object 27 Arbitration Register Low
CAN_MSGARH27 0x20066A Message Object 27 Arbitration Register High
CAN_MSGAMRL27 0x20066C Message Object 27 Arbitration Mask Register Low
CAN_MSGAMRH27 0x20066E Message Object 27 Arbitration Mask Register High
CAN_MSGCTRL27 0x200670 Message Object 27 Message Control Register Low
CAN_MSGCTRH27 0x200672 Message Object 27 Message Control Register High
CAN_MSGCFGL27 0x200674 Message Object 27 Message Configuration Register Low
CAN_MSGCFGH27 0x200676 Message Object 27 Message Configuration Register High
CAN_MSGFGCRL27 0x200678 Message Object 27 FIFO/Gateway Control Register Low
CAN_MSGFGCRH27 0x20067A Message Object 27 FIFO/Gateway Control Register High
CAN_MSGDRL280 0x200680 Message Object 28 Data Register 0 Low
CAN_MSGDRH280 0x200682 Message Object 28 Data Register 0 High
CAN_MSGDRL284 0x200684 Message Object 28 Data Register 4 Low
CAN_MSGDRH284 0x200686 Message Object 28 Data Register 4 High
CAN_MSGARL28 0x200688 Message Object 28 Arbitration Register Low
CAN_MSGARH28 0x20068A Message Object 28 Arbitration Register High
CAN_MSGAMRL28 0x20068C Message Object 28 Arbitration Mask Register Low
CAN_MSGAMRH28 0x20068E Message Object 28 Arbitration Mask Register High
CAN_MSGCTRL28 0x200690 Message Object 28 Message Control Register Low
CAN_MSGCTRH28 0x200692 Message Object 28 Message Control Register High
CAN_MSGCFGL28 0x200694 Message Object 28 Message Configuration Register Low
CAN_MSGCFGH28 0x200696 Message Object 28 Message Configuration Register High
CAN_MSGFGCRL28 0x200698 Message Object 28 FIFO/Gateway Control Register Low
CAN_MSGFGCRH28 0x20069A Message Object 28 FIFO/Gateway Control Register High
CAN_MSGDRL290 0x2006A0 Message Object 29 Data Register 0 Low
CAN_MSGDRH290 0x2006A2 Message Object 29 Data Register 0 High
CAN_MSGDRL294 0x2006A4 Message Object 29 Data Register 4 Low
CAN_MSGDRH294 0x2006A6 Message Object 29 Data Register 4 High
CAN_MSGARL29 0x2006A8 Message Object 29 Arbitration Register Low
CAN_MSGARH29 0x2006AA Message Object 29 Arbitration Register High
CAN_MSGAMRL29 0x2006AC Message Object 29 Arbitration Mask Register Low
CAN_MSGAMRH29 0x2006AE Message Object 29 Arbitration Mask Register High
CAN_MSGCTRL29 0x2006B0 Message Object 29 Message Control Register Low
CAN_MSGCTRH29 0x2006B2 Message Object 29 Message Control Register High
CAN_MSGCFGL29 0x2006B4 Message Object 29 Message Configuration Register Low
CAN_MSGCFGH29 0x2006B6 Message Object 29 Message Configuration Register High
CAN_MSGFGCRL29 0x2006B8 Message Object 29 FIFO/Gateway Control Register Low
CAN_MSGFGCRH29 0x2006BA Message Object 29 FIFO/Gateway Control Register High
CAN_MSGDRL300 0x2006C0 Message Object 30 Data Register 0 Low
CAN_MSGDRH300 0x2006C2 Message Object 30 Data Register 0 High
CAN_MSGDRL304 0x2006C4 Message Object 30 Data Register 4 Low
CAN_MSGDRH304 0x2006C6 Message Object 30 Data Register 4 High
CAN_MSGARL30 0x2006C8 Message Object 30 Arbitration Register Low
CAN_MSGARH30 0x2006CA Message Object 30 Arbitration Register High
CAN_MSGAMRL30 0x2006CC Message Object 30 Arbitration Mask Register Low
CAN_MSGAMRH30 0x2006CE Message Object 30 Arbitration Mask Register High
CAN_MSGCTRL30 0x2006D0 Message Object 30 Message Control Register Low
CAN_MSGCTRH30 0x2006D2 Message Object 30 Message Control Register High
CAN_MSGCFGL30 0x2006D4 Message Object 30 Message Configuration Register Low
CAN_MSGCFGH30 0x2006D6 Message Object 30 Message Configuration Register High
CAN_MSGFGCRL30 0x2006D8 Message Object 30 FIFO/Gateway Control Register Low
CAN_MSGFGCRH30 0x2006DA Message Object 30 FIFO/Gateway Control Register High
CAN_MSGDRL310 0x2006E0 Message Object 31 Data Register 0 Low
CAN_MSGDRH310 0x2006E2 Message Object 31 Data Register 0 High
CAN_MSGDRL314 0x2006E4 Message Object 31 Data Register 4 Low
CAN_MSGDRH314 0x2006E6 Message Object 31 Data Register 4 High
CAN_MSGARL31 0x2006E8 Message Object 31 Arbitration Register Low
CAN_MSGARH31 0x2006EA Message Object 31 Arbitration Register High
CAN_MSGAMRL31 0x2006EC Message Object 31 Arbitration Mask Register Low
CAN_MSGAMRH31 0x2006EE Message Object 31 Arbitration Mask Register High
CAN_MSGCTRL31 0x2006F0 Message Object 31 Message Control Register Low
CAN_MSGCTRH31 0x2006F2 Message Object 31 Message Control Register High
CAN_MSGCFGL31 0x2006F4 Message Object 31 Message Configuration Register Low
CAN_MSGCFGH31 0x2006F6 Message Object 31 Message Configuration Register High
CAN_MSGFGCRL31 0x2006F8 Message Object 31 FIFO/Gateway Control Register Low
CAN_MSGFGCRH31 0x2006FA Message Object 31 FIFO/Gateway Control Register High
.XC164CS
; xc164_ds_v1_0_2002_03.pdf (Interrupt)
; xc164_umd_system_v1_1_2002_02.pdf (Register, MEMORY MAP (P.69))
; The XC164 is a C164CS-like derivative with extended functionality in a 100-pin package.
; MEMORY MAP
area DATA EXT_MEM 0x0000:0x8000 External Memory
area BSS RESERVED 0x8000:0xC000 Reserved for Internal Data SRAM
area DATA SRAM 0xC000:0xD000 Data SRAM
area BSS RESERVED 0xD000:0xE000
area BSS RESERVED 0xE000:0xE600
area DATA XSFR_1 0xE600:0xEA00 XSFR Area
area BSS RESERVED 0xEA00:0xEC00
area DATA XSFR_2 0xEC00:0xF000 XSFR Area
area DATA E_SFR 0xF000:0xF200
area BSS RESERVED 0xF200:0xF600 Reserved for DPRAM
area DATA DPRAM 0xF600:0xFE00
area DATA SFR 0xFE00:0x10000 SFR Area
; Interrupt and reset vector assignments
entry RESET_ 0x0000 RESET
entry NMITRAP_ 0x0008 Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP_ 0x0010 Stack Overflow (Class A Hardware Traps)
entry STUTRAP_ 0x0018 Stack Underflow (Class A Hardware Traps)
entry SBRKTRAP_ 0x0020 Software Break (Class A Hardware Traps)
entry BTRAP_ 0x0028 BTRAP (Class B Hardware Traps)
entry CC1_CC0IC_ 0x0040 CAPCOM Register 0
entry CC1_CC1IC_ 0x0044 CAPCOM Register 1
entry CC1_CC2IC_ 0x0048 CAPCOM Register 2
entry CC1_CC3IC_ 0x004C CAPCOM Register 3
entry CC1_CC4IC_ 0x0050 CAPCOM Register 4
entry CC1_CC5IC_ 0x0054 CAPCOM Register 5
entry CC1_CC6IC_ 0x0058 CAPCOM Register 6
entry CC1_CC7IC_ 0x005C CAPCOM Register 7
entry CC1_CC8IC_ 0x0060 CAPCOM Register 8
entry CC1_CC9IC_ 0x0064 CAPCOM Register 9
entry CC1_CC10IC_ 0x0068 CAPCOM Register 10
entry CC1_CC11IC_ 0x006C CAPCOM Register 11
entry CC1_CC12IC_ 0x0070 CAPCOM Register 12
entry CC1_CC13IC_ 0x0074 CAPCOM Register 13
entry CC1_CC14IC_ 0x0078 CAPCOM Register 14
entry CC1_CC15IC_ 0x007C CAPCOM Register 15
entry CC1_T0IC_ 0x0080 CAPCOM Timer 0
entry CC1_T1IC_ 0x0084 CAPCOM Timer 1
entry GPT12E_T2IC_ 0x0088 GPT1 Timer 2
entry GPT12E_T3IC_ 0x008C GPT1 Timer 3
entry GPT12E_T4IC_ 0x0090 GPT1 Timer 4
entry GPT12E_T5IC_ 0x0094 GPT2 Timer 5
entry GPT12E_T6IC_ 0x0098 GPT2 Timer 6
entry GPT12E_CRIC_ 0x009C GPT2 CAPREL Reg.
entry ADC_CIC_ 0x00A0 A/D Conversion Compl.
entry ADC_EIC_ 0x00A4 A/D Overrun Error
entry ASC0_TIC_ 0x00A8 ASC0 Transmit
entry ASC0_RIC_ 0x00AC ASC0 Receive
entry ASC0_EIC_ 0x00B0 ASC0 Error
entry SSC0_TIC_ 0x00B4 SSC0 Transmit
entry SSC0_RIC_ 0x00B8 SSC0 Receive
entry SSC0_EIC_ 0x00BC SSC0 Error
entry CC2_CC16IC_ 0x00C0 CAPCOM Register 16
entry CC2_CC17IC_ 0x00C4 CAPCOM Register 17
entry CC2_CC18IC_ 0x00C8 CAPCOM Register 18
entry CC2_CC19IC_ 0x00CC CAPCOM Register 19
entry CC2_CC20IC_ 0x00D0 CAPCOM Register 20
entry CC2_CC21IC_ 0x00D4 CAPCOM Register 21
entry CC2_CC22IC_ 0x00D8 CAPCOM Register 22
entry CC2_CC23IC_ 0x00DC CAPCOM Register 23
entry CC2_CC24IC_ 0x00E0 CAPCOM Register 24
entry CC2_CC25IC_ 0x00E4 CAPCOM Register 25
entry CC2_CC26IC_ 0x00E8 CAPCOM Register 26
entry CC2_CC27IC_ 0x00EC CAPCOM Register 27
entry CC2_CC28IC_ 0x00F0 CAPCOM Register 28
entry CC2_T7IC_ 0x00F4 CAPCOM Timer 7
entry GG2_T8IC_ 0x00F8 CAPCOM Timer 8
entry ASC1_ABIC_ 0x0108 ASC1 Autobaud
entry PLLIC_ 0x010C PLL/OWD
entry CC2_CC29IC_ 0x0110 CAPCOM Register 29
entry CC2_CC30IC_ 0x0114 CAPCOM Register 30
entry CC2_CC31IC_ 0x0118 CAPCOM Register 31
entry ASC0_TBIC_ 0x011C ASC0 Transmit Buffer
entry ASC1_TIC_ 0x0120 ASC1 Transmit 2
entry ASC1_RIC_ 0x0124 ASC1 Receive
entry ASC1_EIC_ 0x0128 ASC1 Error
entry EOPIC_ 0x0130 End of PEC Subch.
entry CCU6_T12IC_ 0x0134 CAPCOM6 Timer T12
entry CCU6_T13IC_ 0x0138 CAPCOM6 Timer T13
entry CCU6_EIC_ 0x013C CAPCOM6 Emergency
entry CCU6_IC_ 0x0140 CAPCOM6
entry SSC1_TIC_ 0x0144 SSC1 Transmit
entry SSC1_RIC_ 0x0148 SSC1 Receive
entry SSC1_EIC_ 0x014C SSC1 Error
entry CAN_0IC_ 0x0150 CAN0
entry CAN_1IC_ 0x0154 CAN1
entry CAN_2IC_ 0x0158 CAN2
entry CAN_3IC_ 0x015C CAN3
entry CAN_4IC_ 0x0164 CAN4
entry CAN_5IC_ 0x0168 CAN5
entry CAN_6IC_ 0x016C CAN6
entry CAN_7IC_ 0x0170 CAN7
entry RTC_IC_ 0x0174 RTC
entry ASC1_TBIC_ 0x0178 ASC1 Transmit Buffer
entry ASC0_ABIC_ 0x017C ASC0 Autobaud
; INPUT/OUTPUT PORTS
; Addressing Modes to Access Word-GPRs (p.100)
; R0 General Purpose Register 0
; R0 General Purpose Register 0
; R1 General Purpose Register 1
; R1 General Purpose Register 1
; R10 General Purpose Register 10
; R10 General Purpose Register 10
; R11 General Purpose Register 11
; R11 General Purpose Register 11
; R12 General Purpose Register 12
; R12 General Purpose Register 12
; R13 General Purpose Register 13
; R13 General Purpose Register 13
; R14 General Purpose Register 14
; R14 General Purpose Register 14
; R15 General Purpose Register 15
; R15 General Purpose Register 15
; R2 General Purpose Register 2
; R2 General Purpose Register 2
; R3 General Purpose Register 3
; R3 General Purpose Register 3
; R4 General Purpose Register 4
; R4 General Purpose Register 4
; R5 General Purpose Register 5
; R5 General Purpose Register 5
; R6 General Purpose Register 6
; R6 General Purpose Register 6
; R7 General Purpose Register 7
; R7 General Purpose Register 7
; R8 General Purpose Register 8
; R8 General Purpose Register 8
; R9 General Purpose Register 9
; R9 General Purpose Register 9
IIC_CFG 0xE600 IIC Configuration Register
IIC_CON 0xE602 IIC Control Register
IIC_ST 0xE604 IIC Status Register
IIC_ADR 0xE606 IIC Address Register
IIC_RTBL 0xE608 IIC Receive/Transmit Buffer Low Register
IIC_RTBH 0xE60A IIC Receive/Transmit Buffer High Register
IIC_ID 0xE60C IIC Module Identification Register
CCU6_PISEL 0xE884 Port Input Select Register
CCU6_ID 0xE888 Module Identification Register
CCU6_T12 0xE890 Timer T12 Counter Register
CCU6_T12PR 0xE892 Timer 12 Period Register
CCU6_T12DTC 0xE894 Dead-Time Control Register for Timer 12
CCU6_CC60R 0xE898 Capture/Compare Register for Channel CC60
CCU6_CC61R 0xE89A Capture/Compare Register for Channel CC61
CCU6_CC62R 0xE89C Capture/Compare Register for Channel CC62
CCU6_CC60SR 0xE8A0 Capture/Compare Shadow Register for Channel 0
CCU6_CC61SR 0xE8A2 Capture/Compare Shadow Register for Channel 1
CCU6_CC62SR 0xE8A4 Capture/Compare Shadow Register for Channel 2
CCU6_TCTR4 0xE8A6 Timer Control Register 4
CCU6_CMPSTAT 0xE8A8 Compare Status Register
CCU6_CMPMODIF 0xE8AA Compare State Modification Register
CCU6_TCTR0 0xE8AC Timer Control Register 0
CCU6_TCTR2 0xE8AE Timer Control Register 2
CCU6_T13 0xE8B0 Timer T13 Counter Register
CCU6_T13PR 0xE8B2 Timer 13 Period Register
CCU6_CC63R 0xE8B4 Compare Register for Channel CC63
CCU6_CC63SR 0xE8B6 Compare Shadow Register for Channel CC63
CCU6_MODCTR 0xE8C0 Modulation Control Register
CCU6_TRPCTR 0xE8C2 Trap Control Register
CCU6_PSLR 0xE8C4 Passive State Level Register
CCU6_T12MSEL 0xE8C6 T12 Capture/Compare Mode Select Register
CCU6_MCMOUTS 0xE8CA Multi-Channel Mode Output Shadow Register
CCU6_MCMOUT 0xE8CC Multi-Channel Mode Output Register
CCU6_MCMCTR 0xE8CE Multi-Channel Mode Control Register
CCU6_IS 0xE8D0 Capture/Compare Interrupt Status Register
CCU6_ISS 0xE8D2 Capture/Compare Interrupt Status Set Register
CCU6_ISR 0xE8D4 Capture/Compare Interrupt Status Reset Register
CCU6_INP 0xE8D6 Capture/Compare Interrupt Node Pointer Register
CCU6_IEN 0xE8D8 Capture/Compare Interrupt Enable Register
SDLM_PISEL 0xE904 SDLM Port Input Select Register
SDLM_ID 0xE908 SDLM Module Identification Register
SDLM_GLOBCON 0xE910 Global Control Register
SDLM_CLKDIV 0xE914 Clock Divider Register
SDLM_TXDELAY 0xE916 Transceiver Delay Register
SDLM_IFRVAL 0xE918 In-Frame Response Value Register
SDLM_BUFFSTAT 0xE91C Buffer Status Register
SDLM_TRANSSTAT 0xE91E Transfer Register
SDLM_BUSSTAT 0xE920 Bus Status Register
SDLM_ERRSTAT 0xE922 Error Status Register
SDLM_BUFFCON 0xE924 Buffer Control Register
SDLM_FLAGRST 0xE928 Flag Reset Register
SDLM_INTCON 0xE92C Interrupt Control Register
SDLM_TXD0 0xE930 Transmit Data Register
SDLM_TXD2 0xE932 Transmit Data Register
SDLM_TXD4 0xE934 Transmit Data Register
SDLM_TXD6 0xE936 Transmit Data Register
SDLM_TXD8 0xE938 Transmit Data Register
SDLM_TXD10 0xE93A Transmit Data Register
SDLM_TXCNT 0xE93C Bus Transmit Byte Counter
SDLM_TXCPU 0xE93E CPU Transmit Byte Counter
SDLM_RXD00 0xE940 Receive Data Register
SDLM_RXD02 0xE942 Receive Data Register
SDLM_RXD04 0xE944 Receive Data Register
SDLM_RXD06 0xE946 Receive Data Register
SDLM_RXD08 0xE948 Receive Data Register
SDLM_RXD010 0xE94A Receive Data Register
SDLM_RXCNT 0xE94C Bus Receive Byte Counter
SDLM_RXCPU 0xE94E CPU Receive Byte Counter
SDLM_RXD10 0xE950 Receive Data Register
SDLM_RXD12 0xE952 Receive Data Register
SDLM_RXD14 0xE954 Receive Data Register
SDLM_RXD16 0xE956 Receive Data Register
SDLM_RXD18 0xE958 Receive Data Register
SDLM_RXD110 0xE95A Receive Data Register
SDLM_RXCNTB 0xE95C Bus Receive Byte Counter Register (on bus side)
SDLM_SOFPTR 0xE960 Start-of-Frame Pointer Register
FINT0CSP 0xEC00 Fast Interrupt Control Register 0
FINT0CSP.EN 15 Fast Interrupt Enable
FINT0CSP.GPX 12 Group Priority Extension
FINT0CSP.ILVL_11 11 Interrupt Priority Level bit 11
FINT0CSP.ILVL_10 10 Interrupt Priority Level bit 10
FINT0CSP.GLVL_9 9 Group Priority Level bit 9
FINT0CSP.GLVL_8 8 Group Priority Level bit 8
FINT0CSP.SEG_7 7 Segment Number of Interrupt Service Routine bit 7
FINT0CSP.SEG_6 6 Segment Number of Interrupt Service Routine bit 6
FINT0CSP.SEG_5 5 Segment Number of Interrupt Service Routine bit 5
FINT0CSP.SEG_4 4 Segment Number of Interrupt Service Routine bit 4
FINT0CSP.SEG_3 3 Segment Number of Interrupt Service Routine bit 3
FINT0CSP.SEG_2 2 Segment Number of Interrupt Service Routine bit 2
FINT0CSP.SEG_1 1 Segment Number of Interrupt Service Routine bit 1
FINT0CSP.SEG_0 0 Segment Number of Interrupt Service Routine bit 0
FINT0ADDR 0xEC02 Fast Interrupt Address Register 0
FINT0ADDR.ADDR_15 15 Address of Interrupt Service Routine bit 15
FINT0ADDR.ADDR_14 14 Address of Interrupt Service Routine bit 14
FINT0ADDR.ADDR_13 13 Address of Interrupt Service Routine bit 13
FINT0ADDR.ADDR_12 12 Address of Interrupt Service Routine bit 12
FINT0ADDR.ADDR_11 11 Address of Interrupt Service Routine bit 11
FINT0ADDR.ADDR_10 10 Address of Interrupt Service Routine bit 10
FINT0ADDR.ADDR_9 9 Address of Interrupt Service Routine bit 9
FINT0ADDR.ADDR_8 8 Address of Interrupt Service Routine bit 8
FINT0ADDR.ADDR_7 7 Address of Interrupt Service Routine bit 7
FINT0ADDR.ADDR_6 6 Address of Interrupt Service Routine bit 6
FINT0ADDR.ADDR_5 5 Address of Interrupt Service Routine bit 5
FINT0ADDR.ADDR_4 4 Address of Interrupt Service Routine bit 4
FINT0ADDR.ADDR_3 3 Address of Interrupt Service Routine bit 3
FINT0ADDR.ADDR_2 2 Address of Interrupt Service Routine bit 2
FINT0ADDR.ADDR_1 1 Address of Interrupt Service Routine bit 1
FINT1CSP 0xEC04 Fast Interrupt Control Register 1
FINT1CSP.EN 15 Fast Interrupt Enable
FINT1CSP.GPX 12 Group Priority Extension
FINT1CSP.ILVL_11 11 Interrupt Priority Level bit 11
FINT1CSP.ILVL_10 10 Interrupt Priority Level bit 10
FINT1CSP.GLVL_9 9 Group Priority Level bit 9
FINT1CSP.GLVL_8 8 Group Priority Level bit 8
FINT1CSP.SEG_7 7 Segment Number of Interrupt Service Routine bit 7
FINT1CSP.SEG_6 6 Segment Number of Interrupt Service Routine bit 6
FINT1CSP.SEG_5 5 Segment Number of Interrupt Service Routine bit 5
FINT1CSP.SEG_4 4 Segment Number of Interrupt Service Routine bit 4
FINT1CSP.SEG_3 3 Segment Number of Interrupt Service Routine bit 3
FINT1CSP.SEG_2 2 Segment Number of Interrupt Service Routine bit 2
FINT1CSP.SEG_1 1 Segment Number of Interrupt Service Routine bit 1
FINT1CSP.SEG_0 0 Segment Number of Interrupt Service Routine bit 0
FINT1ADDR 0xEC06 Fast Interrupt Address Register 1
FINT1ADDR.ADDR_15 15 Address of Interrupt Service Routine bit 15
FINT1ADDR.ADDR_14 14 Address of Interrupt Service Routine bit 14
FINT1ADDR.ADDR_13 13 Address of Interrupt Service Routine bit 13
FINT1ADDR.ADDR_12 12 Address of Interrupt Service Routine bit 12
FINT1ADDR.ADDR_11 11 Address of Interrupt Service Routine bit 11
FINT1ADDR.ADDR_10 10 Address of Interrupt Service Routine bit 10
FINT1ADDR.ADDR_9 9 Address of Interrupt Service Routine bit 9
FINT1ADDR.ADDR_8 8 Address of Interrupt Service Routine bit 8
FINT1ADDR.ADDR_7 7 Address of Interrupt Service Routine bit 7
FINT1ADDR.ADDR_6 6 Address of Interrupt Service Routine bit 6
FINT1ADDR.ADDR_5 5 Address of Interrupt Service Routine bit 5
FINT1ADDR.ADDR_4 4 Address of Interrupt Service Routine bit 4
FINT1ADDR.ADDR_3 3 Address of Interrupt Service Routine bit 3
FINT1ADDR.ADDR_2 2 Address of Interrupt Service Routine bit 2
FINT1ADDR.ADDR_1 1 Address of Interrupt Service Routine bit 1
BNKSEL0 0xEC20 Register Bank Selection Register 0 (??? p.206)
BNKSEL0.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL0.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL0.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL0.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL0.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL0.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL0.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL0.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL0.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL0.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL0.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL0.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL0.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL0.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL0.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL0.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL1 0xEC22 Register Bank Selection Register 1
BNKSEL1.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL1.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL1.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL1.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL1.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL1.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL1.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL1.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL1.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL1.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL1.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL1.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL1.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL1.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL1.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL1.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL2 0xEC24 Register Bank Selection Register 2
BNKSEL2.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL2.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL2.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL2.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL2.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL2.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL2.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL2.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL2.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL2.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL2.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL2.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL2.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL2.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL2.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL2.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL3 0xEC26 Register Bank Selection Register 3
BNKSEL3.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL3.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL3.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL3.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL3.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL3.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL3.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL3.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL3.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL3.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL3.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL3.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL3.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL3.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL3.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL3.GPRSEL0_0 0 Register Bank Selection 0_0
SRCP0 0xEC40 PEC Channel 0 Source Pointer
SRCP0.SRCP0_15 15 Source Pointer Address of Channel 0 bit 15
SRCP0.SRCP0_14 14 Source Pointer Address of Channel 0 bit 14
SRCP0.SRCP0_13 13 Source Pointer Address of Channel 0 bit 13
SRCP0.SRCP0_12 12 Source Pointer Address of Channel 0 bit 12
SRCP0.SRCP0_11 11 Source Pointer Address of Channel 0 bit 11
SRCP0.SRCP0_10 10 Source Pointer Address of Channel 0 bit 10
SRCP0.SRCP0_9 9 Source Pointer Address of Channel 0 bit 9
SRCP0.SRCP0_8 8 Source Pointer Address of Channel 0 bit 8
SRCP0.SRCP0_7 7 Source Pointer Address of Channel 0 bit 7
SRCP0.SRCP0_6 6 Source Pointer Address of Channel 0 bit 6
SRCP0.SRCP0_5 5 Source Pointer Address of Channel 0 bit 5
SRCP0.SRCP0_4 4 Source Pointer Address of Channel 0 bit 4
SRCP0.SRCP0_3 3 Source Pointer Address of Channel 0 bit 3
SRCP0.SRCP0_2 2 Source Pointer Address of Channel 0 bit 2
SRCP0.SRCP0_1 1 Source Pointer Address of Channel 0 bit 1
SRCP0.SRCP0_0 0 Source Pointer Address of Channel 0 bit 0
DSTP0 0xEC42 PEC Channel 0 Destination Pointer
DSTP0.DSTP0_15 15 Destination Pointer Address of Channel 0 bit 15
DSTP0.DSTP0_14 14 Destination Pointer Address of Channel 0 bit 14
DSTP0.DSTP0_13 13 Destination Pointer Address of Channel 0 bit 13
DSTP0.DSTP0_12 12 Destination Pointer Address of Channel 0 bit 12
DSTP0.DSTP0_11 11 Destination Pointer Address of Channel 0 bit 11
DSTP0.DSTP0_10 10 Destination Pointer Address of Channel 0 bit 10
DSTP0.DSTP0_9 9 Destination Pointer Address of Channel 0 bit 9
DSTP0.DSTP0_8 8 Destination Pointer Address of Channel 0 bit 8
DSTP0.DSTP0_7 7 Destination Pointer Address of Channel 0 bit 7
DSTP0.DSTP0_6 6 Destination Pointer Address of Channel 0 bit 6
DSTP0.DSTP0_5 5 Destination Pointer Address of Channel 0 bit 5
DSTP0.DSTP0_4 4 Destination Pointer Address of Channel 0 bit 4
DSTP0.DSTP0_3 3 Destination Pointer Address of Channel 0 bit 3
DSTP0.DSTP0_2 2 Destination Pointer Address of Channel 0 bit 2
DSTP0.DSTP0_1 1 Destination Pointer Address of Channel 0 bit 1
DSTP0.DSTP0_0 0 Destination Pointer Address of Channel 0 bit 0
SRCP1 0xEC44 PEC Channel 1 Source Pointer
SRCP1.SRCP1_15 15 Source Pointer Address of Channel 1 bit 15
SRCP1.SRCP1_14 14 Source Pointer Address of Channel 1 bit 14
SRCP1.SRCP1_13 13 Source Pointer Address of Channel 1 bit 13
SRCP1.SRCP1_12 12 Source Pointer Address of Channel 1 bit 12
SRCP1.SRCP1_11 11 Source Pointer Address of Channel 1 bit 11
SRCP1.SRCP1_10 10 Source Pointer Address of Channel 1 bit 10
SRCP1.SRCP1_9 9 Source Pointer Address of Channel 1 bit 9
SRCP1.SRCP1_8 8 Source Pointer Address of Channel 1 bit 8
SRCP1.SRCP1_7 7 Source Pointer Address of Channel 1 bit 7
SRCP1.SRCP1_6 6 Source Pointer Address of Channel 1 bit 6
SRCP1.SRCP1_5 5 Source Pointer Address of Channel 1 bit 5
SRCP1.SRCP1_4 4 Source Pointer Address of Channel 1 bit 4
SRCP1.SRCP1_3 3 Source Pointer Address of Channel 1 bit 3
SRCP1.SRCP1_2 2 Source Pointer Address of Channel 1 bit 2
SRCP1.SRCP1_1 1 Source Pointer Address of Channel 1 bit 1
SRCP1.SRCP1_0 0 Source Pointer Address of Channel 1 bit 0
DSTP1 0xEC46 PEC Channel 1 Destination Pointer
DSTP1.DSTP1_15 15 Destination Pointer Address of Channel 1 bit 15
DSTP1.DSTP1_14 14 Destination Pointer Address of Channel 1 bit 14
DSTP1.DSTP1_13 13 Destination Pointer Address of Channel 1 bit 13
DSTP1.DSTP1_12 12 Destination Pointer Address of Channel 1 bit 12
DSTP1.DSTP1_11 11 Destination Pointer Address of Channel 1 bit 11
DSTP1.DSTP1_10 10 Destination Pointer Address of Channel 1 bit 10
DSTP1.DSTP1_9 9 Destination Pointer Address of Channel 1 bit 9
DSTP1.DSTP1_8 8 Destination Pointer Address of Channel 1 bit 8
DSTP1.DSTP1_7 7 Destination Pointer Address of Channel 1 bit 7
DSTP1.DSTP1_6 6 Destination Pointer Address of Channel 1 bit 6
DSTP1.DSTP1_5 5 Destination Pointer Address of Channel 1 bit 5
DSTP1.DSTP1_4 4 Destination Pointer Address of Channel 1 bit 4
DSTP1.DSTP1_3 3 Destination Pointer Address of Channel 1 bit 3
DSTP1.DSTP1_2 2 Destination Pointer Address of Channel 1 bit 2
DSTP1.DSTP1_1 1 Destination Pointer Address of Channel 1 bit 1
DSTP1.DSTP1_0 0 Destination Pointer Address of Channel 1 bit 0
SRCP2 0xEC48 PEC Channel 2 Source Pointer
SRCP2.SRCP2_15 15 Source Pointer Address of Channel 2 bit 15
SRCP2.SRCP2_14 14 Source Pointer Address of Channel 2 bit 14
SRCP2.SRCP2_13 13 Source Pointer Address of Channel 2 bit 13
SRCP2.SRCP2_12 12 Source Pointer Address of Channel 2 bit 12
SRCP2.SRCP2_11 11 Source Pointer Address of Channel 2 bit 11
SRCP2.SRCP2_10 10 Source Pointer Address of Channel 2 bit 10
SRCP2.SRCP2_9 9 Source Pointer Address of Channel 2 bit 9
SRCP2.SRCP2_8 8 Source Pointer Address of Channel 2 bit 8
SRCP2.SRCP2_7 7 Source Pointer Address of Channel 2 bit 7
SRCP2.SRCP2_6 6 Source Pointer Address of Channel 2 bit 6
SRCP2.SRCP2_5 5 Source Pointer Address of Channel 2 bit 5
SRCP2.SRCP2_4 4 Source Pointer Address of Channel 2 bit 4
SRCP2.SRCP2_3 3 Source Pointer Address of Channel 2 bit 3
SRCP2.SRCP2_2 2 Source Pointer Address of Channel 2 bit 2
SRCP2.SRCP2_1 1 Source Pointer Address of Channel 2 bit 1
SRCP2.SRCP2_0 0 Source Pointer Address of Channel 2 bit 0
DSTP2 0xEC4A PEC Channel 2 Destination Pointer
DSTP2.DSTP2_15 15 Destination Pointer Address of Channel 2 bit 15
DSTP2.DSTP2_14 14 Destination Pointer Address of Channel 2 bit 14
DSTP2.DSTP2_13 13 Destination Pointer Address of Channel 2 bit 13
DSTP2.DSTP2_12 12 Destination Pointer Address of Channel 2 bit 12
DSTP2.DSTP2_11 11 Destination Pointer Address of Channel 2 bit 11
DSTP2.DSTP2_10 10 Destination Pointer Address of Channel 2 bit 10
DSTP2.DSTP2_9 9 Destination Pointer Address of Channel 2 bit 9
DSTP2.DSTP2_8 8 Destination Pointer Address of Channel 2 bit 8
DSTP2.DSTP2_7 7 Destination Pointer Address of Channel 2 bit 7
DSTP2.DSTP2_6 6 Destination Pointer Address of Channel 2 bit 6
DSTP2.DSTP2_5 5 Destination Pointer Address of Channel 2 bit 5
DSTP2.DSTP2_4 4 Destination Pointer Address of Channel 2 bit 4
DSTP2.DSTP2_3 3 Destination Pointer Address of Channel 2 bit 3
DSTP2.DSTP2_2 2 Destination Pointer Address of Channel 2 bit 2
DSTP2.DSTP2_1 1 Destination Pointer Address of Channel 2 bit 1
DSTP2.DSTP2_0 0 Destination Pointer Address of Channel 2 bit 0
SRCP3 0xEC4C PEC Channel 3 Source Pointer
SRCP3.SRCP3_15 15 Source Pointer Address of Channel 3 bit 15
SRCP3.SRCP3_14 14 Source Pointer Address of Channel 3 bit 14
SRCP3.SRCP3_13 13 Source Pointer Address of Channel 3 bit 13
SRCP3.SRCP3_12 12 Source Pointer Address of Channel 3 bit 12
SRCP3.SRCP3_11 11 Source Pointer Address of Channel 3 bit 11
SRCP3.SRCP3_10 10 Source Pointer Address of Channel 3 bit 10
SRCP3.SRCP3_9 9 Source Pointer Address of Channel 3 bit 9
SRCP3.SRCP3_8 8 Source Pointer Address of Channel 3 bit 8
SRCP3.SRCP3_7 7 Source Pointer Address of Channel 3 bit 7
SRCP3.SRCP3_6 6 Source Pointer Address of Channel 3 bit 6
SRCP3.SRCP3_5 5 Source Pointer Address of Channel 3 bit 5
SRCP3.SRCP3_4 4 Source Pointer Address of Channel 3 bit 4
SRCP3.SRCP3_3 3 Source Pointer Address of Channel 3 bit 3
SRCP3.SRCP3_2 2 Source Pointer Address of Channel 3 bit 2
SRCP3.SRCP3_1 1 Source Pointer Address of Channel 3 bit 1
SRCP3.SRCP3_0 0 Source Pointer Address of Channel 3 bit 0
DSTP3 0xEC4E PEC Channel 3 Destination Pointer
DSTP3.DSTP3_15 15 Destination Pointer Address of Channel 3 bit 15
DSTP3.DSTP3_14 14 Destination Pointer Address of Channel 3 bit 14
DSTP3.DSTP3_13 13 Destination Pointer Address of Channel 3 bit 13
DSTP3.DSTP3_12 12 Destination Pointer Address of Channel 3 bit 12
DSTP3.DSTP3_11 11 Destination Pointer Address of Channel 3 bit 11
DSTP3.DSTP3_10 10 Destination Pointer Address of Channel 3 bit 10
DSTP3.DSTP3_9 9 Destination Pointer Address of Channel 3 bit 9
DSTP3.DSTP3_8 8 Destination Pointer Address of Channel 3 bit 8
DSTP3.DSTP3_7 7 Destination Pointer Address of Channel 3 bit 7
DSTP3.DSTP3_6 6 Destination Pointer Address of Channel 3 bit 6
DSTP3.DSTP3_5 5 Destination Pointer Address of Channel 3 bit 5
DSTP3.DSTP3_4 4 Destination Pointer Address of Channel 3 bit 4
DSTP3.DSTP3_3 3 Destination Pointer Address of Channel 3 bit 3
DSTP3.DSTP3_2 2 Destination Pointer Address of Channel 3 bit 2
DSTP3.DSTP3_1 1 Destination Pointer Address of Channel 3 bit 1
DSTP3.DSTP3_0 0 Destination Pointer Address of Channel 3 bit 0
SRCP4 0xEC50 PEC Channel 4 Source Pointer
SRCP4.SRCP4_15 15 Source Pointer Address of Channel 4 bit 15
SRCP4.SRCP4_14 14 Source Pointer Address of Channel 4 bit 14
SRCP4.SRCP4_13 13 Source Pointer Address of Channel 4 bit 13
SRCP4.SRCP4_12 12 Source Pointer Address of Channel 4 bit 12
SRCP4.SRCP4_11 11 Source Pointer Address of Channel 4 bit 11
SRCP4.SRCP4_10 10 Source Pointer Address of Channel 4 bit 10
SRCP4.SRCP4_9 9 Source Pointer Address of Channel 4 bit 9
SRCP4.SRCP4_8 8 Source Pointer Address of Channel 4 bit 8
SRCP4.SRCP4_7 7 Source Pointer Address of Channel 4 bit 7
SRCP4.SRCP4_6 6 Source Pointer Address of Channel 4 bit 6
SRCP4.SRCP4_5 5 Source Pointer Address of Channel 4 bit 5
SRCP4.SRCP4_4 4 Source Pointer Address of Channel 4 bit 4
SRCP4.SRCP4_3 3 Source Pointer Address of Channel 4 bit 3
SRCP4.SRCP4_2 2 Source Pointer Address of Channel 4 bit 2
SRCP4.SRCP4_1 1 Source Pointer Address of Channel 4 bit 1
SRCP4.SRCP4_0 0 Source Pointer Address of Channel 4 bit 0
DSTP4 0xEC52 PEC Channel 4 Destination Pointer
DSTP4.DSTP4_15 15 Destination Pointer Address of Channel 4 bit 15
DSTP4.DSTP4_14 14 Destination Pointer Address of Channel 4 bit 14
DSTP4.DSTP4_13 13 Destination Pointer Address of Channel 4 bit 13
DSTP4.DSTP4_12 12 Destination Pointer Address of Channel 4 bit 12
DSTP4.DSTP4_11 11 Destination Pointer Address of Channel 4 bit 11
DSTP4.DSTP4_10 10 Destination Pointer Address of Channel 4 bit 10
DSTP4.DSTP4_9 9 Destination Pointer Address of Channel 4 bit 9
DSTP4.DSTP4_8 8 Destination Pointer Address of Channel 4 bit 8
DSTP4.DSTP4_7 7 Destination Pointer Address of Channel 4 bit 7
DSTP4.DSTP4_6 6 Destination Pointer Address of Channel 4 bit 6
DSTP4.DSTP4_5 5 Destination Pointer Address of Channel 4 bit 5
DSTP4.DSTP4_4 4 Destination Pointer Address of Channel 4 bit 4
DSTP4.DSTP4_3 3 Destination Pointer Address of Channel 4 bit 3
DSTP4.DSTP4_2 2 Destination Pointer Address of Channel 4 bit 2
DSTP4.DSTP4_1 1 Destination Pointer Address of Channel 4 bit 1
DSTP4.DSTP4_0 0 Destination Pointer Address of Channel 4 bit 0
SRCP5 0xEC54 PEC Channel 5 Source Pointer
SRCP5.SRCP5_15 15 Source Pointer Address of Channel 5 bit 15
SRCP5.SRCP5_14 14 Source Pointer Address of Channel 5 bit 14
SRCP5.SRCP5_13 13 Source Pointer Address of Channel 5 bit 13
SRCP5.SRCP5_12 12 Source Pointer Address of Channel 5 bit 12
SRCP5.SRCP5_11 11 Source Pointer Address of Channel 5 bit 11
SRCP5.SRCP5_10 10 Source Pointer Address of Channel 5 bit 10
SRCP5.SRCP5_9 9 Source Pointer Address of Channel 5 bit 9
SRCP5.SRCP5_8 8 Source Pointer Address of Channel 5 bit 8
SRCP5.SRCP5_7 7 Source Pointer Address of Channel 5 bit 7
SRCP5.SRCP5_6 6 Source Pointer Address of Channel 5 bit 6
SRCP5.SRCP5_5 5 Source Pointer Address of Channel 5 bit 5
SRCP5.SRCP5_4 4 Source Pointer Address of Channel 5 bit 4
SRCP5.SRCP5_3 3 Source Pointer Address of Channel 5 bit 3
SRCP5.SRCP5_2 2 Source Pointer Address of Channel 5 bit 2
SRCP5.SRCP5_1 1 Source Pointer Address of Channel 5 bit 1
SRCP5.SRCP5_0 0 Source Pointer Address of Channel 5 bit 0
DSTP5 0xEC56 PEC Channel 5 Destination Pointer
DSTP5.DSTP5_15 15 Destination Pointer Address of Channel 5 bit 15
DSTP5.DSTP5_14 14 Destination Pointer Address of Channel 5 bit 14
DSTP5.DSTP5_13 13 Destination Pointer Address of Channel 5 bit 13
DSTP5.DSTP5_12 12 Destination Pointer Address of Channel 5 bit 12
DSTP5.DSTP5_11 11 Destination Pointer Address of Channel 5 bit 11
DSTP5.DSTP5_10 10 Destination Pointer Address of Channel 5 bit 10
DSTP5.DSTP5_9 9 Destination Pointer Address of Channel 5 bit 9
DSTP5.DSTP5_8 8 Destination Pointer Address of Channel 5 bit 8
DSTP5.DSTP5_7 7 Destination Pointer Address of Channel 5 bit 7
DSTP5.DSTP5_6 6 Destination Pointer Address of Channel 5 bit 6
DSTP5.DSTP5_5 5 Destination Pointer Address of Channel 5 bit 5
DSTP5.DSTP5_4 4 Destination Pointer Address of Channel 5 bit 4
DSTP5.DSTP5_3 3 Destination Pointer Address of Channel 5 bit 3
DSTP5.DSTP5_2 2 Destination Pointer Address of Channel 5 bit 2
DSTP5.DSTP5_1 1 Destination Pointer Address of Channel 5 bit 1
DSTP5.DSTP5_0 0 Destination Pointer Address of Channel 5 bit 0
SRCP6 0xEC58 PEC Channel 6 Source Pointer
SRCP6.SRCP6_15 15 Source Pointer Address of Channel 6 bit 15
SRCP6.SRCP6_14 14 Source Pointer Address of Channel 6 bit 14
SRCP6.SRCP6_13 13 Source Pointer Address of Channel 6 bit 13
SRCP6.SRCP6_12 12 Source Pointer Address of Channel 6 bit 12
SRCP6.SRCP6_11 11 Source Pointer Address of Channel 6 bit 11
SRCP6.SRCP6_10 10 Source Pointer Address of Channel 6 bit 10
SRCP6.SRCP6_9 9 Source Pointer Address of Channel 6 bit 9
SRCP6.SRCP6_8 8 Source Pointer Address of Channel 6 bit 8
SRCP6.SRCP6_7 7 Source Pointer Address of Channel 6 bit 7
SRCP6.SRCP6_6 6 Source Pointer Address of Channel 6 bit 6
SRCP6.SRCP6_5 5 Source Pointer Address of Channel 6 bit 5
SRCP6.SRCP6_4 4 Source Pointer Address of Channel 6 bit 4
SRCP6.SRCP6_3 3 Source Pointer Address of Channel 6 bit 3
SRCP6.SRCP6_2 2 Source Pointer Address of Channel 6 bit 2
SRCP6.SRCP6_1 1 Source Pointer Address of Channel 6 bit 1
SRCP6.SRCP6_0 0 Source Pointer Address of Channel 6 bit 0
DSTP6 0xEC5A PEC Channel 6 Destination Pointer
DSTP6.DSTP6_15 15 Destination Pointer Address of Channel 6 bit 15
DSTP6.DSTP6_14 14 Destination Pointer Address of Channel 6 bit 14
DSTP6.DSTP6_13 13 Destination Pointer Address of Channel 6 bit 13
DSTP6.DSTP6_12 12 Destination Pointer Address of Channel 6 bit 12
DSTP6.DSTP6_11 11 Destination Pointer Address of Channel 6 bit 11
DSTP6.DSTP6_10 10 Destination Pointer Address of Channel 6 bit 10
DSTP6.DSTP6_9 9 Destination Pointer Address of Channel 6 bit 9
DSTP6.DSTP6_8 8 Destination Pointer Address of Channel 6 bit 8
DSTP6.DSTP6_7 7 Destination Pointer Address of Channel 6 bit 7
DSTP6.DSTP6_6 6 Destination Pointer Address of Channel 6 bit 6
DSTP6.DSTP6_5 5 Destination Pointer Address of Channel 6 bit 5
DSTP6.DSTP6_4 4 Destination Pointer Address of Channel 6 bit 4
DSTP6.DSTP6_3 3 Destination Pointer Address of Channel 6 bit 3
DSTP6.DSTP6_2 2 Destination Pointer Address of Channel 6 bit 2
DSTP6.DSTP6_1 1 Destination Pointer Address of Channel 6 bit 1
DSTP6.DSTP6_0 0 Destination Pointer Address of Channel 6 bit 0
SRCP7 0xEC5C PEC Channel 7 Source Pointer
SRCP7.SRCP7_15 15 Source Pointer Address of Channel 7 bit 15
SRCP7.SRCP7_14 14 Source Pointer Address of Channel 7 bit 14
SRCP7.SRCP7_13 13 Source Pointer Address of Channel 7 bit 13
SRCP7.SRCP7_12 12 Source Pointer Address of Channel 7 bit 12
SRCP7.SRCP7_11 11 Source Pointer Address of Channel 7 bit 11
SRCP7.SRCP7_10 10 Source Pointer Address of Channel 7 bit 10
SRCP7.SRCP7_9 9 Source Pointer Address of Channel 7 bit 9
SRCP7.SRCP7_8 8 Source Pointer Address of Channel 7 bit 8
SRCP7.SRCP7_7 7 Source Pointer Address of Channel 7 bit 7
SRCP7.SRCP7_6 6 Source Pointer Address of Channel 7 bit 6
SRCP7.SRCP7_5 5 Source Pointer Address of Channel 7 bit 5
SRCP7.SRCP7_4 4 Source Pointer Address of Channel 7 bit 4
SRCP7.SRCP7_3 3 Source Pointer Address of Channel 7 bit 3
SRCP7.SRCP7_2 2 Source Pointer Address of Channel 7 bit 2
SRCP7.SRCP7_1 1 Source Pointer Address of Channel 7 bit 1
SRCP7.SRCP7_0 0 Source Pointer Address of Channel 7 bit 0
DSTP7 0xEC5E PEC Channel 7 Destination
DSTP7.DSTP7_15 15 Destination Pointer Address of Channel 7 bit 15
DSTP7.DSTP7_14 14 Destination Pointer Address of Channel 7 bit 14
DSTP7.DSTP7_13 13 Destination Pointer Address of Channel 7 bit 13
DSTP7.DSTP7_12 12 Destination Pointer Address of Channel 7 bit 12
DSTP7.DSTP7_11 11 Destination Pointer Address of Channel 7 bit 11
DSTP7.DSTP7_10 10 Destination Pointer Address of Channel 7 bit 10
DSTP7.DSTP7_9 9 Destination Pointer Address of Channel 7 bit 9
DSTP7.DSTP7_8 8 Destination Pointer Address of Channel 7 bit 8
DSTP7.DSTP7_7 7 Destination Pointer Address of Channel 7 bit 7
DSTP7.DSTP7_6 6 Destination Pointer Address of Channel 7 bit 6
DSTP7.DSTP7_5 5 Destination Pointer Address of Channel 7 bit 5
DSTP7.DSTP7_4 4 Destination Pointer Address of Channel 7 bit 4
DSTP7.DSTP7_3 3 Destination Pointer Address of Channel 7 bit 3
DSTP7.DSTP7_2 2 Destination Pointer Address of Channel 7 bit 2
DSTP7.DSTP7_1 1 Destination Pointer Address of Channel 7 bit 1
DSTP7.DSTP7_0 0 Destination Pointer Address of Channel 7 bit 0
PECSEG0 0xEC80 PEC Pointer 0 Segment Address Register
PECSEG0.SRCSEG0_15 15 Source Pointer Segment Address of Channel 0 bit 15
PECSEG0.SRCSEG0_14 14 Source Pointer Segment Address of Channel 0 bit 14
PECSEG0.SRCSEG0_13 13 Source Pointer Segment Address of Channel 0 bit 13
PECSEG0.SRCSEG0_12 12 Source Pointer Segment Address of Channel 0 bit 12
PECSEG0.SRCSEG0_11 11 Source Pointer Segment Address of Channel 0 bit 11
PECSEG0.SRCSEG0_10 10 Source Pointer Segment Address of Channel 0 bit 10
PECSEG0.SRCSEG0_9 9 Source Pointer Segment Address of Channel 0 bit 9
PECSEG0.SRCSEG0_8 8 Source Pointer Segment Address of Channel 0 bit 8
PECSEG0.DSTSEG0_7 7 Destination Pointer Segment Address of Channel 0 bit 7
PECSEG0.DSTSEG0_6 6 Destination Pointer Segment Address of Channel 0 bit 6
PECSEG0.DSTSEG0_5 5 Destination Pointer Segment Address of Channel 0 bit 5
PECSEG0.DSTSEG0_4 4 Destination Pointer Segment Address of Channel 0 bit 4
PECSEG0.DSTSEG0_3 3 Destination Pointer Segment Address of Channel 0 bit 3
PECSEG0.DSTSEG0_2 2 Destination Pointer Segment Address of Channel 0 bit 2
PECSEG0.DSTSEG0_1 1 Destination Pointer Segment Address of Channel 0 bit 1
PECSEG0.DSTSEG0_0 0 Destination Pointer Segment Address of Channel 0 bit 0
PECSEG1 0xEC82 PEC Pointer 1 Segment Address Register
PECSEG1.SRCSEG1_15 15 Source Pointer Segment Address of Channel 1 bit 15
PECSEG1.SRCSEG1_14 14 Source Pointer Segment Address of Channel 1 bit 14
PECSEG1.SRCSEG1_13 13 Source Pointer Segment Address of Channel 1 bit 13
PECSEG1.SRCSEG1_12 12 Source Pointer Segment Address of Channel 1 bit 12
PECSEG1.SRCSEG1_11 11 Source Pointer Segment Address of Channel 1 bit 11
PECSEG1.SRCSEG1_10 10 Source Pointer Segment Address of Channel 1 bit 10
PECSEG1.SRCSEG1_9 9 Source Pointer Segment Address of Channel 1 bit 9
PECSEG1.SRCSEG1_8 8 Source Pointer Segment Address of Channel 1 bit 8
PECSEG1.DSTSEG1_7 7 Destination Pointer Segment Address of Channel 1 bit 7
PECSEG1.DSTSEG1_6 6 Destination Pointer Segment Address of Channel 1 bit 6
PECSEG1.DSTSEG1_5 5 Destination Pointer Segment Address of Channel 1 bit 5
PECSEG1.DSTSEG1_4 4 Destination Pointer Segment Address of Channel 1 bit 4
PECSEG1.DSTSEG1_3 3 Destination Pointer Segment Address of Channel 1 bit 3
PECSEG1.DSTSEG1_2 2 Destination Pointer Segment Address of Channel 1 bit 2
PECSEG1.DSTSEG1_1 1 Destination Pointer Segment Address of Channel 1 bit 1
PECSEG1.DSTSEG1_0 0 Destination Pointer Segment Address of Channel 1 bit 0
PECSEG2 0xEC84 PEC Pointer 2 Segment Address Register
PECSEG2.SRCSEG2_15 15 Source Pointer Segment Address of Channel 2 bit 15
PECSEG2.SRCSEG2_14 14 Source Pointer Segment Address of Channel 2 bit 14
PECSEG2.SRCSEG2_13 13 Source Pointer Segment Address of Channel 2 bit 13
PECSEG2.SRCSEG2_12 12 Source Pointer Segment Address of Channel 2 bit 12
PECSEG2.SRCSEG2_11 11 Source Pointer Segment Address of Channel 2 bit 11
PECSEG2.SRCSEG2_10 10 Source Pointer Segment Address of Channel 2 bit 10
PECSEG2.SRCSEG2_9 9 Source Pointer Segment Address of Channel 2 bit 9
PECSEG2.SRCSEG2_8 8 Source Pointer Segment Address of Channel 2 bit 8
PECSEG2.DSTSEG2_7 7 Destination Pointer Segment Address of Channel 2 bit 7
PECSEG2.DSTSEG2_6 6 Destination Pointer Segment Address of Channel 2 bit 6
PECSEG2.DSTSEG2_5 5 Destination Pointer Segment Address of Channel 2 bit 5
PECSEG2.DSTSEG2_4 4 Destination Pointer Segment Address of Channel 2 bit 4
PECSEG2.DSTSEG2_3 3 Destination Pointer Segment Address of Channel 2 bit 3
PECSEG2.DSTSEG2_2 2 Destination Pointer Segment Address of Channel 2 bit 2
PECSEG2.DSTSEG2_1 1 Destination Pointer Segment Address of Channel 2 bit 1
PECSEG2.DSTSEG2_0 0 Destination Pointer Segment Address of Channel 2 bit 0
PECSEG3 0xEC86 PEC Pointer 3 Segment Address Register
PECSEG3.SRCSEG3_15 15 Source Pointer Segment Address of Channel 3 bit 15
PECSEG3.SRCSEG3_14 14 Source Pointer Segment Address of Channel 3 bit 14
PECSEG3.SRCSEG3_13 13 Source Pointer Segment Address of Channel 3 bit 13
PECSEG3.SRCSEG3_12 12 Source Pointer Segment Address of Channel 3 bit 12
PECSEG3.SRCSEG3_11 11 Source Pointer Segment Address of Channel 3 bit 11
PECSEG3.SRCSEG3_10 10 Source Pointer Segment Address of Channel 3 bit 10
PECSEG3.SRCSEG3_9 9 Source Pointer Segment Address of Channel 3 bit 9
PECSEG3.SRCSEG3_8 8 Source Pointer Segment Address of Channel 3 bit 8
PECSEG3.DSTSEG3_7 7 Destination Pointer Segment Address of Channel 3 bit 7
PECSEG3.DSTSEG3_6 6 Destination Pointer Segment Address of Channel 3 bit 6
PECSEG3.DSTSEG3_5 5 Destination Pointer Segment Address of Channel 3 bit 5
PECSEG3.DSTSEG3_4 4 Destination Pointer Segment Address of Channel 3 bit 4
PECSEG3.DSTSEG3_3 3 Destination Pointer Segment Address of Channel 3 bit 3
PECSEG3.DSTSEG3_2 2 Destination Pointer Segment Address of Channel 3 bit 2
PECSEG3.DSTSEG3_1 1 Destination Pointer Segment Address of Channel 3 bit 1
PECSEG3.DSTSEG3_0 0 Destination Pointer Segment Address of Channel 3 bit 0
PECSEG4 0xEC88 PEC Pointer 4 Segment Address Register
PECSEG4.SRCSEG4_15 15 Source Pointer Segment Address of Channel 4 bit 15
PECSEG4.SRCSEG4_14 14 Source Pointer Segment Address of Channel 4 bit 14
PECSEG4.SRCSEG4_13 13 Source Pointer Segment Address of Channel 4 bit 13
PECSEG4.SRCSEG4_12 12 Source Pointer Segment Address of Channel 4 bit 12
PECSEG4.SRCSEG4_11 11 Source Pointer Segment Address of Channel 4 bit 11
PECSEG4.SRCSEG4_10 10 Source Pointer Segment Address of Channel 4 bit 10
PECSEG4.SRCSEG4_9 9 Source Pointer Segment Address of Channel 4 bit 9
PECSEG4.SRCSEG4_8 8 Source Pointer Segment Address of Channel 4 bit 8
PECSEG4.DSTSEG4_7 7 Destination Pointer Segment Address of Channel 4 bit 7
PECSEG4.DSTSEG4_6 6 Destination Pointer Segment Address of Channel 4 bit 6
PECSEG4.DSTSEG4_5 5 Destination Pointer Segment Address of Channel 4 bit 5
PECSEG4.DSTSEG4_4 4 Destination Pointer Segment Address of Channel 4 bit 4
PECSEG4.DSTSEG4_3 3 Destination Pointer Segment Address of Channel 4 bit 3
PECSEG4.DSTSEG4_2 2 Destination Pointer Segment Address of Channel 4 bit 2
PECSEG4.DSTSEG4_1 1 Destination Pointer Segment Address of Channel 4 bit 1
PECSEG4.DSTSEG4_0 0 Destination Pointer Segment Address of Channel 4 bit 0
PECSEG5 0xEC8A PEC Pointer 5 Segment Address Register
PECSEG5.SRCSEG5_15 15 Source Pointer Segment Address of Channel 5 bit 15
PECSEG5.SRCSEG5_14 14 Source Pointer Segment Address of Channel 5 bit 14
PECSEG5.SRCSEG5_13 13 Source Pointer Segment Address of Channel 5 bit 13
PECSEG5.SRCSEG5_12 12 Source Pointer Segment Address of Channel 5 bit 12
PECSEG5.SRCSEG5_11 11 Source Pointer Segment Address of Channel 5 bit 11
PECSEG5.SRCSEG5_10 10 Source Pointer Segment Address of Channel 5 bit 10
PECSEG5.SRCSEG5_9 9 Source Pointer Segment Address of Channel 5 bit 9
PECSEG5.SRCSEG5_8 8 Source Pointer Segment Address of Channel 5 bit 8
PECSEG5.DSTSEG5_7 7 Destination Pointer Segment Address of Channel 5 bit 7
PECSEG5.DSTSEG5_6 6 Destination Pointer Segment Address of Channel 5 bit 6
PECSEG5.DSTSEG5_5 5 Destination Pointer Segment Address of Channel 5 bit 5
PECSEG5.DSTSEG5_4 4 Destination Pointer Segment Address of Channel 5 bit 4
PECSEG5.DSTSEG5_3 3 Destination Pointer Segment Address of Channel 5 bit 3
PECSEG5.DSTSEG5_2 2 Destination Pointer Segment Address of Channel 5 bit 2
PECSEG5.DSTSEG5_1 1 Destination Pointer Segment Address of Channel 5 bit 1
PECSEG5.DSTSEG5_0 0 Destination Pointer Segment Address of Channel 5 bit 0
PECSEG6 0xEC8C PEC Pointer 6 Segment Address Register
PECSEG6.SRCSEG6_15 15 Source Pointer Segment Address of Channel 6 bit 15
PECSEG6.SRCSEG6_14 14 Source Pointer Segment Address of Channel 6 bit 14
PECSEG6.SRCSEG6_13 13 Source Pointer Segment Address of Channel 6 bit 13
PECSEG6.SRCSEG6_12 12 Source Pointer Segment Address of Channel 6 bit 12
PECSEG6.SRCSEG6_11 11 Source Pointer Segment Address of Channel 6 bit 11
PECSEG6.SRCSEG6_10 10 Source Pointer Segment Address of Channel 6 bit 10
PECSEG6.SRCSEG6_9 9 Source Pointer Segment Address of Channel 6 bit 9
PECSEG6.SRCSEG6_8 8 Source Pointer Segment Address of Channel 6 bit 8
PECSEG6.DSTSEG6_7 7 Destination Pointer Segment Address of Channel 6 bit 7
PECSEG6.DSTSEG6_6 6 Destination Pointer Segment Address of Channel 6 bit 6
PECSEG6.DSTSEG6_5 5 Destination Pointer Segment Address of Channel 6 bit 5
PECSEG6.DSTSEG6_4 4 Destination Pointer Segment Address of Channel 6 bit 4
PECSEG6.DSTSEG6_3 3 Destination Pointer Segment Address of Channel 6 bit 3
PECSEG6.DSTSEG6_2 2 Destination Pointer Segment Address of Channel 6 bit 2
PECSEG6.DSTSEG6_1 1 Destination Pointer Segment Address of Channel 6 bit 1
PECSEG6.DSTSEG6_0 0 Destination Pointer Segment Address of Channel 6 bit 0
PECSEG7 0xEC8E PEC Pointer 7 Segment Address Register
PECSEG7.SRCSEG7_15 15 Source Pointer Segment Address of Channel 7 bit 15
PECSEG7.SRCSEG7_14 14 Source Pointer Segment Address of Channel 7 bit 14
PECSEG7.SRCSEG7_13 13 Source Pointer Segment Address of Channel 7 bit 13
PECSEG7.SRCSEG7_12 12 Source Pointer Segment Address of Channel 7 bit 12
PECSEG7.SRCSEG7_11 11 Source Pointer Segment Address of Channel 7 bit 11
PECSEG7.SRCSEG7_10 10 Source Pointer Segment Address of Channel 7 bit 10
PECSEG7.SRCSEG7_9 9 Source Pointer Segment Address of Channel 7 bit 9
PECSEG7.SRCSEG7_8 8 Source Pointer Segment Address of Channel 7 bit 8
PECSEG7.DSTSEG7_7 7 Destination Pointer Segment Address of Channel 7 bit 7
PECSEG7.DSTSEG7_6 6 Destination Pointer Segment Address of Channel 7 bit 6
PECSEG7.DSTSEG7_5 5 Destination Pointer Segment Address of Channel 7 bit 5
PECSEG7.DSTSEG7_4 4 Destination Pointer Segment Address of Channel 7 bit 4
PECSEG7.DSTSEG7_3 3 Destination Pointer Segment Address of Channel 7 bit 3
PECSEG7.DSTSEG7_2 2 Destination Pointer Segment Address of Channel 7 bit 2
PECSEG7.DSTSEG7_1 1 Destination Pointer Segment Address of Channel 7 bit 1
PECSEG7.DSTSEG7_0 0 Destination Pointer Segment Address of Channel 7 bit 0
EBCMOD0 0xEE00 EBC Mode Control Register 0
EBCMOD0.ALEDIS 13 ALE Pin Disable
EBCMOD0.BYTDIS 12 BHE Pin Disable
EBCMOD0.WRCFG 11 Configuration for Pins WR/WRL, BHE/WRH
EBCMOD0.EBCDIS 10 EBC Pins Disable
EBCMOD0.CSPEN_7 7 CSx Pins Enable (only external CSx) bit 7
EBCMOD0.CSPEN_6 6 CSx Pins Enable (only external CSx) bit 6
EBCMOD0.CSPEN_5 5 CSx Pins Enable (only external CSx) bit 5
EBCMOD0.CSPEN_4 4 CSx Pins Enable (only external CSx) bit 4
EBCMOD0.SAPEN_3 3 Segment Address Pins Enable bit 3
EBCMOD0.SAPEN_2 2 Segment Address Pins Enable bit 2
EBCMOD0.SAPEN_1 1 Segment Address Pins Enable bit 1
EBCMOD0.SAPEN_0 0 Segment Address Pins Enable bit 0
EBCMOD1 0xEE02 EBC Mode Control Register 1
EBCMOD1.WRPDIS 7 WR/WRL Pin Disable
EBCMOD1.DHPDIS 6 Data High Port Pins Disable
EBCMOD1.ALPDIS 5 Address Low Pins Disable
EBCMOD1.A0PDIS 4 Address Bit 0 Pin Disable
EBCMOD1.APDIS_3 3 Address Port Pins Disable bit 3
EBCMOD1.APDIS_2 2 Address Port Pins Disable bit 2
EBCMOD1.APDIS_1 1 Address Port Pins Disable bit 1
EBCMOD1.APDIS_0 0 Address Port Pins Disable bit 0
TCONCSMM 0xEE0C Monitor Memory CS Timing Configuration Register
TCONCSSM 0xEE0E Startup Memory CS Timing Configuration Register
TCONCS0 0xEE10 CS0 Timing Configuration Register
TCONCS0.WRPHF_14 14 Write Phase F bit 14
TCONCS0.WRPHF_13 13 Write Phase F bit 13
TCONCS0.RDPHF_12 12 Read Phase F bit 12
TCONCS0.RDPHF_11 11 Read Phase F bit 11
TCONCS0.PHE_10 10 Phase E bit 10
TCONCS0.PHE_9 9 Phase E bit 9
TCONCS0.PHE_8 8 Phase E bit 8
TCONCS0.PHE_7 7 Phase E bit 7
TCONCS0.PHE_6 6 Phase E bit 6
TCONCS0.PHD 5 Phase D
TCONCS0.PHC_4 4 Phase C bit 4
TCONCS0.PHC_3 3 Phase C bit 3
TCONCS0.PHB 2 Phase B
TCONCS0.PHA_1 1 Phase A bit 1
TCONCS0.PHA_0 0 Phase A bit 0
FCONCS0 0xEE12 CS0 Function Configuration Register
FCONCS0.BTYP_5 5 Bus Type Selection bit 5
FCONCS0.BTYP_4 4 Bus Type Selection bit 4
FCONCS0.ENCS 0 Enable Chip Select
TCONCS1 0xEE18 CS1 Timing Configuration Register
TCONCS1.WRPHF_14 14 Write Phase F bit 14
TCONCS1.WRPHF_13 13 Write Phase F bit 13
TCONCS1.RDPHF_12 12 Read Phase F bit 12
TCONCS1.RDPHF_11 11 Read Phase F bit 11
TCONCS1.PHE_10 10 Phase E bit 10
TCONCS1.PHE_9 9 Phase E bit 9
TCONCS1.PHE_8 8 Phase E bit 8
TCONCS1.PHE_7 7 Phase E bit 7
TCONCS1.PHE_6 6 Phase E bit 6
TCONCS1.PHD 5 Phase D
TCONCS1.PHC_4 4 Phase C bit 4
TCONCS1.PHC_3 3 Phase C bit 3
TCONCS1.PHB 2 Phase B
TCONCS1.PHA_1 1 Phase A bit 1
TCONCS1.PHA_0 0 Phase A bit 0
FCONCS1 0xEE1A CS1 Function Configuration Register
FCONCS1.BTYP_5 5 Bus Type Selection bit 5
FCONCS1.BTYP_4 4 Bus Type Selection bit 4
FCONCS1.RDYMOD 2 Ready Mode
FCONCS1.RDYEN 1 Ready enable
FCONCS1.ENCS 0 Enable Chip Select
ADDRSEL1 0xEE1E CS1 Address Range and Size Selection Register
ADDRSEL1.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL1.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL1.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL1.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL1.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL1.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL1.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL1.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL1.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL1.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL1.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL1.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL1.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL1.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL1.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL1.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS2 0xEE20 CS2 Timing Configuration Register
TCONCS2.WRPHF_14 14 Write Phase F bit 14
TCONCS2.WRPHF_13 13 Write Phase F bit 13
TCONCS2.RDPHF_12 12 Read Phase F bit 12
TCONCS2.RDPHF_11 11 Read Phase F bit 11
TCONCS2.PHE_10 10 Phase E bit 10
TCONCS2.PHE_9 9 Phase E bit 9
TCONCS2.PHE_8 8 Phase E bit 8
TCONCS2.PHE_7 7 Phase E bit 7
TCONCS2.PHE_6 6 Phase E bit 6
TCONCS2.PHD 5 Phase D
TCONCS2.PHC_4 4 Phase C bit 4
TCONCS2.PHC_3 3 Phase C bit 3
TCONCS2.PHB 2 Phase B
TCONCS2.PHA_1 1 Phase A bit 1
TCONCS2.PHA_0 0 Phase A bit 0
FCONCS2 0xEE22 CS2 Function Configuration Register
FCONCS2.BTYP_5 5 Bus Type Selection bit 5
FCONCS2.BTYP_4 4 Bus Type Selection bit 4
FCONCS2.RDYMOD 2 Ready Mode
FCONCS2.RDYEN 1 Ready enable
FCONCS2.ENCS 0 Enable Chip Select
ADDRSEL2 0xEE26 CS2 Address Range and Size Selection Register
ADDRSEL2.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL2.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL2.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL2.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL2.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL2.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL2.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL2.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL2.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL2.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL2.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL2.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL2.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL2.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL2.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL2.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS3 0xEE28 CS3 Timing Configuration Register
TCONCS3.WRPHF_14 14 Write Phase F bit 14
TCONCS3.WRPHF_13 13 Write Phase F bit 13
TCONCS3.RDPHF_12 12 Read Phase F bit 12
TCONCS3.RDPHF_11 11 Read Phase F bit 11
TCONCS3.PHE_10 10 Phase E bit 10
TCONCS3.PHE_9 9 Phase E bit 9
TCONCS3.PHE_8 8 Phase E bit 8
TCONCS3.PHE_7 7 Phase E bit 7
TCONCS3.PHE_6 6 Phase E bit 6
TCONCS3.PHD 5 Phase D
TCONCS3.PHC_4 4 Phase C bit 4
TCONCS3.PHC_3 3 Phase C bit 3
TCONCS3.PHB 2 Phase B
TCONCS3.PHA_1 1 Phase A bit 1
TCONCS3.PHA_0 0 Phase A bit 0
FCONCS3 0xEE2A CS3 Function Configuration Register
FCONCS3.BTYP_5 5 Bus Type Selection bit 5
FCONCS3.BTYP_4 4 Bus Type Selection bit 4
FCONCS3.RDYMOD 2 Ready Mode
FCONCS3.RDYEN 1 Ready enable
FCONCS3.ENCS 0 Enable Chip Select
ADDRSEL3 0xEE2E CS3 Address Range and Size Selection Register
ADDRSEL3.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL3.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL3.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL3.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL3.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL3.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL3.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL3.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL3.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL3.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL3.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL3.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL3.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL3.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL3.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL3.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS7 0xEE48 CS7 Timing Configuration Register
TCONCS7.WRPHF_14 14 Write Phase F bit 14
TCONCS7.WRPHF_13 13 Write Phase F bit 13
TCONCS7.RDPHF_12 12 Read Phase F bit 12
TCONCS7.RDPHF_11 11 Read Phase F bit 11
TCONCS7.PHE_10 10 Phase E bit 10
TCONCS7.PHE_9 9 Phase E bit 9
TCONCS7.PHE_8 8 Phase E bit 8
TCONCS7.PHE_7 7 Phase E bit 7
TCONCS7.PHE_6 6 Phase E bit 6
TCONCS7.PHD 5 Phase D
TCONCS7.PHC_4 4 Phase C bit 4
TCONCS7.PHC_3 3 Phase C bit 3
TCONCS7.PHB 2 Phase B
TCONCS7.PHA_1 1 Phase A bit 1
TCONCS7.PHA_0 0 Phase A bit 0
FCONCS7 0xEE4A CS7 Function Configuration Register
FCONCS7.BTYP_5 5 Bus Type Selection bit 5
FCONCS7.BTYP_4 4 Bus Type Selection bit 4
FCONCS7.RDYMOD 2 Ready Mode
FCONCS7.RDYEN 1 Ready enable
FCONCS7.ENCS 0 Enable Chip Select
ADDRSEL7 0xEE4E CS7 Address Range and Size Selection Register
ADDRSEL7.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL7.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL7.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL7.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL7.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL7.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL7.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL7.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL7.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL7.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL7.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL7.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL7.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL7.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL7.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL7.RGSZ_0 0 Address Range Size Selection bit 0
QX0 0xF000 MAC Offset Register
QX0.QX_15 15 Modifiable portion of register QX0 bit 15
QX0.QX_14 14 Modifiable portion of register QX0 bit 14
QX0.QX_13 13 Modifiable portion of register QX0 bit 13
QX0.QX_12 12 Modifiable portion of register QX0 bit 12
QX0.QX_11 11 Modifiable portion of register QX0 bit 11
QX0.QX_10 10 Modifiable portion of register QX0 bit 10
QX0.QX_9 9 Modifiable portion of register QX0 bit 9
QX0.QX_8 8 Modifiable portion of register QX0 bit 8
QX0.QX_7 7 Modifiable portion of register QX0 bit 7
QX0.QX_6 6 Modifiable portion of register QX0 bit 6
QX0.QX_5 5 Modifiable portion of register QX0 bit 5
QX0.QX_4 4 Modifiable portion of register QX0 bit 4
QX0.QX_3 3 Modifiable portion of register QX0 bit 3
QX0.QX_2 2 Modifiable portion of register QX0 bit 2
QX0.QX_1 1 Modifiable portion of register QX0 bit 1
QX1 0xF002 MAC Offset Register
QX1.QX_15 15 Modifiable portion of register QX1 bit 15
QX1.QX_14 14 Modifiable portion of register QX1 bit 14
QX1.QX_13 13 Modifiable portion of register QX1 bit 13
QX1.QX_12 12 Modifiable portion of register QX1 bit 12
QX1.QX_11 11 Modifiable portion of register QX1 bit 11
QX1.QX_10 10 Modifiable portion of register QX1 bit 10
QX1.QX_9 9 Modifiable portion of register QX1 bit 9
QX1.QX_8 8 Modifiable portion of register QX1 bit 8
QX1.QX_7 7 Modifiable portion of register QX1 bit 7
QX1.QX_6 6 Modifiable portion of register QX1 bit 6
QX1.QX_5 5 Modifiable portion of register QX1 bit 5
QX1.QX_4 4 Modifiable portion of register QX1 bit 4
QX1.QX_3 3 Modifiable portion of register QX1 bit 3
QX1.QX_2 2 Modifiable portion of register QX1 bit 2
QX1.QX_1 1 Modifiable portion of register QX1 bit 1
QR0 0xF004 MAC Offset Register
QR0.QR_15 15 Modifiable portion of register QR0 bit 15
QR0.QR_14 14 Modifiable portion of register QR0 bit 14
QR0.QR_13 13 Modifiable portion of register QR0 bit 13
QR0.QR_12 12 Modifiable portion of register QR0 bit 12
QR0.QR_11 11 Modifiable portion of register QR0 bit 11
QR0.QR_10 10 Modifiable portion of register QR0 bit 10
QR0.QR_9 9 Modifiable portion of register QR0 bit 9
QR0.QR_8 8 Modifiable portion of register QR0 bit 8
QR0.QR_7 7 Modifiable portion of register QR0 bit 7
QR0.QR_6 6 Modifiable portion of register QR0 bit 6
QR0.QR_5 5 Modifiable portion of register QR0 bit 5
QR0.QR_4 4 Modifiable portion of register QR0 bit 4
QR0.QR_3 3 Modifiable portion of register QR0 bit 3
QR0.QR_2 2 Modifiable portion of register QR0 bit 2
QR0.QR_1 1 Modifiable portion of register QR0 bit 1
QR1 0xF006 MAC Offset Register
QR1.QR_15 15 Modifiable portion of register QR1 bit 15
QR1.QR_14 14 Modifiable portion of register QR1 bit 14
QR1.QR_13 13 Modifiable portion of register QR1 bit 13
QR1.QR_12 12 Modifiable portion of register QR1 bit 12
QR1.QR_11 11 Modifiable portion of register QR1 bit 11
QR1.QR_10 10 Modifiable portion of register QR1 bit 10
QR1.QR_9 9 Modifiable portion of register QR1 bit 9
QR1.QR_8 8 Modifiable portion of register QR1 bit 8
QR1.QR_7 7 Modifiable portion of register QR1 bit 7
QR1.QR_6 6 Modifiable portion of register QR1 bit 6
QR1.QR_5 5 Modifiable portion of register QR1 bit 5
QR1.QR_4 4 Modifiable portion of register QR1 bit 4
QR1.QR_3 3 Modifiable portion of register QR1 bit 3
QR1.QR_2 2 Modifiable portion of register QR1 bit 2
QR1.QR_1 1 Modifiable portion of register QR1 bit 1
CPUID 0xF00C CPU Identification Register
CC2_T7 0xF050 CAPCOM 2 Timer 7 Register
CC2_T8 0xF052 CAPCOM 2 Timer 8 Register
CC2_T7REL 0xF054 CAPCOM 2 Timer 7 Reload Register
CC2_T8REL 0xF056 CAPCOM 2 Timer 8 Reload Register
SSC1_TB 0xF05A SSC Transmit Buffer (WO)
SSC1_RB 0xF05C SSC Receive Buffer (RO)
SSC1_BR 0xF05E SSC Baudrate Register
CC1_IOC 0xF062 CAPCOM1 IO Control
CC2_IOC 0xF066 CAPCOM2 IO Control
COMDATA 0xF068 Communication Mode data register (Cerberus)
COMDATA.MTR_ADDR_15 15 Set bit 15 of selected
COMDATA.MTR_ADDR_14 14 Set bit 14 of selected
COMDATA.MTR_ADDR_13 13 Set bit 13 of selected
COMDATA.MTR_ADDR_12 12 Set bit 12 of selected
COMDATA.MTR_ADDR_11 11 Set bit 11 of selected
COMDATA.MTR_ADDR_10 10 Set bit 10 of selected
COMDATA.MTR_ADDR_9 9 Set bit 9 of selected
COMDATA.MTR_ADDR_8 8 Set bit 8 of selected
COMDATA.MTR_ADDR_7 7 Set bit 7 of selected
COMDATA.MTR_ADDR_6 6 Set bit 6 of selected
COMDATA.MTR_ADDR_5 5 Set bit 5 of selected
COMDATA.MTR_ADDR_4 4 Set bit 4 of selected
COMDATA.MTR_ADDR_3 3 Set bit 3 of selected
COMDATA.MTR_ADDR_2 2 Set bit 2 of selected
COMDATA.MTR_ADDR_1 1 Set bit 1 of selected
COMDATA.MTR_ADDR_0 0 Set bit 0 of selected
RWDATA 0xF06A RW mode data reg. (Cerberus)
RWDATA.MTR_SELECT_ADDR_9 9
RWDATA.MTR_SELECT_ADDR_8 8
RWDATA.MTR_ADDR_X_7 7 Set bit of selected 7
RWDATA.MTR_ADDR_X_6 6 Set bit of selected 6
RWDATA.MTR_ADDR_X_5 5 Set bit of selected 5
RWDATA.MTR_ADDR_X_4 4 Set bit of selected 4
RWDATA.MTR_ADDR_X_3 3 Set bit of selected 3
RWDATA.MTR_ADDR_X_2 2 Set bit of selected 2
RWDATA.MTR_ADDR_X_1 1 Set bit of selected 1
RWDATA.MTR_ADDR_X_0 0 Set bit of selected 0
IOSR 0xF06C Cerberus Status and Control Register
IOSR.MTR_CTL_P 15 Bit protection (MTR_CTL unchanged/can be changed)
IOSR.MTR_CTL 14 Monitor controlled tracing disabled/enabled
IOSR.CLNT_ON 9 Client not selected/selected
IOSR.DBG_ON 8 No external debugger present / External debugger present
IOSR.COM_SYNC 7 High level sync bit for Communication Mode
IOSR.CW_ACK 6 Write request acknowledge in Communication Mode
IOSR.CWSYNC 5 Write sync bit for Communication Mode
IOSR.CRSYNC 4 Read sync bit for Communication Mode
IOSR.RW_EN_P 3 Bit protection (RW_ENABLE unchanged / RW_ENABLE can be changed)
IOSR.RW_ENABLED 2 Used by user program for security
IOSR.RW_DIS_P 1 Bit protection (RW_DISABLE unchanged / RW_DISABLE can be changed)
IOSR.RW_DISABLE 0 RW mode protection
IDRT 0xF070 Identifier Silicon Correction
IDMEM2 0xF076 IDMEM2 Identifier
IDPROG 0xF078 IDPROG Identifier
IDMEM 0xF07A IDMEM Identifier
IDCHIP 0xF07C IDCHIP Identifier
IDMANUF 0xF07E IDMANUF Identifier
POCON0L 0xF080 Port 0L Output Control Register
POCON0H 0xF082 Port 0H Output Control Register
POCON1L 0xF084 Port 1L Output Control Register
POCON1H 0xF086 Port 1H Output Control Register
POCON3 0xF08A Port 3 Output Control Register
POCON4 0xF08C Port 4 Output Control Register
POCON9 0xF094 Port 9 Output Control Register
ADC_CTR2 0xF09C A/D Converter Control Register 2
ADC_CTR2IN 0xF09E A/D Converter Injection Control Register 2
ADC_DAT2 0xF0A0 A/D Converter Result Register 2
ASC1_TxFCON 0xF0A4 Transmit FIFO Control Register
ASC1_RxFCON 0xF0A6 Receive FIFO Control Register
POCON20 0xF0AA Port 20 Output Control Register
SSC0_TB 0xF0B0 SSC Transmit Buffer (WO)
SSC0_RB 0xF0B2 SSC Receive Buffer (RO)
SSC0_BR 0xF0B4 SSC Baudrate Register
ASC0_ABSTAT 0xF0B8 ASC0 Autobaud Status Register
ASC0_FSTAT 0xF0BA FIFO Status Register
ASC1_ABSTAT 0xF0BC ASC1 Autobaud Status Register
ASC1_FSTAT 0xF0BE FIFO Status Register
SCUSLC 0xF0C0 Security Level Command Reg.
SCUSLC.COMMAND_15 15 Security Level Control Command bit 15
SCUSLC.COMMAND_14 14 Security Level Control Command bit 14
SCUSLC.COMMAND_13 13 Security Level Control Command bit 13
SCUSLC.COMMAND_12 12 Security Level Control Command bit 12
SCUSLC.COMMAND_11 11 Security Level Control Command bit 11
SCUSLC.COMMAND_10 10 Security Level Control Command bit 10
SCUSLC.COMMAND_9 9 Security Level Control Command bit 9
SCUSLC.COMMAND_8 8 Security Level Control Command bit 8
SCUSLC.COMMAND_7 7 Security Level Control Command bit 7
SCUSLC.COMMAND_6 6 Security Level Control Command bit 6
SCUSLC.COMMAND_5 5 Security Level Control Command bit 5
SCUSLC.COMMAND_4 4 Security Level Control Command bit 4
SCUSLC.COMMAND_3 3 Security Level Control Command bit 3
SCUSLC.COMMAND_2 2 Security Level Control Command bit 2
SCUSLC.COMMAND_1 1 Security Level Control Command bit 1
SCUSLC.COMMAND_0 0 Security Level Control Command bit 0
SCUSLS 0xF0C2 Security Level Status Register
SCUSLS.STATE_15 15 Current State of Switching State Machine bit 15
SCUSLS.STATE_14 14 Current State of Switching State Machine bit 14
SCUSLS.STATE_13 13 Current State of Switching State Machine bit 13
SCUSLS.SL_12 12 Security Level bit 12
SCUSLS.SL_11 11 Security Level bit 11
SCUSLS.PASSWORD_7 7 Current Security Control Password bit 7
SCUSLS.PASSWORD_6 6 Current Security Control Password bit 6
SCUSLS.PASSWORD_5 5 Current Security Control Password bit 5
SCUSLS.PASSWORD_4 4 Current Security Control Password bit 4
SCUSLS.PASSWORD_3 3 Current Security Control Password bit 3
SCUSLS.PASSWORD_2 2 Current Security Control Password bit 2
SCUSLS.PASSWORD_1 1 Current Security Control Password bit 1
SCUSLS.PASSWORD_0 0 Current Security Control Password bit 0
ASC0_TxFCON 0xF0C4 Transmit FIFO Control Register
ASC0_RxFCON 0xF0C6 Receive FIFO Control Register
RTC_RELL 0xF0CC RTC Timer Reload Low Register
RTC_RELH 0xF0CE RTC Timer Reload High Register
RTC_T14REL 0xF0D0 Timer 14 Reload Register
RTC_T14 0xF0D2 Timer 14 Register
RTC_RTCL 0xF0D4 RTC Timer Low Register
RTC_RTCH 0xF0D6 RTC Timer High Register
DTIDR 0xF0D8 Task ID register
DTIDR.TASKID_15 15
DTIDR.TASKID_14 14
DTIDR.TASKID_13 13
DTIDR.TASKID_12 12
DTIDR.TASKID_11 11
DTIDR.TASKID_10 10
DTIDR.TASKID_9 9
DTIDR.TASKID_8 8
DTIDR.TASKID_7 7
DTIDR.TASKID_6 6
DTIDR.TASKID_5 5
DTIDR.TASKID_4 4
DTIDR.TASKID_3 3
DTIDR.TASKID_2 2
DTIDR.TASKID_1 1
DTIDR.TASKID_0 0
DCMPSP 0xF0EC Select and Programming Register for DCMPx
DCMPSP.GPR 15 Selects the GPR address format
DCMPSP.SELECT_DCMP_11 11 Select the Comparison Register bit 11
DCMPSP.SELECT_DCMP_10 10 Select the Comparison Register bit 10
DCMPSP.SELECT_DCMP_9 9 Select the Comparison Register bit 9
DCMPSP.SELECT_DCMP_8 8 Select the Comparison Register bit 8
DCMPSP.DCMP_DATA_X_7 7 Sets bit 23 of selected
DCMPSP.DCMP_DATA_X_6 6 Sets bit 22 of selected
DCMPSP.DCMP_DATA_X_5 5 Sets bit 21 of selected
DCMPSP.DCMP_DATA_X_4 4 Sets bit 20 of selected
DCMPSP.DCMP_DATA_X_3 3 Sets bit 19 of selected
DCMPSP.DCMP_DATA_X_2 2 Sets bit 18 of selected
DCMPSP.DCMP_DATA_X_1 1 Sets bit 17 of selected
DCMPSP.DCMP_DATA_X_0 0 Sets bit 16 of selected
DCMPDP 0xF0EE Data programming register for DCMPx
DCMPDP.DCMP_DATA_15 15 Set bit 15 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_14 14 Set bit 14 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_13 13 Set bit 13 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_12 12 Set bit 12 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_11 11 Set bit 11 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_10 10 Set bit 10 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_9 9 Set bit 9 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_8 8 Set bit 8 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_7 7 Set bit 7 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_6 6 Set bit 6 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_5 5 Set bit 5 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_4 4 Set bit 4 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_3 3 Set bit 3 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_2 2 Set bit 2 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_1 1 Set bit 1 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_0 0 Set bit 0 of selected (SELECT_DCMP) DCMP register
DTREVT 0xF0F0 Hardware Trigger Combination Debug Event Control Register
DTREVT.COM_RE 15 Equal and range comparison combination
DTREVT.SELECT_E_14 14 Selects equal/range comparison bit 14
DTREVT.SELECT_E_13 13 Selects equal/range comparison bit 13
DTREVT.MODE_E 12 Controls the complex watch point generation
DTREVT.COM_R_11 11 Select range comparison bit 11
DTREVT.COM_R_10 10 Select range comparison bit 10
DTREVT.MUX_E_9 9 Equal comp. input mux control bit 9
DTREVT.MUX_E_8 8 Equal comp. input mux control bit 8
DTREVT.MUX_R_7 7 Range comparison input mux bit 7
DTREVT.MUX_R_6 6 Range comparison input mux bit 6
DTREVT.ACTIVATE_PIN 5 Identical to ACTIVATE_PIN in DEXEVT
DTREVT.ACT_S_R 4 Activate Second Range for DCMP1 & DCMP2
DTREVT.PERIPHERALS_STOP 3 Identical to PERIPHERALS_STOP in DEXEVT
DTREVT.EVENT_ACTION_1 1 Identical to EVENT_ACTION in DEXEVT bit 1
DTREVT.EVENT_ACTION_0 0 Identical to EVENT_ACTION in DEXEVT bit 0
DEXEVT 0xF0F2 Break Pin Event Control Register
DEXEVT.ACTIVATE_PIN 5
DEXEVT.PERIPHERALS_STOP 3
DEXEVT.EVENT_ACTION_1 1
DEXEVT.EVENT_ACTION_0 0
DSWEVT 0xF0F4 Software Debug Event Control Register
DSWEVT.ACTIVATE_PIN 5
DSWEVT.PERIPHERALS_STOP 3
DSWEVT.EVENT_ACTION_1 1
DSWEVT.EVENT_ACTION_0 0
CMADR 0xF0F8 Call a monitor target address register
CMADR.ADDR_15 15 Bit 15 of the Call A Monitor target address
CMADR.ADDR_14 14 Bit 14 of the Call A Monitor target address
CMADR.ADDR_13 13 Bit 13 of the Call A Monitor target address
CMADR.ADDR_12 12 Bit 12 of the Call A Monitor target address
CMADR.ADDR_11 11 Bit 11 of the Call A Monitor target address
CMADR.ADDR_10 10 Bit 10 of the Call A Monitor target address
CMADR.ADDR_9 9 Bit 9 of the Call A Monitor target address
CMADR.ADDR_8 8 Bit 8 of the Call A Monitor target address
CMADR.ADDR_7 7 Bit 7 of the Call A Monitor target address
CMADR.ADDR_6 6 Bit 6 of the Call A Monitor target address
CMADR.ADDR_5 5 Bit 5 of the Call A Monitor target address
CMADR.ADDR_4 4 Bit 4 of the Call A Monitor target address
CMADR.ADDR_3 3 Bit 3 of the Call A Monitor target address
CMADR.ADDR_2 2 Bit 2 of the Call A Monitor target address
CMADR.ADDR_1 1 Bit 1 of the Call A Monitor target address
CMADR.ADDR_0 0 Bit 0 of the Call A Monitor target address
CMCTR 0xF0FA Call a Monitor Control Register
CMCTR.LEVEL_15 15 Injection Level bit 15
CMCTR.LEVEL_14 14 Injection Level bit 14
CMCTR.LEVEL_13 13 Injection Level bit 13
CMCTR.LEVEL_12 12 Injection Level bit 12
CMCTR.LEVEL_11 11 Injection Level bit 11
CMCTR.BSEL_9 9 Selects the GPR Register Bank bit 9
CMCTR.BSEL_8 8 Selects the GPR Register Bank bit 8
CMCTR.ADDR_7 7 Bit 23 of the Call A Monitor target addres
CMCTR.ADDR_6 6 Bit 22 of the Call A Monitor target addres
CMCTR.ADDR_5 5 Bit 21 of the Call A Monitor target addres
CMCTR.ADDR_4 4 Bit 20 of the Call A Monitor target addres
CMCTR.ADDR_3 3 Bit 19 of the Call A Monitor target addres
CMCTR.ADDR_2 2 Bit 18 of the Call A Monitor target addres
CMCTR.ADDR_1 1 Bit 17 of the Call A Monitor target addres
CMCTR.ADDR_0 0 Bit 16 of the Call A Monitor target addres
DBGSR 0xF0FC Debug Status Register
DBGSR.EVENT_SOURCE_15 15 Reports source of the last debug event bit 15
DBGSR.EVENT_SOURCE_14 14 Reports source of the last debug event bit 14
DBGSR.EVENT_SOURCE_13 13 Reports source of the last debug event bit 13
DBGSR.DBGMOD 11 Specifies the debug mode to be entered in case of a break event
DBGSR.TRGEVT_E_CMP2 10
DBGSR.TRGEVT_E_CMP1 9
DBGSR.TRGEVT_E_CMP0 8
DBGSR.TRGEVT_R_CMP 7
DBGSR.SBRKC 6 Software Break Conflict
DBGSR.CBBM 5 Conditional Break Before Make
DBGSR.OPS 4 OCDS_P_SUSPEND
DBGSR.DEBUG_STATE_3 3 Current debug state bit 3
DBGSR.DEBUG_STATE_2 2 Current debug state bit 2
DBGSR.EXE_ONE_INST 1 Execute one instruction request
DBGSR.DBG_EN 0
IMBCTR 0xF0FE Instruction Memory Block Control Register
IMBCTR.RPA 15 Read Protection Activated
IMBCTR.DDF 9 Disable Data Read from Flas Memory
IMBCTR.DCF 8 Disable Code Fetch from Flas Memory
IMBCTR.WSRAM 2 Wait State Control for programm RAM acsess
IMBCTR.WSFLASH_1 1 Wait States for the Flas Memory bit 1
IMBCTR.WSFLASH_0 0 Wait States for the Flas Memory bit 0
DP0L 0xF100 P0L Direction Control Register
DP0L.P7 7
DP0L.P6 6
DP0L.P5 5
DP0L.P4 4
DP0L.P3 3
DP0L.P2 2
DP0L.P1 1
DP0L.P0 0
DP0H 0xF102 P0H Direction Control Register
DP0H.P7 7
DP0H.P6 6
DP0H.P5 5
DP0H.P4 4
DP0H.P3 3
DP0H.P2 2
DP0H.P1 1
DP0H.P0 0
DP1L 0xF104 P1L Direction Control Register
DP1L.P7 7
DP1L.P6 6
DP1L.P5 5
DP1L.P4 4
DP1L.P3 3
DP1L.P2 2
DP1L.P1 1
DP1L.P0 0
DP1H 0xF106 P1H Direction Control Register
DP1H.P7 7
DP1H.P6 6
DP1H.P5 5
DP1H.P4 4
DP1H.P3 3
DP1H.P2 2
DP1H.P1 1
DP1H.P0 0
RSTCFG 0xF108 Reset Configuration Register
RSTCFG.CLKCFG_15 15 Clock Generation Mode Configuration bit 15
RSTCFG.CLKCFG_14 14 Clock Generation Mode Configuration bit 14
RSTCFG.CLKCFG_13 13 Clock Generation Mode Configuration bit 13
RSTCFG.SALSEL_12 12 Segment Address Line Select bit 12
RSTCFG.SALSEL_11 11 Segment Address Line Select bit 11
RSTCFG.CSSEL_10 10 Chip Select Line Select bit
RSTCFG.CSSEL_9 9 Chip Select Line Select bit
RSTCFG.WRC 8 Write Configuration
RSTCFG.BUSTYP_7 7 External Bus Type bit 7
RSTCFG.BUSTYP_6 6 External Bus Type bit 6
RSTCFG.SMOD_5 5 Special Modes bit 5
RSTCFG.SMOD_4 4 Special Modes bit 4
RSTCFG.SMOD_3 3 Special Modes bit 3
RSTCFG.SMOD_2 2 Special Modes bit 2
RSTCFG.ADP 1 Adapt Mode
RSTCFG.ROC 0 RSTOUT Control
RTC_ISNC 0xF10C RTC Interrupt Sub Node Control Register Low
RTC_ISNC.CNT3IR 9
RTC_ISNC.CNT3IE 8
RTC_ISNC.CNT2IR 7
RTC_ISNC.CNT2IE 6
RTC_ISNC.CNT1IR 5
RTC_ISNC.CNT1IE 4
RTC_ISNC.CNT0IR 3
RTC_ISNC.CNT0IE 2
RTC_ISNC.T14IR 1
RTC_ISNC.T14IE 0
RTC_CONL 0xF110 RTC Control Register Low
RTC_CONL.ACCPOS 15
RTC_CONL.REFCLK 4
RTC_CONL.T14INC 3
RTC_CONL.T14DEC 2
RTC_CONL.PRE 1
RTC_CONL.RUN 0
RTC_CONH 0xF112 RTC Control Register High
ALTSEL0P1H 0xF120 Alternate I/O Source 0 Port P1H
ALTSEL0P1H.P7 7
ALTSEL0P1H.P6 6
ALTSEL0P1H.P5 5
ALTSEL0P1H.P4 4
ALTSEL0P1H.P3 3
ALTSEL0P1H.P2 2
ALTSEL0P1H.P1 1
ALTSEL0P1H.P0 0
ALTSEL0P3 0xF126 Alternate I/O Source Port 3 Selection
ALTSEL0P3.P13 13
ALTSEL0P3.P11 11
ALTSEL0P3.P10 10
ALTSEL0P3.P9 9
ALTSEL0P3.P8 8
ALTSEL0P3.P3 3
ALTSEL0P3.P1 1
ALTSEL1P3 0xF128 Alternate I/O Source 1 Port P3
ALTSEL1P3.P1 1
ALTSEL0P4 0xF12A Alternate I/O Source 0 Port P4
ALTSEL0P4.P7 7
ALTSEL0P4.P6 6
ALTSEL0P1L 0xF130 P1L Alternate Select Register 0
ALTSEL0P1L.P7 7
ALTSEL0P1L.P6 6
ALTSEL0P1L.P5 5
ALTSEL0P1L.P4 4
ALTSEL0P1L.P3 3
ALTSEL0P1L.P2 2
ALTSEL0P1L.P1 1
ALTSEL0P1L.P0 0
ALTSEL1P4 0xF136 Alternate I/O Source 1 Port P4
ALTSEL1P4.P7 7
ALTSEL0P9 0xF138 Alternate I/O Source 0 Port P9
ALTSEL0P9.P5 5
ALTSEL0P9.P4 4
ALTSEL0P9.P3 3
ALTSEL0P9.P2 2
ALTSEL0P9.P1 1
ALTSEL0P9.P0 0
ALTSEL1P9 0xF13A Alternate I/O Source 1 Port P9
ALTSEL1P9.P5 5
ALTSEL1P9.P4 4
ALTSEL1P9.P3 3
ALTSEL1P9.P2 2
ALTSEL1P9.P1 1
ALTSEL1P9.P0 0
CCU6_IC 0xF140 CAPCOM 6 Interrupt Control Register
CCU6_IC.GPX 8 Group Priority Extension
CCU6_IC.IR 7 Interrupt Request Flag
CCU6_IC.IE 6 Interrupt Enable Control Bit
CCU6_IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_IC.GLVL_1 1 Group Priority Level bit 1
CCU6_IC.GLVL_0 0 Group Priority Level bit 0
CAN_1IC 0xF142 CAN Mode 1 Interrupt Control register
CAN_1IC.GPX 8 Group Priority Extension
CAN_1IC.IR 7 Interrupt Request Flag
CAN_1IC.IE 6 Interrupt Enable Control Bit
CAN_1IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_1IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_1IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_1IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_1IC.GLVL_1 1 Group Priority Level bit 1
CAN_1IC.GLVL_0 0 Group Priority Level bit 0
CAN_2IC 0xF144 CAN Mode 2 Interrupt Control register
CAN_2IC.GPX 8 Group Priority Extension
CAN_2IC.IR 7 Interrupt Request Flag
CAN_2IC.IE 6 Interrupt Enable Control Bit
CAN_2IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_2IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_2IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_2IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_2IC.GLVL_1 1 Group Priority Level bit 1
CAN_2IC.GLVL_0 0 Group Priority Level bit 0
CAN_3IC 0xF146 CAN Mode 3 Interrupt Control register
CAN_3IC.GPX 8 Group Priority Extension
CAN_3IC.IR 7 Interrupt Request Flag
CAN_3IC.IE 6 Interrupt Enable Control Bit
CAN_3IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_3IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_3IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_3IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_3IC.GLVL_1 1 Group Priority Level bit 1
CAN_3IC.GLVL_0 0 Group Priority Level bit 0
CAN_4IC 0xF148 CAN Mode 4 Interrupt Control register
CAN_4IC.GPX 8 Group Priority Extension
CAN_4IC.IR 7 Interrupt Request Flag
CAN_4IC.IE 6 Interrupt Enable Control Bit
CAN_4IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_4IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_4IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_4IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_4IC.GLVL_1 1 Group Priority Level bit 1
CAN_4IC.GLVL_0 0 Group Priority Level bit 0
CAN_5IC 0xF14A CAN Mode 5 Interrupt Control register
CAN_5IC.GPX 8 Group Priority Extension
CAN_5IC.IR 7 Interrupt Request Flag
CAN_5IC.IE 6 Interrupt Enable Control Bit
CAN_5IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_5IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_5IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_5IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_5IC.GLVL_1 1 Group Priority Level bit 1
CAN_5IC.GLVL_0 0 Group Priority Level bit 0
CAN_6IC 0xF14C CAN Mode 6 Interrupt Control register
CAN_6IC.GPX 8 Group Priority Extension
CAN_6IC.IR 7 Interrupt Request Flag
CAN_6IC.IE 6 Interrupt Enable Control Bit
CAN_6IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_6IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_6IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_6IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_6IC.GLVL_1 1 Group Priority Level bit 1
CAN_6IC.GLVL_0 0 Group Priority Level bit 0
CAN_7IC 0xF14E CAN Mode 7 Interrupt Control register
CAN_7IC.GPX 8 Group Priority Extension
CAN_7IC.IR 7 Interrupt Request Flag
CAN_7IC.IE 6 Interrupt Enable Control Bit
CAN_7IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_7IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_7IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_7IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_7IC.GLVL_1 1 Group Priority Level bit 1
CAN_7IC.GLVL_0 0 Group Priority Level bit 0
ASC1_TBIC 0xF150 ASC1 Transmit Buffer Interrupt Control Register
ASC1_TBIC.GPX 8 Group Priority Extension
ASC1_TBIC.IR 7 Interrupt Request Flag
ASC1_TBIC.IE 6 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_TBIC.GLVL_1 1 Group Priority Level bit 1
ASC1_TBIC.GLVL_0 0 Group Priority Level bit 0
ASC0_ABIC 0xF15C ASC0 Autobaud Interrupt Control Register
ASC0_ABIC.GPX 8 Group Priority Extension
ASC0_ABIC.IR 7 Interrupt Request Flag
ASC0_ABIC.IE 6 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_ABIC.GLVL_1 1 Group Priority Level bit 1
ASC0_ABIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC16IC 0xF160 CAPCOM Channel 16 Interrupt Control Register
CC2_CC16IC.GPX 8 Group Priority Extension
CC2_CC16IC.IR 7 Interrupt Request Flag
CC2_CC16IC.IE 6 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC16IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC16IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC17IC 0xF162 CAPCOM Channel 17 Interrupt Control Register
CC2_CC17IC.GPX 8 Group Priority Extension
CC2_CC17IC.IR 7 Interrupt Request Flag
CC2_CC17IC.IE 6 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC17IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC17IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC18IC 0xF164 CAPCOM Channel 18 Interrupt Control Register
CC2_CC18IC.GPX 8 Group Priority Extension
CC2_CC18IC.IR 7 Interrupt Request Flag
CC2_CC18IC.IE 6 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC18IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC18IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC19IC 0xF166 CAPCOM Channel 19 Interrupt Control Register
CC2_CC19IC.GPX 8 Group Priority Extension
CC2_CC19IC.IR 7 Interrupt Request Flag
CC2_CC19IC.IE 6 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC19IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC19IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC20IC 0xF168 CAPCOM Channel 20 Interrupt Control Register
CC2_CC20IC.GPX 8 Group Priority Extension
CC2_CC20IC.IR 7 Interrupt Request Flag
CC2_CC20IC.IE 6 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC20IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC20IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC21IC 0xF16A CAPCOM Channel 21 Interrupt Control Register
CC2_CC21IC.GPX 8 Group Priority Extension
CC2_CC21IC.IR 7 Interrupt Request Flag
CC2_CC21IC.IE 6 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC21IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC21IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC22IC 0xF16C CAPCOM Channel 22 Interrupt Control Register
CC2_CC22IC.GPX 8 Group Priority Extension
CC2_CC22IC.IR 7 Interrupt Request Flag
CC2_CC22IC.IE 6 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC22IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC22IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC23IC 0xF16E CAPCOM Channel 23 Interrupt Control Register
CC2_CC23IC.GPX 8 Group Priority Extension
CC2_CC23IC.IR 7 Interrupt Request Flag
CC2_CC23IC.IE 6 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC23IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC23IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC24IC 0xF170 CAPCOM Channel 24 Interrupt Control Register
CC2_CC24IC.GPX 8 Group Priority Extension
CC2_CC24IC.IR 7 Interrupt Request Flag
CC2_CC24IC.IE 6 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC24IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC24IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC25IC 0xF172 CAPCOM Channel 25 Interrupt Control Register
CC2_CC25IC.GPX 8 Group Priority Extension
CC2_CC25IC.IR 7 Interrupt Request Flag
CC2_CC25IC.IE 6 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC25IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC25IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC26IC 0xF174 CAPCOM Channel 26 Interrupt Control Register
CC2_CC26IC.GPX 8 Group Priority Extension
CC2_CC26IC.IR 7 Interrupt Request Flag
CC2_CC26IC.IE 6 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC26IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC26IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC27IC 0xF176 CAPCOM Channel 27 Interrupt Control Register
CC2_CC27IC.GPX 8 Group Priority Extension
CC2_CC27IC.IR 7 Interrupt Request Flag
CC2_CC27IC.IE 6 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC27IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC27IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC28IC 0xF178 CAPCOM Channel 28 Interrupt Control Register
CC2_CC28IC.GPX 8 Group Priority Extension
CC2_CC28IC.IR 7 Interrupt Request Flag
CC2_CC28IC.IE 6 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC28IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC28IC.GLVL_0 0 Group Priority Level bit 0
CC2_T7IC 0xF17A CAPCOM 2 Timer 7 Interrupt Control Register
CC2_T7IC.GPX 8 Group Priority Extension
CC2_T7IC.IR 7 Interrupt Request Flag
CC2_T7IC.IE 6 Interrupt Enable Control Bit
CC2_T7IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_T7IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_T7IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_T7IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_T7IC.GLVL_1 1 Group Priority Level bit 1
CC2_T7IC.GLVL_0 0 Group Priority Level bit 0
CC2_T8IC 0xF17C CAPCOM 2 Timer 8 Interrupt Control Register
CC2_T8IC.GPX 8 Group Priority Extension
CC2_T8IC.IR 7 Interrupt Request Flag
CC2_T8IC.IE 6 Interrupt Enable Control Bit
CC2_T8IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_T8IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_T8IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_T8IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_T8IC.GLVL_1 1 Group Priority Level bit 1
CC2_T8IC.GLVL_0 0 Group Priority Level bit 0
EOPIC 0xF180 End of PEC Interrupt Control Register
EOPIC.GPX 8 Group Priority Extension
EOPIC.IR 7 Interrupt Request Flag
EOPIC.IE 6 Interrupt Enable Control Bit
EOPIC.ILVL_5 5 Interrupt Enable Control Bit
EOPIC.ILVL_4 4 Interrupt Enable Control Bit
EOPIC.ILVL_3 3 Interrupt Enable Control Bit
EOPIC.ILVL_2 2 Interrupt Enable Control Bit
EOPIC.GLVL_1 1 Group Priority Level bit 1
EOPIC.GLVL_0 0 Group Priority Level bit 0
ASC1_TIC 0xF182 ASC1 Transmit Interrupt Control Register
ASC1_TIC.GPX 8 Group Priority Extension
ASC1_TIC.IR 7 Interrupt Request Flag
ASC1_TIC.IE 6 Interrupt Enable Control Bit
ASC1_TIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_TIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_TIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_TIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_TIC.GLVL_1 1 Group Priority Level bit 1
ASC1_TIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC29IC 0xF184 CAPCOM Channel 29 Interrupt Control Register
CC2_CC29IC.GPX 8 Group Priority Extension
CC2_CC29IC.IR 7 Interrupt Request Flag
CC2_CC29IC.IE 6 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC29IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC29IC.GLVL_0 0 Group Priority Level bit 0
CCU6_EIC 0xF188 CAPCOM 6 Emergency Interrupt Control Register
CCU6_EIC.GPX 8 Group Priority Extension
CCU6_EIC.IR 7 Interrupt Request Flag
CCU6_EIC.IE 6 Interrupt Enable Control Bit
CCU6_EIC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_EIC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_EIC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_EIC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_EIC.GLVL_1 1 Group Priority Level bit 1
CCU6_EIC.GLVL_0 0 Group Priority Level bit 0
ASC1_RIC 0xF18A ASC1 Receive Interrupt Control Register
ASC1_RIC.GPX 8 Group Priority Extension
ASC1_RIC.IR 7 Interrupt Request Flag
ASC1_RIC.IE 6 Interrupt Enable Control Bit
ASC1_RIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_RIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_RIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_RIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_RIC.GLVL_1 1 Group Priority Level bit 1
ASC1_RIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC30IC 0xF18C CAPCOM Channel 30 Interrupt Control Register
CC2_CC30IC.GPX 8 Group Priority Extension
CC2_CC30IC.IR 7 Interrupt Request Flag
CC2_CC30IC.IE 6 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC30IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC30IC.GLVL_0 0 Group Priority Level bit 0
CCU6_T12IC 0xF190 CAPCOM 6 Timer 12 Interrupt Control Register
CCU6_T12IC.GPX 8 Group Priority Extension
CCU6_T12IC.IR 7 Interrupt Request Flag
CCU6_T12IC.IE 6 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_T12IC.GLVL_1 1 Group Priority Level bit 1
CCU6_T12IC.GLVL_0 0 Group Priority Level bit 0
ASC1_EIC 0xF192 ASC1 Error Interrupt Control Register
ASC1_EIC.GPX 8 Group Priority Extension
ASC1_EIC.IR 7 Interrupt Request Flag
ASC1_EIC.IE 6 Interrupt Enable Control Bit
ASC1_EIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_EIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_EIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_EIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_EIC.GLVL_1 1 Group Priority Level bit 1
ASC1_EIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC31IC 0xF194 CAPCOM Channel 31 Interrupt Control Register
CC2_CC31IC.GPX 8 Group Priority Extension
CC2_CC31IC.IR 7 Interrupt Request Flag
CC2_CC31IC.IE 6 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC31IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC31IC.GLVL_0 0 Group Priority Level bit 0
CAN_0IC 0xF196 CAN Mode 0 Interrupt Control register
CAN_0IC.GPX 8 Group Priority Extension
CAN_0IC.IR 7 Interrupt Request Flag
CAN_0IC.IE 6 Interrupt Enable Control Bit
CAN_0IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_0IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_0IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_0IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_0IC.GLVL_1 1 Group Priority Level bit 1
CAN_0IC.GLVL_0 0 Group Priority Level bit 0
CCU6_T13IC 0xF198 CAPCOM 6 Timer 13 Interrupt Control Register
CCU6_T13IC.GPX 8 Group Priority Extension
CCU6_T13IC.IR 7 Interrupt Request Flag
CCU6_T13IC.IE 6 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_T13IC.GLVL_1 1 Group Priority Level bit 1
CCU6_T13IC.GLVL_0 0 Group Priority Level bit 0
SDLM_IC 0xF19A SDLM Interrupt Control Register
ASC0_TBIC 0xF19C ASC0 Transmit Buffer Interrupt Control Register
ASC0_TBIC.GPX 8 Group Priority Extension
ASC0_TBIC.IR 7 Interrupt Request Flag
ASC0_TBIC.IE 6 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_TBIC.GLVL_1 1 Group Priority Level bit 1
ASC0_TBIC.GLVL_0 0 Group Priority Level bit 0
PLLIC 0xF19E PLL Interrupt Control Register
PLLIC.GPX 8 Group Priority Extension
PLLIC.IR 7 Interrupt Request Flag
PLLIC.IE 6 Interrupt Enable Control Bit
PLLIC.ILVL_5 5 Interrupt Enable Control Bit
PLLIC.ILVL_4 4 Interrupt Enable Control Bit
PLLIC.ILVL_3 3 Interrupt Enable Control Bit
PLLIC.ILVL_2 2 Interrupt Enable Control Bit
PLLIC.GLVL_1 1 Group Priority Level bit 1
PLLIC.GLVL_0 0 Group Priority Level bit 0
RTC_IC 0xF1A0 RTC Interrupt Control Register
RTC_IC.GPX 8 Group Priority Extension
RTC_IC.IR 7 Interrupt Request Flag
RTC_IC.IE 6 Interrupt Enable Control Bit
RTC_IC.ILVL_5 5 Interrupt Enable Control Bit
RTC_IC.ILVL_4 4 Interrupt Enable Control Bit
RTC_IC.ILVL_3 3 Interrupt Enable Control Bit
RTC_IC.ILVL_2 2 Interrupt Enable Control Bit
RTC_IC.GLVL_1 1 Group Priority Level bit 1
RTC_IC.GLVL_0 0 Group Priority Level bit 0
SSC1_TIC 0xF1AA SSC1 Transmit Interrupt Control Register
SSC1_TIC.GPX 8 Group Priority Extension
SSC1_TIC.IR 7 Interrupt Request Flag
SSC1_TIC.IE 6 Interrupt Enable Control Bit
SSC1_TIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_TIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_TIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_TIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_TIC.GLVL_1 1 Group Priority Level bit 1
SSC1_TIC.GLVL_0 0 Group Priority Level bit 0
SSC1_RIC 0xF1AC SSC1 Receive Interrupt Control Register
SSC1_RIC.GPX 8 Group Priority Extension
SSC1_RIC.IR 7 Interrupt Request Flag
SSC1_RIC.IE 6 Interrupt Enable Control Bit
SSC1_RIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_RIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_RIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_RIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_RIC.GLVL_1 1 Group Priority Level bit 1
SSC1_RIC.GLVL_0 0 Group Priority Level bit 0
SSC1_EIC 0xF1AE SSC Error Interrupt Control Register
SSC1_EIC.GPX 8 Group Priority Extension
SSC1_EIC.IR 7 Interrupt Request Flag
SSC1_EIC.IE 6 Interrupt Enable Control Bit
SSC1_EIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_EIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_EIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_EIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_EIC.GLVL_1 1 Group Priority Level bit 1
SSC1_EIC.GLVL_0 0 Group Priority Level bit 0
ASC0_ABCON 0xF1B8 ASC0 Autobaud Control Register
ASC1_ABIC 0xF1BA ASC1 Autobaud Interrupt Control Register
ASC1_ABIC.GPX 8 Group Priority Extension
ASC1_ABIC.IR 7 Interrupt Request Flag
ASC1_ABIC.IE 6 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_ABIC.GLVL_1 1 Group Priority Level bit 1
ASC1_ABIC.GLVL_0 0 Group Priority Level bit 0
ASC1_ABCON 0xF1BC ASC1 Autobaud Control Register
SYSCON0 0xF1BE General System Control Register
SYSCON0.RTCRST 15 RTC Reset Trigger
SYSCON0.RTCCM 14 RTC Clocking Mode
EXICON 0xF1C0 External Interrupt Control Register
EXICON.EXI7ES_15 15 External Interrupt 7 Edge Selection Field bit 15
EXICON.EXI7ES_14 14 External Interrupt 7 Edge Selection Field bit 14
EXICON.EXI6ES_13 13 External Interrupt 6 Edge Selection Field bit 13
EXICON.EXI6ES_12 12 External Interrupt 6 Edge Selection Field bit 12
EXICON.EXI5ES_11 11 External Interrupt 5 Edge Selection Field bit 11
EXICON.EXI5ES_10 10 External Interrupt 5 Edge Selection Field bit 10
EXICON.EXI4ES_9 9 External Interrupt 4 Edge Selection Field bit 9
EXICON.EXI4ES_8 8 External Interrupt 4 Edge Selection Field bit 8
EXICON.EXI3ES_7 7 External Interrupt 3 Edge Selection Field bit 7
EXICON.EXI3ES_6 6 External Interrupt 3 Edge Selection Field bit 6
EXICON.EXI2ES_5 5 External Interrupt 2 Edge Selection Field bit 5
EXICON.EXI2ES_4 4 External Interrupt 2 Edge Selection Field bit 4
EXICON.EXI1ES_3 3 External Interrupt 1 Edge Selection Field bit 3
EXICON.EXI1ES_2 2 External Interrupt 1 Edge Selection Field bit 2
EXICON.EXI0ES_1 1 External Interrupt 0 Edge Selection Field bit 1
EXICON.EXI0ES_0 0 External Interrupt 0 Edge Selection Field bit 0
PICON 0xF1C4 Port Input Control Register
PICON.P20HIN 9
PICON.P20LIN 8
PICON.P9LIN 7
PICON.P4LIN 4
PICON.P3HIN 3
PICON.P3LIN 2
ODP3 0xF1C6 Port 3 Open Drain Control Register
ODP3.P13 13
ODP3.P12 12
ODP3.P11 11
ODP3.P10 10
ODP3.P9 9
ODP3.P8 8
ODP3.P7 7
ODP3.P6 6
ODP3.P5 5
ODP3.P4 4
ODP3.P3 3
ODP3.P2 2
ODP3.P1 1
ODP3.P0 0
ODP4 0xF1CA Port 4 Open Drain Control Register
ODP4.P7 7
ODP4.P6 6
ODP4.P5 5
ODP4.P4 4
ODP4.P3 3
ODP4.P2 2
ODP4.P1 1
ODP4.P0 0
PLLCON 0xF1D0 PLL Control Register
PLLCON.PLLWRI 15 PLLCON Write Ignore Flag
PLLCON.PLLCTRL_14 14 PLL Operation Control bit 14
PLLCON.PLLCTRL_13 13 PLL Operation Control bit 13
PLLCON.PLLMUL_12 12 PLL Multiplication Factor bit 12
PLLCON.PLLMUL_11 11 PLL Multiplication Factor bit 11
PLLCON.PLLMUL_10 10 PLL Multiplication Factor bit 10
PLLCON.PLLMUL_9 9 PLL Multiplication Factor bit 9
PLLCON.PLLMUL_8 8 PLL Multiplication Factor bit 8
PLLCON.PLLVB_7 7 PLL VCO Band Select bit 7
PLLCON.PLLVB_6 6 PLL VCO Band Select bit 6
PLLCON.PLLIDIV_5 5 PLL Input Divider bit 5
PLLCON.PLLIDIV_4 4 PLL Input Divider bit 4
PLLCON.PLLODIV_3 3 PLL Output Divider bit 3
PLLCON.PLLODIV_2 2 PLL Output Divider bit 2
PLLCON.PLLODIV_1 1 PLL Output Divider bit 1
PLLCON.PLLODIV_0 0 PLL Output Divider bit 0
SYSCON3 0xF1D4 System Control Register 3
SYSCON3.SSC1DIS 15 Synchronous Serial Channel SSC1
SYSCON3.RTCDIS 14 Real Time Clock
SYSCON3.CANDIS 13 On-chip CAN Module
SYSCON3.CC6DIS 8 CAPCOM6 Unit
SYSCON3.CC2DIS 7 CAPCOM Unit 2
SYSCON3.CC1DIS 6 CAPCOM Unit 1
SYSCON3.PFMDIS 5 Program Flash Module
SYSCON3.GPTDIS 3 General Purpose Timer Blocks
SYSCON3.SSC0DIS 2 Synchronous Serial Channel SSC0
SYSCON3.ASC0DIS 1 USART ASC0
SYSCON3.ADCDIS 0 Analog/Digital Converter
EXISEL1 0xF1D8 External Interrupt Input Select Register
EXISEL1.EXI7SS_15 15 External Interrupt 7 Source Selection Field bit 15
EXISEL1.EXI7SS_14 14 External Interrupt 7 Source Selection Field bit 14
EXISEL1.EXI7SS_13 13 External Interrupt 7 Source Selection Field bit 13
EXISEL1.EXI7SS_12 12 External Interrupt 7 Source Selection Field bit 12
EXISEL1.EXI6SS_11 11 External Interrupt 6 Source Selection Field bit 11
EXISEL1.EXI6SS_10 10 External Interrupt 6 Source Selection Field bit 10
EXISEL1.EXI6SS_9 9 External Interrupt 6 Source Selection Field bit 9
EXISEL1.EXI6SS_8 8 External Interrupt 6 Source Selection Field bit 8
EXISEL1.EXI5SS_7 7 External Interrupt 5 Source Selection Field bit 7
EXISEL1.EXI5SS_6 6 External Interrupt 5 Source Selection Field bit 6
EXISEL1.EXI5SS_5 5 External Interrupt 5 Source Selection Field bit 5
EXISEL1.EXI5SS_4 4 External Interrupt 5 Source Selection Field bit 4
EXISEL1.EXI4SS_3 3 External Interrupt 4 Source Selection Field bit 3
EXISEL1.EXI4SS_2 2 External Interrupt 4 Source Selection Field bit 2
EXISEL1.EXI4SS_1 1 External Interrupt 4 Source Selection Field bit 1
EXISEL1.EXI4SS_0 0 External Interrupt 4 Source Selection Field bit 0
EXISEL0 0xF1DA External Interrupt Input Select Register
EXISEL0.EXI3SS_15 15 External Interrupt 3 Source Selection Field bit 15
EXISEL0.EXI3SS_14 14 External Interrupt 3 Source Selection Field bit 14
EXISEL0.EXI3SS_13 13 External Interrupt 3 Source Selection Field bit 13
EXISEL0.EXI3SS_12 12 External Interrupt 3 Source Selection Field bit 12
EXISEL0.EXI2SS_11 11 External Interrupt 2 Source Selection Field bit 11
EXISEL0.EXI2SS_10 10 External Interrupt 2 Source Selection Field bit 10
EXISEL0.EXI2SS_9 9 External Interrupt 2 Source Selection Field bit 9
EXISEL0.EXI2SS_8 8 External Interrupt 2 Source Selection Field bit 8
EXISEL0.EXI1SS_7 7 External Interrupt 1 Source Selection Field bit 7
EXISEL0.EXI1SS_6 6 External Interrupt 1 Source Selection Field bit 6
EXISEL0.EXI1SS_5 5 External Interrupt 1 Source Selection Field bit 5
EXISEL0.EXI1SS_4 4 External Interrupt 1 Source Selection Field bit 4
EXISEL0.EXI0SS_3 3 External Interrupt 0 Source Selection Field bit 3
EXISEL0.EXI0SS_2 2 External Interrupt 0 Source Selection Field bit 2
EXISEL0.EXI0SS_1 1 External Interrupt 0 Source Selection Field bit 1
EXISEL0.EXI0SS_0 0 External Interrupt 0 Source Selection Field bit 0
SYSCON1 0xF1DC System Control Register 1
SYSCON1.CPSYS 8 Clock Prescaler for System
SYSCON1.PFCFG_5 5 Program Flash Configuration bit 5
SYSCON1.PFCFG_4 4 Program Flash Configuration bit 4
SYSCON1.PDCFG_3 3 Port Driver Configuration bit 3
SYSCON1.PDCFG_2 2 Port Driver Configuration bit 2
SYSCON1.SLEEPCON_1 1 SLEEP Mode Configuration bit 1
SYSCON1.SLEEPCON_0 0 SLEEP Mode Configuration bit 0
RSTCON 0xF1E0 Reset Control Register
RSTCON.RODIS 7 RSTOUT Disable Control
RSTCON.ROCON 6 RSTOUT Control Switching ON
RSTCON.ROCOFF 5 RSTOUT Control Switching Off
RSTCON.RORMV 4 RSTOUT Remove Control
RSTCON.RSTLEN_2 2 Reset Length Control bit 2
RSTCON.RSTLEN_1 1 Reset Length Control bit 1
RSTCON.RSTLEN_0 0 Reset Length Control bit 0
SYSSTAT 0xF1E4 System Status Register
SYSSTAT.OSCLOCK 15 Oscillator Signal Status Bit
SYSSTAT.PLLLOCK 14 PLL Signal Status Bit
SYSSTAT.CLKHIX 13 Input Clock High Limit Exceeded
SYSSTAT.CLKLOX 12 Input Clock Low Limit Exceeded
SYSSTAT.PLLEM 10 PLL Emergency Mode Flag
SYSSTAT.HWR 2 Hardware Reset Indication Flag
SYSSTAT.SWR 1 Software Reset Indication Flag
SYSSTAT.WDTR 0 Watchdog Timer Reset Indication Flag
DPP0 0xFE00 Data Page Pointer 0 Register
DPP0.PN_9 9 Data Page Number of DPP bit 9
DPP0.PN_8 8 Data Page Number of DPP bit 8
DPP0.PN_7 7 Data Page Number of DPP bit 7
DPP0.PN_6 6 Data Page Number of DPP bit 6
DPP0.PN_5 5 Data Page Number of DPP bit 5
DPP0.PN_4 4 Data Page Number of DPP bit 4
DPP0.PN_3 3 Data Page Number of DPP bit 3
DPP0.PN_2 2 Data Page Number of DPP bit 2
DPP0.PN_1 1 Data Page Number of DPP bit 1
DPP0.PN_0 0 Data Page Number of DPP bit 0
DPP1 0xFE02 Data Page Pointer 1 Register
DPP1.PN_9 9 Data Page Number of DPP bit 9
DPP1.PN_8 8 Data Page Number of DPP bit 8
DPP1.PN_7 7 Data Page Number of DPP bit 7
DPP1.PN_6 6 Data Page Number of DPP bit 6
DPP1.PN_5 5 Data Page Number of DPP bit 5
DPP1.PN_4 4 Data Page Number of DPP bit 4
DPP1.PN_3 3 Data Page Number of DPP bit 3
DPP1.PN_2 2 Data Page Number of DPP bit 2
DPP1.PN_1 1 Data Page Number of DPP bit 1
DPP1.PN_0 0 Data Page Number of DPP bit 0
DPP2 0xFE04 Data Page Pointer 2 Register
DPP2.PN_9 9 Data Page Number of DPP bit 9
DPP2.PN_8 8 Data Page Number of DPP bit 8
DPP2.PN_7 7 Data Page Number of DPP bit 7
DPP2.PN_6 6 Data Page Number of DPP bit 6
DPP2.PN_5 5 Data Page Number of DPP bit 5
DPP2.PN_4 4 Data Page Number of DPP bit 4
DPP2.PN_3 3 Data Page Number of DPP bit 3
DPP2.PN_2 2 Data Page Number of DPP bit 2
DPP2.PN_1 1 Data Page Number of DPP bit 1
DPP2.PN_0 0 Data Page Number of DPP bit 0
DPP3 0xFE06 Data Page Pointer 3 Register
DPP3.PN_9 9 Data Page Number of DPP bit 9
DPP3.PN_8 8 Data Page Number of DPP bit 8
DPP3.PN_7 7 Data Page Number of DPP bit 7
DPP3.PN_6 6 Data Page Number of DPP bit 6
DPP3.PN_5 5 Data Page Number of DPP bit 5
DPP3.PN_4 4 Data Page Number of DPP bit 4
DPP3.PN_3 3 Data Page Number of DPP bit 3
DPP3.PN_2 2 Data Page Number of DPP bit 2
DPP3.PN_1 1 Data Page Number of DPP bit 1
DPP3.PN_0 0 Data Page Number of DPP bit 0
CSP 0xFE08 Code Segment Pointer Register
CSP.SEGNR_7 7
CSP.SEGNR_6 6
CSP.SEGNR_5 5
CSP.SEGNR_4 4
CSP.SEGNR_3 3
CSP.SEGNR_2 2
CSP.SEGNR_1 1
CSP.SEGNR_0 0
EMUCON 0xFE0A Emulation Control Reg.
EMUCON.OCEN 2 OCDS/Cerberus Enable
EMUCON.OCDSIOEN 1 OCDS Break Input/Output Enable
MDH 0xFE0C Multiply Divide Register - High Word
MDH.MDH_15 15 High part of MD bit 15
MDH.MDH_14 14 High part of MD bit 14
MDH.MDH_13 13 High part of MD bit 13
MDH.MDH_12 12 High part of MD bit 12
MDH.MDH_11 11 High part of MD bit 11
MDH.MDH_10 10 High part of MD bit 10
MDH.MDH_9 9 High part of MD bit 9
MDH.MDH_8 8 High part of MD bit 8
MDH.MDH_7 7 High part of MD bit 7
MDH.MDH_6 6 High part of MD bit 6
MDH.MDH_5 5 High part of MD bit 5
MDH.MDH_4 4 High part of MD bit 4
MDH.MDH_3 3 High part of MD bit 3
MDH.MDH_2 2 High part of MD bit 2
MDH.MDH_1 1 High part of MD bit 1
MDH.MDH_0 0 High part of MD bit 0
MDL 0xFE0E Multiply Divide Register - Low Word
MDL.MDL_15 15 Low part of MD bit 15
MDL.MDL_14 14 Low part of MD bit 14
MDL.MDL_13 13 Low part of MD bit 13
MDL.MDL_12 12 Low part of MD bit 12
MDL.MDL_11 11 Low part of MD bit 11
MDL.MDL_10 10 Low part of MD bit 10
MDL.MDL_9 9 Low part of MD bit 9
MDL.MDL_8 8 Low part of MD bit 8
MDL.MDL_7 7 Low part of MD bit 7
MDL.MDL_6 6 Low part of MD bit 6
MDL.MDL_5 5 Low part of MD bit 5
MDL.MDL_4 4 Low part of MD bit 4
MDL.MDL_3 3 Low part of MD bit 3
MDL.MDL_2 2 Low part of MD bit 2
MDL.MDL_1 1 Low part of MD bit 1
MDL.MDL_0 0 Low part of MD bit 0
CP 0xFE10 Context Pointer Register
CP.CONTEXT_POINTER_11 11 Modifiable Portion of register CP bit 11
CP.CONTEXT_POINTER_10 10 Modifiable Portion of register CP bit 10
CP.CONTEXT_POINTER_9 9 Modifiable Portion of register CP bit 9
CP.CONTEXT_POINTER_8 8 Modifiable Portion of register CP bit 8
CP.CONTEXT_POINTER_7 7 Modifiable Portion of register CP bit 7
CP.CONTEXT_POINTER_6 6 Modifiable Portion of register CP bit 6
CP.CONTEXT_POINTER_5 5 Modifiable Portion of register CP bit 5
CP.CONTEXT_POINTER_4 4 Modifiable Portion of register CP bit 4
CP.CONTEXT_POINTER_3 3 Modifiable Portion of register CP bit 3
CP.CONTEXT_POINTER_2 2 Modifiable Portion of register CP bit 2
CP.CONTEXT_POINTER_1 1 Modifiable Portion of register CP bit 1
SP 0xFE12 Stack Pointer Register
SP.SP_15 15 Modifiable portion of register SP bit 15
SP.SP_14 14 Modifiable portion of register SP bit 14
SP.SP_13 13 Modifiable portion of register SP bit 13
SP.SP_12 12 Modifiable portion of register SP bit 12
SP.SP_11 11 Modifiable portion of register SP bit 11
SP.SP_10 10 Modifiable portion of register SP bit 10
SP.SP_9 9 Modifiable portion of register SP bit 9
SP.SP_8 8 Modifiable portion of register SP bit 8
SP.SP_7 7 Modifiable portion of register SP bit 7
SP.SP_6 6 Modifiable portion of register SP bit 6
SP.SP_5 5 Modifiable portion of register SP bit 5
SP.SP_4 4 Modifiable portion of register SP bit 4
SP.SP_3 3 Modifiable portion of register SP bit 3
SP.SP_2 2 Modifiable portion of register SP bit 2
SP.SP_1 1 Modifiable portion of register SP bit 1
STKOV 0xFE14 Stack Overflow Pointer Register
STKOV.STKOV_15 15 Modifiable portion of register STKOV bit 15
STKOV.STKOV_14 14 Modifiable portion of register STKOV bit 14
STKOV.STKOV_13 13 Modifiable portion of register STKOV bit 13
STKOV.STKOV_12 12 Modifiable portion of register STKOV bit 12
STKOV.STKOV_11 11 Modifiable portion of register STKOV bit 11
STKOV.STKOV_10 10 Modifiable portion of register STKOV bit 10
STKOV.STKOV_9 9 Modifiable portion of register STKOV bit 9
STKOV.STKOV_8 8 Modifiable portion of register STKOV bit 8
STKOV.STKOV_7 7 Modifiable portion of register STKOV bit 7
STKOV.STKOV_6 6 Modifiable portion of register STKOV bit 6
STKOV.STKOV_5 5 Modifiable portion of register STKOV bit 5
STKOV.STKOV_4 4 Modifiable portion of register STKOV bit 4
STKOV.STKOV_3 3 Modifiable portion of register STKOV bit 3
STKOV.STKOV_2 2 Modifiable portion of register STKOV bit 2
STKOV.STKOV_1 1 Modifiable portion of register STKOV bit 1
STKUN 0xFE16 Stack Underflow Pointer Register
STKUN.STKUN_15 15 Modifiable portion of register STKUN bit 15
STKUN.STKUN_14 14 Modifiable portion of register STKUN bit 14
STKUN.STKUN_13 13 Modifiable portion of register STKUN bit 13
STKUN.STKUN_12 12 Modifiable portion of register STKUN bit 12
STKUN.STKUN_11 11 Modifiable portion of register STKUN bit 11
STKUN.STKUN_10 10 Modifiable portion of register STKUN bit 10
STKUN.STKUN_9 9 Modifiable portion of register STKUN bit 9
STKUN.STKUN_8 8 Modifiable portion of register STKUN bit 8
STKUN.STKUN_7 7 Modifiable portion of register STKUN bit 7
STKUN.STKUN_6 6 Modifiable portion of register STKUN bit 6
STKUN.STKUN_5 5 Modifiable portion of register STKUN bit 5
STKUN.STKUN_4 4 Modifiable portion of register STKUN bit 4
STKUN.STKUN_3 3 Modifiable portion of register STKUN bit 3
STKUN.STKUN_2 2 Modifiable portion of register STKUN bit 2
STKUN.STKUN_1 1 Modifiable portion of register STKUN bit 1
CPUCON1 0xFE18 CPU Control Register 1
CPUCON1.VECSC_6 6 Scaling factor of Vector Table bit 6
CPUCON1.VECSC_5 5 Scaling factor of Vector Table bit 5
CPUCON1.WDTCTL 4 Configuration of Watch Dog Timer
CPUCON1.SGTDIS 3 Segmentation Disable/Enable Control
CPUCON1.INTSCXT 2 Enable Interruptibility of Switch Context
CPUCON1.BP 1 Enable Branch Prediction Unit
CPUCON1.ZCJ 0 Enable Zero Cycle Jump function
CPUCON2 0xFE1A CPU Control Register 2
CPUCON2.FIFODEPTH_15 15 FIFO Depth configuration bit 15
CPUCON2.FIFODEPTH_14 14 FIFO Depth configuration bit 14
CPUCON2.FIFODEPTH_13 13 FIFO Depth configuration bit 13
CPUCON2.FIFODEPTH_12 12 FIFO Depth configuration bit 12
CPUCON2.FIFOFED_11 11 FIFO Fed configuration bit 11
CPUCON2.FIFOFED_10 10 FIFO Fed configuration bit 10
CPUCON2.BYPPF 9 Prefetch Bypass control
CPUCON2.BYPF 8 Fetch Bypass control
CPUCON2.EIOIAEN 7 Early IO Injection Acknowledge Enable
CPUCON2.STEN 6 Stall Instruction Enable
CPUCON2.LFIC 5 Linear Follower Instruction Cache
CPUCON2.OVRUN 4 Pipeline control
CPUCON2.RETST 3 Enable return Stack
CPUCON2.DAID 1 Disable Atomic Injection Deny
CPUCON2.SL 0 Enables short loop mode
CC2_SEM 0xFE28 CAPCOM 2 Single Event Control Register
CC2_SEE 0xFE2A CAPCOM 2 Single Event Enable Register
CC1_SEM 0xFE2C CAPCOM 1 Single Event Control Register
CC1_SEE 0xFE2E CAPCOM 1 Single Event Enable Register
GPT12E_T2 0xFE40 GPT1 Timer 2 Register
GPT12E_T3 0xFE42 GPT1 Timer 3 Register
GPT12E_T4 0xFE44 GPT1 Timer 4 Register
GPT12E_T5 0xFE46 GPT2 Timer 5 Register
GPT12E_T6 0xFE48 GPT2 Timer 6 Register
GPT12E_CAPREL 0xFE4A GPT12 Capture/Reload Register
CC1_T0 0xFE50 CAPCOM 1 Timer 0 Register
CC1_T1 0xFE52 CAPCOM 1 Timer 1 Register
CC1_T0REL 0xFE54 CAPCOM 1 Timer 0 Reload Register
CC1_T1REL 0xFE56 CC Timer 1 Reloed Register
OPSEN 0xFE58 OCE/OCDS P-Susp. En. Reg
OPSEN.SSC1SEN 15 Module xx Suspend Enable
OPSEN.RTCSEN 14 Module xx Suspend Enable
OPSEN.CC6SEN 8 Module xx Suspend Enable
OPSEN.CC2SEN 7 Module xx Suspend Enable
OPSEN.CC1SEN 6 Module xx Suspend Enable
OPSEN.GPTSEN 2 Module xx Suspend Enable
OPSEN.SSC0SEN 1 Module xx Suspend Enable
OPSEN.ASC0SEN 0 Module xx Suspend Enable
MAL 0xFE5C MAC Accumulator Low Word
MAL.MAL_15 15 Low part of Accumulator bit 15
MAL.MAL_14 14 Low part of Accumulator bit 14
MAL.MAL_13 13 Low part of Accumulator bit 13
MAL.MAL_12 12 Low part of Accumulator bit 12
MAL.MAL_11 11 Low part of Accumulator bit 11
MAL.MAL_10 10 Low part of Accumulator bit 10
MAL.MAL_9 9 Low part of Accumulator bit 9
MAL.MAL_8 8 Low part of Accumulator bit 8
MAL.MAL_7 7 Low part of Accumulator bit 7
MAL.MAL_6 6 Low part of Accumulator bit 6
MAL.MAL_5 5 Low part of Accumulator bit 5
MAL.MAL_4 4 Low part of Accumulator bit 4
MAL.MAL_3 3 Low part of Accumulator bit 3
MAL.MAL_2 2 Low part of Accumulator bit 2
MAL.MAL_1 1 Low part of Accumulator bit 1
MAL.MAL_0 0 Low part of Accumulator bit 0
MAH 0xFE5E MAC Accumulator High Word
MAH.MAH_15 15 High part of Accumulator bit 15
MAH.MAH_14 14 High part of Accumulator bit 14
MAH.MAH_13 13 High part of Accumulator bit 13
MAH.MAH_12 12 High part of Accumulator bit 12
MAH.MAH_11 11 High part of Accumulator bit 11
MAH.MAH_10 10 High part of Accumulator bit 10
MAH.MAH_9 9 High part of Accumulator bit 9
MAH.MAH_8 8 High part of Accumulator bit 8
MAH.MAH_7 7 High part of Accumulator bit 7
MAH.MAH_6 6 High part of Accumulator bit 6
MAH.MAH_5 5 High part of Accumulator bit 5
MAH.MAH_4 4 High part of Accumulator bit 4
MAH.MAH_3 3 High part of Accumulator bit 3
MAH.MAH_2 2 High part of Accumulator bit 2
MAH.MAH_1 1 High part of Accumulator bit 1
MAH.MAH_0 0 High part of Accumulator bit 0
CC2_CC16 0xFE60 CAPCOM 2 Register 16
CC2_CC17 0xFE62 CAPCOM 2 Register 17
CC2_CC18 0xFE64 CAPCOM 2 Register 18
CC2_CC19 0xFE66 CAPCOM 2 Register 19
CC2_CC20 0xFE68 CAPCOM 2 Register 20
CC2_CC21 0xFE6A CAPCOM 2 Register 21
CC2_CC22 0xFE6C CAPCOM 2 Register 22
CC2_CC23 0xFE6E CAPCOM 2 Register 23
CC2_CC24 0xFE70 CAPCOM 2 Register 24
CC2_CC25 0xFE72 CAPCOM 2 Register 25
CC2_CC26 0xFE74 CAPCOM 2 Register 26
CC2_CC27 0xFE76 CAPCOM 2 Register 27
CC2_CC28 0xFE78 CAPCOM 2 Register 28
CC2_CC29 0xFE7A CAPCOM 2 Register 29
CC2_CC30 0xFE7C CAPCOM 2 Register 30
CC2_CC31 0xFE7E CAPCOM 2 Register 31
CC1_CC0 0xFE80 CAPCOM 1 Register 0
CC1_CC1 0xFE82 CAPCOM 1 Register 1
CC1_CC2 0xFE84 CAPCOM 1 Register 2
CC1_CC3 0xFE86 CAPCOM 1 Register 3
CC1_CC4 0xFE88 CAPCOM 1 Register 4
CC1_CC5 0xFE8A CAPCOM 1 Register 5
CC1_CC6 0xFE8C CAPCOM 1 Register 6
CC1_CC7 0xFE8E CAPCOM 1 Register 7
CC1_CC8 0xFE90 CAPCOM 1 Register 8
CC1_CC9 0xFE92 CAPCOM 1 Register 9
CC1_CC10 0xFE94 CAPCOM 1 Register 10
CC1_CC11 0xFE96 CAPCOM 1 Register 11
CC1_CC12 0xFE98 CAPCOM 1 Register 12
CC1_CC13 0xFE9A CAPCOM 1 Register 13
CC1_CC14 0xFE9C CAPCOM 1 Register 14
CC1_CC15 0xFE9E CAPCOM 1 Register 15
ADC_DAT 0xFEA0 A/D Converter Result Register
ADC_ID 0xFEA8 A/D Converter ID Register
ASC0_PMW 0xFEAA ASC0 IrDA Pulse Mode and Width Reg.
ASC1_PMW 0xFEAC ASC1 IrDA Pulse Mode and Width Reg.
WDT 0xFEAE Watchdog Timer Register (RO)
ASC0_TBUF 0xFEB0 Serial Channel 0 Transmitter Buffer Register (WO)
ASC0_RBUF 0xFEB2 Serial Channel 0 Receiver Buffer Register (RO)
ASC0_BG 0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
ASC0_FDV 0xFEB6 Fractional Divider Register
ASC1_TBUF 0xFEB8 Serial Channel 1 Transmitter Buffer Register (WO)
ASC1_RBUF 0xFEBA Serial Channel 1 Receiver Buffer Register (RO)
ASC1_BG 0xFEBC Serial Channel 1 Baud Rate Generator Reload Register
ASC1_FDV 0xFEBE Fractional Divider Register
PECC0 0xFEC0 PEC Channel 0 Control Register
PECC0.EOPINT 14 End of PEC Interrupt Selection
PECC0.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC0.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC0.CL 11 Channel Link Control
PECC0.INC_10 10 Increment Control bit 10
PECC0.INC_9 9 Increment Control bit 9
PECC0.BWT 8 Byte/Word Transfer Selection
PECC0.COUNT_7 7 PEC Transfer Count bit 7
PECC0.COUNT_6 6 PEC Transfer Count bit 6
PECC0.COUNT_5 5 PEC Transfer Count bit 5
PECC0.COUNT_4 4 PEC Transfer Count bit 4
PECC0.COUNT_3 3 PEC Transfer Count bit 3
PECC0.COUNT_2 2 PEC Transfer Count bit 2
PECC0.COUNT_1 1 PEC Transfer Count bit 1
PECC0.COUNT_0 0 PEC Transfer Count bit 0
PECC1 0xFEC2 PEC Channel 1 Control Register
PECC1.EOPINT 14 End of PEC Interrupt Selection
PECC1.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC1.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC1.CL 11 Channel Link Control
PECC1.INC_10 10 Increment Control bit 10
PECC1.INC_9 9 Increment Control bit 9
PECC1.BWT 8 Byte/Word Transfer Selection
PECC1.COUNT_7 7 PEC Transfer Count bit 7
PECC1.COUNT_6 6 PEC Transfer Count bit 6
PECC1.COUNT_5 5 PEC Transfer Count bit 5
PECC1.COUNT_4 4 PEC Transfer Count bit 4
PECC1.COUNT_3 3 PEC Transfer Count bit 3
PECC1.COUNT_2 2 PEC Transfer Count bit 2
PECC1.COUNT_1 1 PEC Transfer Count bit 1
PECC1.COUNT_0 0 PEC Transfer Count bit 0
PECC2 0xFEC4 PEC Channel 2 Control Register
PECC2.EOPINT 14 End of PEC Interrupt Selection
PECC2.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC2.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC2.CL 11 Channel Link Control
PECC2.INC_10 10 Increment Control bit 10
PECC2.INC_9 9 Increment Control bit 9
PECC2.BWT 8 Byte/Word Transfer Selection
PECC2.COUNT_7 7 PEC Transfer Count bit 7
PECC2.COUNT_6 6 PEC Transfer Count bit 6
PECC2.COUNT_5 5 PEC Transfer Count bit 5
PECC2.COUNT_4 4 PEC Transfer Count bit 4
PECC2.COUNT_3 3 PEC Transfer Count bit 3
PECC2.COUNT_2 2 PEC Transfer Count bit 2
PECC2.COUNT_1 1 PEC Transfer Count bit 1
PECC2.COUNT_0 0 PEC Transfer Count bit 0
PECC3 0xFEC6 PEC Channel 3 Control Register
PECC3.EOPINT 14 End of PEC Interrupt Selection
PECC3.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC3.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC3.CL 11 Channel Link Control
PECC3.INC_10 10 Increment Control bit 10
PECC3.INC_9 9 Increment Control bit 9
PECC3.BWT 8 Byte/Word Transfer Selection
PECC3.COUNT_7 7 PEC Transfer Count bit 7
PECC3.COUNT_6 6 PEC Transfer Count bit 6
PECC3.COUNT_5 5 PEC Transfer Count bit 5
PECC3.COUNT_4 4 PEC Transfer Count bit 4
PECC3.COUNT_3 3 PEC Transfer Count bit 3
PECC3.COUNT_2 2 PEC Transfer Count bit 2
PECC3.COUNT_1 1 PEC Transfer Count bit 1
PECC3.COUNT_0 0 PEC Transfer Count bit 0
PECC4 0xFEC8 PEC Channel 4 Control Register
PECC4.EOPINT 14 End of PEC Interrupt Selection
PECC4.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC4.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC4.CL 11 Channel Link Control
PECC4.INC_10 10 Increment Control bit 10
PECC4.INC_9 9 Increment Control bit 9
PECC4.BWT 8 Byte/Word Transfer Selection
PECC4.COUNT_7 7 PEC Transfer Count bit 7
PECC4.COUNT_6 6 PEC Transfer Count bit 6
PECC4.COUNT_5 5 PEC Transfer Count bit 5
PECC4.COUNT_4 4 PEC Transfer Count bit 4
PECC4.COUNT_3 3 PEC Transfer Count bit 3
PECC4.COUNT_2 2 PEC Transfer Count bit 2
PECC4.COUNT_1 1 PEC Transfer Count bit 1
PECC4.COUNT_0 0 PEC Transfer Count bit 0
PECC5 0xFECA PEC Channel 5 Control Register
PECC5.EOPINT 14 End of PEC Interrupt Selection
PECC5.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC5.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC5.CL 11 Channel Link Control
PECC5.INC_10 10 Increment Control bit 10
PECC5.INC_9 9 Increment Control bit 9
PECC5.BWT 8 Byte/Word Transfer Selection
PECC5.COUNT_7 7 PEC Transfer Count bit 7
PECC5.COUNT_6 6 PEC Transfer Count bit 6
PECC5.COUNT_5 5 PEC Transfer Count bit 5
PECC5.COUNT_4 4 PEC Transfer Count bit 4
PECC5.COUNT_3 3 PEC Transfer Count bit 3
PECC5.COUNT_2 2 PEC Transfer Count bit 2
PECC5.COUNT_1 1 PEC Transfer Count bit 1
PECC5.COUNT_0 0 PEC Transfer Count bit 0
PECC6 0xFECC PEC Channel 6 Control Register
PECC6.EOPINT 14 End of PEC Interrupt Selection
PECC6.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC6.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC6.CL 11 Channel Link Control
PECC6.INC_10 10 Increment Control bit 10
PECC6.INC_9 9 Increment Control bit 9
PECC6.BWT 8 Byte/Word Transfer Selection
PECC6.COUNT_7 7 PEC Transfer Count bit 7
PECC6.COUNT_6 6 PEC Transfer Count bit 6
PECC6.COUNT_5 5 PEC Transfer Count bit 5
PECC6.COUNT_4 4 PEC Transfer Count bit 4
PECC6.COUNT_3 3 PEC Transfer Count bit 3
PECC6.COUNT_2 2 PEC Transfer Count bit 2
PECC6.COUNT_1 1 PEC Transfer Count bit 1
PECC6.COUNT_0 0 PEC Transfer Count bit 0
PECC7 0xFECE PEC Channel 7 Control Register
PECC7.EOPINT 14 End of PEC Interrupt Selection
PECC7.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC7.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC7.CL 11 Channel Link Control
PECC7.INC_10 10 Increment Control bit 10
PECC7.INC_9 9 Increment Control bit 9
PECC7.BWT 8 Byte/Word Transfer Selection
PECC7.COUNT_7 7 PEC Transfer Count bit 7
PECC7.COUNT_6 6 PEC Transfer Count bit 6
PECC7.COUNT_5 5 PEC Transfer Count bit 5
PECC7.COUNT_4 4 PEC Transfer Count bit 4
PECC7.COUNT_3 3 PEC Transfer Count bit 3
PECC7.COUNT_2 2 PEC Transfer Count bit 2
PECC7.COUNT_1 1 PEC Transfer Count bit 1
PECC7.COUNT_0 0 PEC Transfer Count bit 0
P0L 0xFF00 PORT0 Low Register
P0L.P7 7
P0L.P6 6
P0L.P5 5
P0L.P4 4
P0L.P3 3
P0L.P2 2
P0L.P1 1
P0L.P0 0
P0H 0xFF02 Port 0 High Register (Upper half)
P0H.P7 7
P0H.P6 6
P0H.P5 5
P0H.P4 4
P0H.P3 3
P0H.P2 2
P0H.P1 1
P0H.P0 0
P1L 0xFF04 Port 1 Low Register
P1L.P7 7
P1L.P6 6
P1L.P5 5
P1L.P4 4
P1L.P3 3
P1L.P2 2
P1L.P1 1
P1L.P0 0
P1H 0xFF06 Port 1 High Register
P1H.P7 7
P1H.P6 6
P1H.P5 5
P1H.P4 4
P1H.P3 3
P1H.P2 2
P1H.P1 1
P1H.P0 0
IDX0 0xFF08 MAC Unit Address Pointer
IDX0.IDX_15 15 Modifiable portion of register IDX0 bit 15
IDX0.IDX_14 14 Modifiable portion of register IDX0 bit 14
IDX0.IDX_13 13 Modifiable portion of register IDX0 bit 13
IDX0.IDX_12 12 Modifiable portion of register IDX0 bit 12
IDX0.IDX_11 11 Modifiable portion of register IDX0 bit 11
IDX0.IDX_10 10 Modifiable portion of register IDX0 bit 10
IDX0.IDX_9 9 Modifiable portion of register IDX0 bit 9
IDX0.IDX_8 8 Modifiable portion of register IDX0 bit 8
IDX0.IDX_7 7 Modifiable portion of register IDX0 bit 7
IDX0.IDX_6 6 Modifiable portion of register IDX0 bit 6
IDX0.IDX_5 5 Modifiable portion of register IDX0 bit 5
IDX0.IDX_4 4 Modifiable portion of register IDX0 bit 4
IDX0.IDX_3 3 Modifiable portion of register IDX0 bit 3
IDX0.IDX_2 2 Modifiable portion of register IDX0 bit 2
IDX0.IDX_1 1 Modifiable portion of register IDX0 bit 1
IDX1 0xFF0A MAC Unit Address Pointer
IDX1.IDX_15 15 Modifiable portion of register IDX1 bit 15
IDX1.IDX_14 14 Modifiable portion of register IDX1 bit 14
IDX1.IDX_13 13 Modifiable portion of register IDX1 bit 13
IDX1.IDX_12 12 Modifiable portion of register IDX1 bit 12
IDX1.IDX_11 11 Modifiable portion of register IDX1 bit 11
IDX1.IDX_10 10 Modifiable portion of register IDX1 bit 10
IDX1.IDX_9 9 Modifiable portion of register IDX1 bit 9
IDX1.IDX_8 8 Modifiable portion of register IDX1 bit 8
IDX1.IDX_7 7 Modifiable portion of register IDX1 bit 7
IDX1.IDX_6 6 Modifiable portion of register IDX1 bit 6
IDX1.IDX_5 5 Modifiable portion of register IDX1 bit 5
IDX1.IDX_4 4 Modifiable portion of register IDX1 bit 4
IDX1.IDX_3 3 Modifiable portion of register IDX1 bit 3
IDX1.IDX_2 2 Modifiable portion of register IDX1 bit 2
IDX1.IDX_1 1 Modifiable portion of register IDX1 bit 1
SPSEG 0xFF0C Stack Pointer Segment Register
SPSEG.SPSEGNR_7 7 Stack Pointer Segment Number bit 7
SPSEG.SPSEGNR_6 6 Stack Pointer Segment Number bit 6
SPSEG.SPSEGNR_5 5 Stack Pointer Segment Number bit 5
SPSEG.SPSEGNR_4 4 Stack Pointer Segment Number bit 4
SPSEG.SPSEGNR_3 3 Stack Pointer Segment Number bit 3
SPSEG.SPSEGNR_2 2 Stack Pointer Segment Number bit 2
SPSEG.SPSEGNR_1 1 Stack Pointer Segment Number bit 1
SPSEG.SPSEGNR_0 0 Stack Pointer Segment Number bit 0
MDC 0xFF0E Multiply Divide Control Register
MDC.MDRIU 4 Multiply/Divide Register In Use
PSW 0xFF10 Processor Status Word
PSW.ILVL_15 15 CPU Priority Level bit 15
PSW.ILVL_14 14 CPU Priority Level bit 14
PSW.ILVL_13 13 CPU Priority Level bit 13
PSW.ILVL_12 12 CPU Priority Level bit 12
PSW.IEN 11 Interrupt/PEC Enable Bit (globally)
PSW.HLDEN 10 Hold Enable
PSW.BANK_9 9 Reserved for Register File Bank Selection bit 9
PSW.BANK_8 8 Reserved for Register File Bank Selection bit 8
PSW.USR1 7 General Purpose Flag
PSW.USR0 6 General Purpose Flag
PSW.MULIP 5 Multiplication/Division in progress
PSW.E 4 End of Table Flag
PSW.Z 3 Zero Flag
PSW.V 2 Overflow Flag
PSW.C 1 Carry Flag
PSW.N 0 Negative Result
VECSEG 0xFF12 Vector Segment Pointer
VECSEG.vecseg_7 7 Segment number of the Vector Table bit 7
VECSEG.vecseg_6 6 Segment number of the Vector Table bit 6
VECSEG.vecseg_5 5 Segment number of the Vector Table bit 5
VECSEG.vecseg_4 4 Segment number of the Vector Table bit 4
VECSEG.vecseg_3 3 Segment number of the Vector Table bit 3
VECSEG.vecseg_2 2 Segment number of the Vector Table bit 2
VECSEG.vecseg_1 1 Segment number of the Vector Table bit 1
VECSEG.vecseg_0 0 Segment number of the Vector Table bit 0
P9 0xFF16 Port 9 Data Register
P9.P5 5
P9.P4 4
P9.P3 3
P9.P2 2
P9.P1 1
P9.P0 0
DP9 0xFF18 Port 9 Direction Control Register
DP9.P5 5
DP9.P4 4
DP9.P3 3
DP9.P2 2
DP9.P1 1
DP9.P0 0
ODP9 0xFF1A Port 9 Open Drain Control Register
ODP9.P5 5
ODP9.P4 4
ODP9.P3 3
ODP9.P2 2
ODP9.P1 1
ODP9.P0 0
ZEROS 0xFF1C Constant Zeros Register
ONES 0xFF1E Constant Ones Register
CC2_T78CON 0xFF20 CAPCOM 2 Timer 7 and Timer 8 Control Register
CC2_T78CON.T8R 14
CC2_T78CON.T8M 11
CC2_T78CON.T7R 6
CC2_T78CON.T7M 3
CC2_M4 0xFF22 CC Mode Control Register 4
CC2_M4.ACC19 15
CC2_M4.ACC18 11
CC2_M4.ACC17 7
CC2_M4.ACC16 3
CC2_M5 0xFF24 CC Mode Control Register 5
CC2_M5.ACC23 15
CC2_M5.ACC22 11
CC2_M5.ACC21 7
CC2_M5.ACC20 3
CC2_M6 0xFF26 CC Mode Control Register 6
CC2_M6.ACC27 15
CC2_M6.ACC26 11
CC2_M6.ACC25 7
CC2_M6.ACC24 3
CC2_M7 0xFF28 CC Mode Control Register 7
CC2_M7.ACC31 15
CC2_M7.ACC30 11
CC2_M7.ACC29 7
CC2_M7.ACC28 3
CC2_DRM 0xFF2A CAPCOM 2 Double Register Mode Register
CC2_OUT 0xFF2C CAPCOM 2 Output Register
CC2_OUT.CC15IO 15
CC2_OUT.CC14IO 14
CC2_OUT.CC13IO 13
CC2_OUT.CC12IO 12
CC2_OUT.CC11IO 11
CC2_OUT.CC10IO 10
CC2_OUT.CC9IO 9
CC2_OUT.CC8IO 8
CC2_OUT.CC7IO 7
CC2_OUT.CC6IO 6
CC2_OUT.CC5IO 5
CC2_OUT.CC4IO 4
CC2_OUT.CC3IO 3
CC2_OUT.CC2IO 2
CC2_OUT.CC1IO 1
CC2_OUT.CC0IO 0
GPT12E_T2CON 0xFF40 GPT1 Timer 2 Control Register
GPT12E_T2CON.T2RDIR 15
GPT12E_T2CON.T2CHDIR 14
GPT12E_T2CON.T2EDGE 13
GPT12E_T2CON.T2IRDIS 12
GPT12E_T2CON.T2RC 9
GPT12E_T2CON.T2UDE 8
GPT12E_T2CON.T2UD 7
GPT12E_T2CON.T2R 6
GPT12E_T3CON 0xFF42 GPT1 Timer 3 Control Register
GPT12E_T3CON.T3RDIR 15
GPT12E_T3CON.T3CHDIR 14
GPT12E_T3CON.T3EDGE 13
GPT12E_T3CON.T3OTL 10
GPT12E_T3CON.T3OE 9
GPT12E_T3CON.T3UDE 8
GPT12E_T3CON.T3UD 7
GPT12E_T3CON.T3R 6
GPT12E_T4CON 0xFF44 GPT1 Timer 4 Control Register
GPT12E_T4CON.T4RDIR 15
GPT12E_T4CON.T4CHDIR 14
GPT12E_T4CON.T4EDGE 13
GPT12E_T4CON.T4IRDIS 12
GPT12E_T4CON.T4RC 9
GPT12E_T4CON.T4UDE 8
GPT12E_T4CON.T4UD 7
GPT12E_T4CON.T4R 6
GPT12E_T5CON 0xFF46 GPT2 Timer 5 Control Register
GPT12E_T5CON.T5SC 15
GPT12E_T5CON.T5CLR 14
GPT12E_T5CON.T5CC 11
GPT12E_T5CON.CT3 10
GPT12E_T5CON.T5RC 9
GPT12E_T5CON.T5UDE 8
GPT12E_T5CON.T5UD 7
GPT12E_T5CON.T5R 6
GPT12E_T6CON 0xFF48 GPT2 Timer 6 Control Register
GPT12E_T6CON.T6SR 15
GPT12E_T6CON.T6CLR 14
GPT12E_T6CON.T6OTL 10
GPT12E_T6CON.T6OE 9
GPT12E_T6CON.T6UDE 8
GPT12E_T6CON.T6UD 7
GPT12E_T6CON.T6R 6
CC1_T01CON 0xFF50 Timer 0/1 Control Register
CC1_T01CON.T1R 14
CC1_T01CON.T1M 11
CC1_T01CON.T0R 6
CC1_T01CON.T0M 3
CC1_M0 0xFF52 Capture/Compare Mode Registers for the CAPCOM Unit (CC0...CC3)
CC1_M0.ACC3 15
CC1_M0.ACC2 11
CC1_M0.ACC1 7
CC1_M0.ACC0 3
CC1_M1 0xFF54 Capture/Compare Mode Register for the CAPCOM Unit (CC4...CC79)
CC1_M1.ACC7 15
CC1_M1.ACC6 11
CC1_M1.ACC5 7
CC1_M1.ACC4 3
CC1_M2 0xFF56 Capture/Compare Mode Registers for the CAPCOM Unit (CC8...CC11)
CC1_M2.ACC11 15
CC1_M2.ACC10 11
CC1_M2.ACC9 7
CC1_M2.ACC8 3
CC1_M3 0xFF58 Capture/Compare Mode Registers for the CAPCOM Unit (CC12...CC15)
CC1_M3.ACC15 15
CC1_M3.ACC14 11
CC1_M3.ACC13 7
CC1_M3.ACC12 3
CC1_DRM 0xFF5A CAPCOM1 Double Register Mode Register
CC1_OUT 0xFF5C CAPCOM1 Output Register
CC1_OUT.CC0I15 15
CC1_OUT.CC0I14 14
CC1_OUT.CC0I13 13
CC1_OUT.CC0I12 12
CC1_OUT.CC0I11 11
CC1_OUT.CC0I10 10
CC1_OUT.CC0I9 9
CC1_OUT.CC0I8 8
CC1_OUT.CC0I7 7
CC1_OUT.CC0I6 6
CC1_OUT.CC0I5 5
CC1_OUT.CC0I4 4
CC1_OUT.CC0I3 3
CC1_OUT.CC0I2 2
CC1_OUT.CC0I1 1
CC1_OUT.CC0I0 0
SSC1_CON 0xFF5E SSC1 Control Register
SSC1_CON.EN 15
SSC1_CON.MS 14
SSC1_CON.AREN 12
SSC1_CON.BEN 11
SSC1_CON.PEN 10
SSC1_CON.REN 9
SSC1_CON.TEN 8
SSC1_CON.LB 7
SSC1_CON.PO 6
SSC1_CON.PH 5
SSC1_CON.HB 4
GPT12E_T2IC 0xFF60 GPT1 Timer 2 Interrupt Control Register
GPT12E_T2IC.GPX 8 Group Priority Extension
GPT12E_T2IC.IR 7 Interrupt Request Flag
GPT12E_T2IC.IE 6 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T2IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T2IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T3IC 0xFF62 GPT1 Timer 3 Interrupt Control Register
GPT12E_T3IC.GPX 8 Group Priority Extension
GPT12E_T3IC.IR 7 Interrupt Request Flag
GPT12E_T3IC.IE 6 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T3IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T3IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T4IC 0xFF64 GPT1 Timer 4 Interrupt Control Register
GPT12E_T4IC.GPX 8 Group Priority Extension
GPT12E_T4IC.IR 7 Interrupt Request Flag
GPT12E_T4IC.IE 6 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T4IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T4IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T5IC 0xFF66 GPT2 Timer 5 Interrupt Control Register
GPT12E_T5IC.GPX 8 Group Priority Extension
GPT12E_T5IC.IR 7 Interrupt Request Flag
GPT12E_T5IC.IE 6 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T5IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T5IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T6IC 0xFF68 GPT2 Timer 6 Interrupt Control Register
GPT12E_T6IC.GPX 8 Group Priority Extension
GPT12E_T6IC.IR 7 Interrupt Request Flag
GPT12E_T6IC.IE 6 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T6IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T6IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_CRIC 0xFF6A GPT2 CAPREL Interrupt Control Register
GPT12E_CRIC.GPX 8 Group Priority Extension
GPT12E_CRIC.IR 7 Interrupt Request Flag
GPT12E_CRIC.IE 6 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_CRIC.GLVL_1 1 Group Priority Level bit 1
GPT12E_CRIC.GLVL_0 0 Group Priority Level bit 0
ASC0_TIC 0xFF6C ASC0 Transmit Interrupt Control Register
ASC0_TIC.GPX 8 Group Priority Extension
ASC0_TIC.IR 7 Interrupt Request Flag
ASC0_TIC.IE 6 Interrupt Enable Control Bit
ASC0_TIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_TIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_TIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_TIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_TIC.GLVL_1 1 Group Priority Level bit 1
ASC0_TIC.GLVL_0 0 Group Priority Level bit 0
ASC0_RIC 0xFF6E ASC0 Receive Interrupt Control Register
ASC0_RIC.GPX 8 Group Priority Extension
ASC0_RIC.IR 7 Interrupt Request Flag
ASC0_RIC.IE 6 Interrupt Enable Control Bit
ASC0_RIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_RIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_RIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_RIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_RIC.GLVL_1 1 Group Priority Level bit 1
ASC0_RIC.GLVL_0 0 Group Priority Level bit 0
ASC0_EIC 0xFF70 ASC0 Error Interrupt Control Register
ASC0_EIC.GPX 8 Group Priority Extension
ASC0_EIC.IR 7 Interrupt Request Flag
ASC0_EIC.IE 6 Interrupt Enable Control Bit
ASC0_EIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_EIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_EIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_EIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_EIC.GLVL_1 1 Group Priority Level bit 1
ASC0_EIC.GLVL_0 0 Group Priority Level bit 0
SSC0_TIC 0xFF72 SSC0 Transmit Interrupt Control Register
SSC0_TIC.GPX 8 Group Priority Extension
SSC0_TIC.IR 7 Interrupt Request Flag
SSC0_TIC.IE 6 Interrupt Enable Control Bit
SSC0_TIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_TIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_TIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_TIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_TIC.GLVL_1 1 Group Priority Level bit 1
SSC0_TIC.GLVL_0 0 Group Priority Level bit 0
SSC0_RIC 0xFF74 SSC0 Receive Interrupt Control Register
SSC0_RIC.GPX 8 Group Priority Extension
SSC0_RIC.IR 7 Interrupt Request Flag
SSC0_RIC.IE 6 Interrupt Enable Control Bit
SSC0_RIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_RIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_RIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_RIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_RIC.GLVL_1 1 Group Priority Level bit 1
SSC0_RIC.GLVL_0 0 Group Priority Level bit 0
SSC0_EIC 0xFF76 SSC0 Error Interrupt Control Register
SSC0_EIC.GPX 8 Group Priority Extension
SSC0_EIC.IR 7 Interrupt Request Flag
SSC0_EIC.IE 6 Interrupt Enable Control Bit
SSC0_EIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_EIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_EIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_EIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_EIC.GLVL_1 1 Group Priority Level bit 1
SSC0_EIC.GLVL_0 0 Group Priority Level bit 0
CC1_CC0IC 0xFF78 CAPCOM Channel 0 Interrupt Control Register
CC1_CC0IC.GPX 8 Group Priority Extension
CC1_CC0IC.IR 7 Interrupt Request Flag
CC1_CC0IC.IE 6 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC0IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC0IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC1IC 0xFF7A CAPCOM Channel 1 Interrupt Control Register
CC1_CC1IC.GPX 8 Group Priority Extension
CC1_CC1IC.IR 7 Interrupt Request Flag
CC1_CC1IC.IE 6 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC1IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC1IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC2IC 0xFF7C CAPCOM Channel 2 Interrupt Control Register
CC1_CC2IC.GPX 8 Group Priority Extension
CC1_CC2IC.IR 7 Interrupt Request Flag
CC1_CC2IC.IE 6 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC2IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC2IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC3IC 0xFF7E CAPCOM Channel 3 Interrupt Control Register
CC1_CC3IC.GPX 8 Group Priority Extension
CC1_CC3IC.IR 7 Interrupt Request Flag
CC1_CC3IC.IE 6 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC3IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC3IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC4IC 0xFF80 CAPCOM Channel 4 Interrupt Control Register
CC1_CC4IC.GPX 8 Group Priority Extension
CC1_CC4IC.IR 7 Interrupt Request Flag
CC1_CC4IC.IE 6 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC4IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC4IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC5IC 0xFF82 CAPCOM Channel 5 Interrupt Control Register
CC1_CC5IC.GPX 8 Group Priority Extension
CC1_CC5IC.IR 7 Interrupt Request Flag
CC1_CC5IC.IE 6 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC5IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC5IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC6IC 0xFF84 CAPCOM Channel 6 Interrupt Control Register
CC1_CC6IC.GPX 8 Group Priority Extension
CC1_CC6IC.IR 7 Interrupt Request Flag
CC1_CC6IC.IE 6 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC6IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC6IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC7IC 0xFF86 CC Register 7 Interrupt Control Register
CC1_CC7IC.GPX 8 Group Priority Extension
CC1_CC7IC.IR 7 Interrupt Request Flag
CC1_CC7IC.IE 6 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC7IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC7IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC8IC 0xFF88 CC Register 8 Interrupt Control Register
CC1_CC8IC.GPX 8 Group Priority Extension
CC1_CC8IC.IR 7 Interrupt Request Flag
CC1_CC8IC.IE 6 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC8IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC8IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC9IC 0xFF8A CC Register 9 Interrupt Control Register
CC1_CC9IC.GPX 8 Group Priority Extension
CC1_CC9IC.IR 7 Interrupt Request Flag
CC1_CC9IC.IE 6 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC9IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC9IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC10IC 0xFF8C CAPCOM Channel 10 Interrupt Control Register
CC1_CC10IC.GPX 8 Group Priority Extension
CC1_CC10IC.IR 7 Interrupt Request Flag
CC1_CC10IC.IE 6 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC10IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC10IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC11IC 0xFF8E CAPCOM Channel 11 Interrupt Control Register
CC1_CC11IC.GPX 8 Group Priority Extension
CC1_CC11IC.IR 7 Interrupt Request Flag
CC1_CC11IC.IE 6 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC11IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC11IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC12IC 0xFF90 CAPCOM Channel 12 Interrupt Control Register
CC1_CC12IC.GPX 8 Group Priority Extension
CC1_CC12IC.IR 7 Interrupt Request Flag
CC1_CC12IC.IE 6 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC12IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC12IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC13IC 0xFF92 CAPCOM Channel 13 Interrupt Control Register
CC1_CC13IC.GPX 8 Group Priority Extension
CC1_CC13IC.IR 7 Interrupt Request Flag
CC1_CC13IC.IE 6 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC13IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC13IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC14IC 0xFF94 CAPCOM Channel 14 Interrupt Control Register
CC1_CC14IC.GPX 8 Group Priority Extension
CC1_CC14IC.IR 7 Interrupt Request Flag
CC1_CC14IC.IE 6 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC14IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC14IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC15IC 0xFF96 CAPCOM Channel 15 Interrupt Control Register
CC1_CC15IC.GPX 8 Group Priority Extension
CC1_CC15IC.IR 7 Interrupt Request Flag
CC1_CC15IC.IE 6 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC15IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC15IC.GLVL_0 0 Group Priority Level bit 0
ADC_CIC 0xFF98 ADC End of Conversion Interrupt Control Register
ADC_CIC.GPX 8 Group Priority Extension
ADC_CIC.IR 7 Interrupt Request Flag
ADC_CIC.IE 6 Interrupt Enable Control Bit
ADC_CIC.ILVL_5 5 Interrupt Enable Control Bit
ADC_CIC.ILVL_4 4 Interrupt Enable Control Bit
ADC_CIC.ILVL_3 3 Interrupt Enable Control Bit
ADC_CIC.ILVL_2 2 Interrupt Enable Control Bit
ADC_CIC.GLVL_1 1 Group Priority Level bit 1
ADC_CIC.GLVL_0 0 Group Priority Level bit 0
ADC_EIC 0xFF9A ADC Overrun Error Control Register
ADC_EIC.GPX 8
ADC_EIC.IR 7
ADC_EIC.IE 6
CC1_T0IC 0xFF9C CAPCOM 1 Timer 0 Interrupt Control Register
CC1_T0IC.GPX 8 Group Priority Extension
CC1_T0IC.IR 7 Interrupt Request Flag
CC1_T0IC.IE 6 Interrupt Enable Control Bit
CC1_T0IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_T0IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_T0IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_T0IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_T0IC.GLVL_1 1 Group Priority Level bit 1
CC1_T0IC.GLVL_0 0 Group Priority Level bit 0
CC1_T1IC 0xFF9E CC Timer 1 Interrupt Control Register
CC1_T1IC.GPX 8 Group Priority Extension
CC1_T1IC.IR 7 Interrupt Request Flag
CC1_T1IC.IE 6 Interrupt Enable Control Bit
CC1_T1IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_T1IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_T1IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_T1IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_T1IC.GLVL_1 1 Group Priority Level bit 1
CC1_T1IC.GLVL_0 0 Group Priority Level bit 0
ADC_CON 0xFFA0 A/D Converter Control Register
P5 0xFFA2 Port 5 Data Register
P5.P15 15
P5.P14 14
P5.P13 13
P5.P12 12
P5.P11 11
P5.P10 10
P5.P7 7
P5.P6 6
P5.P5 5
P5.P4 4
P5.P3 3
P5.P2 2
P5.P1 1
P5.P0 0
P5DIDIS 0xFFA4 Port 5 Digital Input Disable
P5DIDIS.P15 15
P5DIDIS.P14 14
P5DIDIS.P13 13
P5DIDIS.P12 12
P5DIDIS.P11 11
P5DIDIS.P10 10
P5DIDIS.P7 7
P5DIDIS.P6 6
P5DIDIS.P5 5
P5DIDIS.P4 4
P5DIDIS.P3 3
P5DIDIS.P2 2
P5DIDIS.P1 1
P5DIDIS.P0 0
ADC_CON1 0xFFA6 A/D Converter Control Register 1
PECISNC 0xFFA8 PEC Interrupt Subnode Control Register
PECISNC.C7IR 15 Interrupt Sub Node Request Flag of PEC Channel 7
PECISNC.C7IE 14 Interrupt Sub Node Enable Control Bit of PEC Channel 7
PECISNC.C6IR 13 Interrupt Sub Node Request Flag of PEC Channel 6
PECISNC.C6IE 12 Interrupt Sub Node Enable Control Bit of PEC Channel 6
PECISNC.C5IR 11 Interrupt Sub Node Request Flag of PEC Channel 5
PECISNC.C5IE 10 Interrupt Sub Node Enable Control Bit of PEC Channel 5
PECISNC.C4IR 9 Interrupt Sub Node Request Flag of PEC Channel 4
PECISNC.C4IE 8 Interrupt Sub Node Enable Control Bit of PEC Channel 4
PECISNC.C3IR 7 Interrupt Sub Node Request Flag of PEC Channel 3
PECISNC.C3IE 6 Interrupt Sub Node Enable Control Bit of PEC Channel 3
PECISNC.C2IR 5 Interrupt Sub Node Request Flag of PEC Channel 2
PECISNC.C2IE 4 Interrupt Sub Node Enable Control Bit of PEC Channel 2
PECISNC.C1IR 3 Interrupt Sub Node Request Flag of PEC Channel 1
PECISNC.C1IE 2 Interrupt Sub Node Enable Control Bit of PEC Channel 1
PECISNC.C0IR 1 Interrupt Sub Node Request Flag of PEC Channel 0
PECISNC.C0IE 0 Interrupt Sub Node Enable Control Bit of PEC Channel 0
FOCON 0xFFAA Frequency Output Control Register
FOCON.FOEN 15 Frequency Output Enable
FOCON.FOSS 14 Frequency Output Signal Select
FOCON.FORV_13 13 Frequency Output Reload Value bit 13
FOCON.FORV_12 12 Frequency Output Reload Value bit 12
FOCON.FORV_11 11 Frequency Output Reload Value bit 11
FOCON.FORV_10 10 Frequency Output Reload Value bit 10
FOCON.FORV_9 9 Frequency Output Reload Value bit 9
FOCON.FORV_8 8 Frequency Output Reload Value bit 8
FOCON.CLKEN 7 CLKOUT Enable
FOCON.FOTL 6 Frequency Output Toggle Latch
FOCON.FOCNT_5 5 Frequency Output Counter bit 5
FOCON.FOCNT_4 4 Frequency Output Counter bit 4
FOCON.FOCNT_3 3 Frequency Output Counter bit 3
FOCON.FOCNT_2 2 Frequency Output Counter bit 2
FOCON.FOCNT_1 1 Frequency Output Counter bit 1
FOCON.FOCNT_0 0 Frequency Output Counter bit 0
TFR 0xFFAC Trap Flag Register
TFR.NMI 15 Non maskable interrupt flag
TFR.STKOF 14 Stack overflow flag
TFR.STKUF 13 Stack underflow flag
TFR.SOFTBRK 12 Software Break
TFR.UNDOPC 7 Undefined Opcode
TFR.PACER 4 Program Memory Interface Access Error
TFR.PRTFLT 3 Protection Fault
TFR.ILLOPA 2 Illegal word operand access
WDTCON 0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL_15 15 Watchdog Timer Reload Value bit 15
WDTCON.WDTREL_14 14 Watchdog Timer Reload Value bit 14
WDTCON.WDTREL_13 13 Watchdog Timer Reload Value bit 13
WDTCON.WDTREL_12 12 Watchdog Timer Reload Value bit 12
WDTCON.WDTREL_11 11 Watchdog Timer Reload Value bit 11
WDTCON.WDTREL_10 10 Watchdog Timer Reload Value bit 10
WDTCON.WDTREL_9 9 Watchdog Timer Reload Value bit 9
WDTCON.WDTREL_8 8 Watchdog Timer Reload Value bit 8
WDTCON.WDTIN_1 1 Watchdog Timer Input Frequency Select bit 1
WDTCON.WDTIN_0 0 Watchdog Timer Input Frequency Select bit 0
ASC0_CON 0xFFB0 Serial Channel 0 Control Register
SSC0_CON 0xFFB2 SSC Control Register
SSC0_CON.EN 15
SSC0_CON.MS 14
SSC0_CON.AREN 12
SSC0_CON.BEN 11
SSC0_CON.PEN 10
SSC0_CON.REN 9
SSC0_CON.TEN 8
SSC0_CON.LB 7
SSC0_CON.PO 6
SSC0_CON.PH 5
SSC0_CON.HB 4
P20 0xFFB4 Port 20 Data Register
P20.P12 12
P20.P5 5
P20.P4 4
P20.P1 1
P20.P0 0
DP20 0xFFB6 Port 20 Direction Control Register
DP20.P12 12
DP20.P5 5
DP20.P4 4
DP20.P1 1
DP20.P0 0
ASC1_CON 0xFFB8 DCH Serial Channel 1 Control Register
ADC_CTR0 0xFFBE DFH A/D Converter Control Register 0
P3 0xFFC4 E2H Port 3 Data Register
P3.P15 15
P3.P13 13
P3.P12 12
P3.P11 11
P3.P10 10
P3.P9 9
P3.P8 8
P3.P7 7
P3.P6 6
P3.P5 5
P3.P4 4
P3.P3 3
P3.P2 2
P3.P1 1
P3.P0 0
DP3 0xFFC6 E3H Port 3 Direction Control Register
DP3.P15 15
DP3.P13 13
DP3.P12 12
DP3.P11 11
DP3.P10 10
DP3.P9 9
DP3.P8 8
DP3.P7 7
DP3.P6 6
DP3.P5 5
DP3.P4 4
DP3.P3 3
DP3.P2 2
DP3.P1 1
DP3.P0 0
P4 0xFFC8 E4H Port 4 Data Register
P4.P7 7
P4.P6 6
P4.P5 5
P4.P4 4
P4.P3 3
P4.P2 2
P4.P1 1
P4.P0 0
DP4 0xFFCA E5H Port 4 Direction Control Register
DP4.P7 7
DP4.P6 6
DP4.P5 5
DP4.P4 4
DP4.P3 3
DP4.P2 2
DP4.P1 1
DP4.P0 0
MRW 0xFFDA EDH MAC Repeat Word
MRW.REPEAT_COUNT_15 15 16-bit loop counter bit 15
MRW.REPEAT_COUNT_14 14 16-bit loop counter bit 14
MRW.REPEAT_COUNT_13 13 16-bit loop counter bit 13
MRW.REPEAT_COUNT_12 12 16-bit loop counter bit 12
MRW.REPEAT_COUNT_11 11 16-bit loop counter bit 11
MRW.REPEAT_COUNT_10 10 16-bit loop counter bit 10
MRW.REPEAT_COUNT_9 9 16-bit loop counter bit 9
MRW.REPEAT_COUNT_8 8 16-bit loop counter bit 8
MRW.REPEAT_COUNT_7 7 16-bit loop counter bit 7
MRW.REPEAT_COUNT_6 6 16-bit loop counter bit 6
MRW.REPEAT_COUNT_5 5 16-bit loop counter bit 5
MRW.REPEAT_COUNT_4 4 16-bit loop counter bit 4
MRW.REPEAT_COUNT_3 3 16-bit loop counter bit 3
MRW.REPEAT_COUNT_2 2 16-bit loop counter bit 2
MRW.REPEAT_COUNT_1 1 16-bit loop counter bit 1
MRW.REPEAT_COUNT_0 0 16-bit loop counter bit 0
MCW 0xFFDC EEH MAC Control Word
MCW.MP 10 One-bit scaler control
MCW.MS 9 Saturation control
MSW 0xFFDE EFH MAC Unit Status Word
MSW.MV 14 Overflow Flag
MSW.MSL 13 Sticky Limit Flag
MSW.ME 12 MAC Extension Flag
MSW.ME 11 Sticky Overflow Flag
MSW.MC 10 Carry Flag
MSW.MZ 9 Zero Flag
MSW.MN 8 Negative Result
MSW.MAE_7 7 The most significant bits of the 40-bit Accumulator bit 7
MSW.MAE_6 6 The most significant bits of the 40-bit Accumulator bit 6
MSW.MAE_5 5 The most significant bits of the 40-bit Accumulator bit 5
MSW.MAE_4 4 The most significant bits of the 40-bit Accumulator bit 4
MSW.MAE_3 3 The most significant bits of the 40-bit Accumulator bit 3
MSW.MAE_2 2 The most significant bits of the 40-bit Accumulator bit 2
MSW.MAE_1 1 The most significant bits of the 40-bit Accumulator bit 1
MSW.MAE_0 0 The most significant bits of the 40-bit Accumulator bit 0
ASC0_ID 0xFFE2 ASC0 Identification Register
SSC0_ID 0xFFE4 SSC0 Module Identification Register
GPT12E_ID 0xFFE6 GPT Identification Register
CC1_ID 0xFFEC CAPCOM1 Module Identification Register
CC2_ID 0xFFEE CAPCOM2 Module Identification Register
SSC1_ID 0xFFF6 Module Identification Register
; TWINCAN-16BIT
CAN_PISEL 0x200004 TwinCAN Port Input Select Register
CAN_ID 0x200008 CAN Module Identification Register
CAN_ACR 0x200200 Node A Control Register
CAN_ASR 0x200204 Node A Status Register
CAN_AIR 0x200208 Node A Interrupt Pending Register
CAN_ABTRL 0x20020C Node A Bit Timing Register Low
CAN_ABTRH 0x20020E Node A Bit Timing Register High
CAN_AGINP 0x200210 Node A Global Interrupt Node Pointer Register
CAN_AFCRL 0x200214 Node A Frame Counter Register Low
CAN_AFCRH 0x200216 Node A Frame Counter Register High
CAN_AIMRL0 0x200218 Node A INTID Mask Register 0 Low
CAN_AIMRH0 0x20021A Node A INTID Mask Register 0 High
CAN_AIMR4 0x20021C Node A INTID Mask Register 4 Low
CAN_AECNTL 0x200220 Node A Error Counter Register Low
CAN_AECNTH 0x200222 Node A Error Counter Register High
CAN_BCR 0x200240 Node B Control Register
CAN_BSR 0x200244 Node B Status Register
CAN_BIR 0x200248 Node B Interrupt Pending Register
CAN_BBTRL 0x20024C Node B Bit Timing Register Low
CAN_BBTRH 0x20024E Node B Bit Timing Register High
CAN_BGINP 0x200250 Node B Global Interrupt Node Pointer Register
CAN_BFCRL 0x200254 Node B Frame Counter Register Low
CAN_BFCRH 0x200256 Node B Frame Counter Register High
CAN_BIMRL0 0x200258 Node B INTID Mask Register 0 Low
CAN_BIMRH0 0x20025A Node B INTID Mask Register 0 High
CAN_BIMR4 0x20025C Node B INTID Mask Register 4 Low
CAN_BECNTL 0x200260 Node B Error Counter Register Low
CAN_BECNTH 0x200262 Node B Error Counter Register High
CAN_RXIPNDL 0x200284 Receive Interrupt Pending Register Low
CAN_RXIPNDH 0x200286 Receive Interrupt Pending Register High
CAN_TXIPNDL 0x200288 Transmit Interrupt Pending Register Low
CAN_TXIPNDH 0x20028A Transmit Interrupt Pending Register High
CAN_MSGDRL00 0x200300 Message Object 0 Data Register 0 Low
CAN_MSGDRH00 0x200302 Message Object 0 Data Register 0 High
CAN_MSGDRL04 0x200304 Message Object 0 Data Register 4 Low
CAN_MSGDRH04 0x200306 Message Object 0 Data Register 4 High
CAN_MSGARL0 0x200308 Message Object 0 Arbitration Register Low
CAN_MSGARH0 0x20030A Message Object 0 Arbitration Register High
CAN_MSGAMRL0 0x20030C Message Object 0 Arbitration Mask Register Low
CAN_MSGAMRH0 0x20030E Message Object 0 Arbitration Mask Register High
CAN_MSGCTRL0 0x200310 Message Object 0 Message Control Register Low
CAN_MSGCTRH0 0x200312 Message Object 0 Message Control Register High
CAN_MSGCFGL0 0x200314 Message Object 0 Message Configuration Register Low
CAN_MSGCFGH0 0x200316 Message Object 0 Message Configuration Register High
CAN_MSGFGCRL0 0x200318 Message Object 0 FIFO/Gateway Control Register Low
CAN_MSGFGCRH0 0x20031A Message Object 0 FIFO/Gateway Control Register High
CAN_MSGDRL10 0x200320 Message Object 1 Data Register 0 Low
CAN_MSGDRH10 0x200322 Message Object 1 Data Register 0 High
CAN_MSGDRL14 0x200324 Message Object 1 Data Register 4 Low
CAN_MSGDRH14 0x200326 Message Object 1 Data Register 4 High
CAN_MSGARL1 0x200328 Message Object 1 Arbitration Register Low
CAN_MSGARH1 0x20032A Message Object 1 Arbitration Register High
CAN_MSGAMRL1 0x20032C Message Object 1 Arbitration Mask Register Low
CAN_MSGAMRH1 0x20032E Message Object 1 Arbitration Mask Register High
CAN_MSGCTRL1 0x200330 Message Object 1 Message Control Register Low
CAN_MSGCTRH1 0x200332 Message Object 1 Message Control Register High
CAN_MSGCFGL1 0x200334 Message Object 1 Message Configuration Register Low
CAN_MSGCFGH1 0x200336 Message Object 1 Message Configuration Register High
CAN_MSGFGCRL1 0x200338 Message Object 1 FIFO/Gateway Control Register Low
CAN_MSGFGCRH1 0x20033A Message Object 1 FIFO/Gateway Control Register High
CAN_MSGDRL20 0x200340 Message Object 2 Data Register 0 Low
CAN_MSGDRH20 0x200342 Message Object 2 Data Register 0 High
CAN_MSGDRL24 0x200344 Message Object 2 Data Register 4 Low
CAN_MSGDRH24 0x200346 Message Object 2 Data Register 4 High
CAN_MSGARL2 0x200348 Message Object 2 Arbitration Register Low
CAN_MSGARH2 0x20034A Message Object 2 Arbitration Register High
CAN_MSGAMRL2 0x20034C Message Object 2 Arbitration Mask Register Low
CAN_MSGAMRH2 0x20034E Message Object 2 Arbitration Mask Register High
CAN_MSGCTRL2 0x200350 Message Object 2 Message Control Register Low
CAN_MSGCTRH2 0x200352 Message Object 2 Message Control Register High
CAN_MSGCFGL2 0x200354 Message Object 2 Message Configuration Register Low
CAN_MSGCFGH2 0x200356 Message Object 2 Message Configuration Register High
CAN_MSGFGCRL2 0x200358 Message Object 2 FIFO/Gateway Control Register Low
CAN_MSGFGCRH2 0x20035A Message Object 2 FIFO/Gateway Control Register High
CAN_MSGDRL30 0x200360 Message Object 3 Data Register 0 Low
CAN_MSGDRH30 0x200362 Message Object 3 Data Register 0 High
CAN_MSGDRL34 0x200364 Message Object 3 Data Register 4 Low
CAN_MSGDRH34 0x200366 Message Object 3 Data Register 4 High
CAN_MSGARL3 0x200368 Message Object 3 Arbitration Register Low
CAN_MSGARH3 0x20036A Message Object 3 Arbitration Register High
CAN_MSGAMRL3 0x20036C Message Object 3 Arbitration Mask Register Low
CAN_MSGAMRH3 0x20036E Message Object 3 Arbitration Mask Register High
CAN_MSGCTRL3 0x200370 Message Object 3 Message Control Register Low
CAN_MSGCTRH3 0x200372 Message Object 3 Message Control Register High
CAN_MSGCFGL3 0x200374 Message Object 3 Message Configuration Register Low
CAN_MSGCFGH3 0x200376 Message Object 3 Message Configuration Register High
CAN_MSGFGCRL3 0x200378 Message Object 3 FIFO/Gateway Control Register Low
CAN_MSGFGCRH3 0x20037A Message Object 3 FIFO/Gateway Control Register High
CAN_MSGDRL40 0x200380 Message Object 4 Data Register 0 Low
CAN_MSGDRH40 0x200382 Message Object 4 Data Register 0 High
CAN_MSGDRL44 0x200384 Message Object 4 Data Register 4 Low
CAN_MSGDRH44 0x200386 Message Object 4 Data Register 4 High
CAN_MSGARL4 0x200388 Message Object 4 Arbitration Register Low
CAN_MSGARH4 0x20038A Message Object 4 Arbitration Register High
CAN_MSGAMRL4 0x20038C Message Object 4 Arbitration Mask Register Low
CAN_MSGAMRH4 0x20038E Message Object 4 Arbitration Mask Register High
CAN_MSGCTRL4 0x200390 Message Object 4 Message Control Register Low
CAN_MSGCTRH4 0x200392 Message Object 4 Message Control Register High
CAN_MSGCFGL4 0x200394 Message Object 4 Message Configuration Register Low
CAN_MSGCFGH4 0x200396 Message Object 4 Message Configuration Register High
CAN_MSGFGCRL4 0x200398 Message Object 4 FIFO/Gateway Control Register Low
CAN_MSGFGCRH4 0x20039A Message Object 4 FIFO/Gateway Control Register High
CAN_MSGDRL50 0x2003A0 Message Object 5 Data Register 0 Low
CAN_MSGDRH50 0x2003A2 Message Object 5 Data Register 0 High
CAN_MSGDRL54 0x2003A4 Message Object 5 Data Register 4 Low
CAN_MSGDRH54 0x2003A6 Message Object 5 Data Register 4 High
CAN_MSGARL5 0x2003A8 Message Object 5 Arbitration Register Low
CAN_MSGARH5 0x2003AA Message Object 5 Arbitration Register High
CAN_MSGAMRL5 0x2003AC Message Object 5 Arbitration Mask Register Low
CAN_MSGAMRH5 0x2003AE Message Object 5 Arbitration Mask Register High
CAN_MSGCTRL5 0x2003B0 Message Object 5 Message Control Register Low
CAN_MSGCTRH5 0x2003B2 Message Object 5 Message Control Register High
CAN_MSGCFGL5 0x2003B4 Message Object 5 Message Configuration Register Low
CAN_MSGCFGH5 0x2003B6 Message Object 5 Message Configuration Register High
CAN_MSGFGCRL5 0x2003B8 Message Object 5 FIFO/Gateway Control Register Low
CAN_MSGFGCRH5 0x2003BA Message Object 5 FIFO/Gateway Control Register High
CAN_MSGDRL60 0x2003C0 Message Object 6 Data Register 0 Low
CAN_MSGDRH60 0x2003C2 Message Object 6 Data Register 0 High
CAN_MSGDRL64 0x2003C4 Message Object 6 Data Register 4 Low
CAN_MSGDRH64 0x2003C6 Message Object 6 Data Register 4 High
CAN_MSGARL6 0x2003C8 Message Object 6 Arbitration Register Low
CAN_MSGARH6 0x2003CA Message Object 6 Arbitration Register High
CAN_MSGAMRL6 0x2003CC Message Object 6 Arbitration Mask Register Low
CAN_MSGAMRH6 0x2003CE Message Object 6 Arbitration Mask Register High
CAN_MSGCTRL6 0x2003D0 Message Object 6 Message Control Register Low
CAN_MSGCTRH6 0x2003D2 Message Object 6 Message Control Register High
CAN_MSGCFGL6 0x2003D4 Message Object 6 Message Configuration Register Low
CAN_MSGCFGH6 0x2003D6 Message Object 6 Message Configuration Register High
CAN_MSGFGCRL6 0x2003D8 Message Object 6 FIFO/Gateway Control Register Low
CAN_MSGFGCRH6 0x2003DA Message Object 6 FIFO/Gateway Control Register High
CAN_MSGDRL70 0x2003E0 Message Object 7 Data Register 0 Low
CAN_MSGDRH70 0x2003E2 Message Object 7 Data Register 0 High
CAN_MSGDRL74 0x2003E4 Message Object 7 Data Register 4 Low
CAN_MSGDRH74 0x2003E6 Message Object 7 Data Register 4 High
CAN_MSGARL7 0x2003E8 Message Object 7 Arbitration Register Low
CAN_MSGARH7 0x2003EA Message Object 7 Arbitration Register High
CAN_MSGAMRL7 0x2003EC Message Object 7 Arbitration Mask Register Low
CAN_MSGAMRH7 0x2003EE Message Object 7 Arbitration Mask Register High
CAN_MSGCTRL7 0x2003F0 Message Object 7 Message Control Register Low
CAN_MSGCTRH7 0x2003F2 Message Object 7 Message Control Register High
CAN_MSGCFGL7 0x2003F4 Message Object 7 Message Configuration Register Low
CAN_MSGCFGH7 0x2003F6 Message Object 7 Message Configuration Register High
CAN_MSGFGCRL7 0x2003F8 Message Object 7 FIFO/Gateway Control Register Low
CAN_MSGFGCRH7 0x2003FA Message Object 7 FIFO/Gateway Control Register High
CAN_MSGDRL80 0x200400 Message Object 8 Data Register 0 Low
CAN_MSGDRH80 0x200402 Message Object 8 Data Register 0 High
CAN_MSGDRL84 0x200404 Message Object 8 Data Register 4 Low
CAN_MSGDRH84 0x200406 Message Object 8 Data Register 4 High
CAN_MSGARL8 0x200408 Message Object 8 Arbitration Register Low
CAN_MSGARH8 0x20040A Message Object 8 Arbitration Register High
CAN_MSGAMRL8 0x20040C Message Object 8 Arbitration Mask Register Low
CAN_MSGAMRH8 0x20040E Message Object 8 Arbitration Mask Register High
CAN_MSGCTRL8 0x200410 Message Object 8 Message Control Register Low
CAN_MSGCTRH8 0x200412 Message Object 8 Message Control Register High
CAN_MSGCFGL8 0x200414 Message Object 8 Message Configuration Register Low
CAN_MSGCFGH8 0x200416 Message Object 8 Message Configuration Register High
CAN_MSGFGCRL8 0x200418 Message Object 8 FIFO/Gateway Control Register Low
CAN_MSGFGCRH8 0x20041A Message Object 8 FIFO/Gateway Control Register High
CAN_MSGDRL90 0x200420 Message Object 9 Data Register 0 Low
CAN_MSGDRH90 0x200422 Message Object 9 Data Register 0 High
CAN_MSGDRL94 0x200424 Message Object 9 Data Register 4 Low
CAN_MSGDRH94 0x200426 Message Object 9 Data Register 4 High
CAN_MSGARL9 0x200428 Message Object 9 Arbitration Register Low
CAN_MSGARH9 0x20042A Message Object 9 Arbitration Register High
CAN_MSGAMRL9 0x20042C Message Object 9 Arbitration Mask Register Low
CAN_MSGAMRH9 0x20042E Message Object 9 Arbitration Mask Register High
CAN_MSGCTRL9 0x200430 Message Object 9 Message Control Register Low
CAN_MSGCTRH9 0x200432 Message Object 9 Message Control Register High
CAN_MSGCFGL9 0x200434 Message Object 9 Message Configuration Register Low
CAN_MSGCFGH9 0x200436 Message Object 9 Message Configuration Register High
CAN_MSGFGCRL9 0x200438 Message Object 9 FIFO/Gateway Control Register Low
CAN_MSGFGCRH9 0x20043A Message Object 9 FIFO/Gateway Control Register High
CAN_MSGDRL100 0x200440 Message Object 10 Data Register 0 Low
CAN_MSGDRH100 0x200442 Message Object 10 Data Register 0 High
CAN_MSGDRL104 0x200444 Message Object 10 Data Register 4 Low
CAN_MSGDRH104 0x200446 Message Object 10 Data Register 4 High
CAN_MSGARL10 0x200448 Message Object 10 Arbitration Register Low
CAN_MSGARH10 0x20044A Message Object 10 Arbitration Register High
CAN_MSGAMRL10 0x20044C Message Object 10 Arbitration Mask Register Low
CAN_MSGAMRH10 0x20044E Message Object 10 Arbitration Mask Register High
CAN_MSGCTRL10 0x200450 Message Object 10 Message Control Register Low
CAN_MSGCTRH10 0x200452 Message Object 10 Message Control Register High
CAN_MSGCFGL10 0x200454 Message Object 10 Message Configuration Register Low
CAN_MSGCFGH10 0x200456 Message Object 10 Message Configuration Register High
CAN_MSGFGCRL10 0x200458 Message Object 10 FIFO/Gateway Control Register Low
CAN_MSGFGCRH10 0x20045A Message Object 10 FIFO/Gateway Control Register High
CAN_MSGDRL110 0x200460 Message Object 11 Data Register 0 Low
CAN_MSGDRH110 0x200462 Message Object 11 Data Register 0 High
CAN_MSGDRL114 0x200464 Message Object 11 Data Register 4 Low
CAN_MSGDRH114 0x200466 Message Object 11 Data Register 4 High
CAN_MSGARL11 0x200468 Message Object 11 Arbitration Register Low
CAN_MSGARH11 0x20046A Message Object 11 Arbitration Register High
CAN_MSGAMRL11 0x20046C Message Object 11 Arbitration Mask Register Low
CAN_MSGAMRH11 0x20046E Message Object 11 Arbitration Mask Register High
CAN_MSGCTRL11 0x200470 Message Object 11 Message Control Register Low
CAN_MSGCTRH11 0x200472 Message Object 11 Message Control Register High
CAN_MSGCFGL11 0x200474 Message Object 11 Message Configuration Register Low
CAN_MSGCFGH11 0x200476 Message Object 11 Message Configuration Register High
CAN_MSGFGCRL11 0x200478 Message Object 11 FIFO/Gateway Control Register Low
CAN_MSGFGCRH11 0x20047A Message Object 11 FIFO/Gateway Control Register High
CAN_MSGDRL120 0x200480 Message Object 12 Data Register 0 Low
CAN_MSGDRH120 0x200482 Message Object 12 Data Register 0 High
CAN_MSGDRL124 0x200484 Message Object 12 Data Register 4 Low
CAN_MSGDRH124 0x200486 Message Object 12 Data Register 4 High
CAN_MSGARL12 0x200488 Message Object 12 Arbitration Register Low
CAN_MSGARH12 0x20048A Message Object 12 Arbitration Register High
CAN_MSGAMRL12 0x20048C Message Object 12 Arbitration Mask Register Low
CAN_MSGAMRH12 0x20048E Message Object 12 Arbitration Mask Register High
CAN_MSGCTRL12 0x200490 Message Object 12 Message Control Register Low
CAN_MSGCTRH12 0x200492 Message Object 12 Message Control Register High
CAN_MSGCFGL12 0x200494 Message Object 12 Message Configuration Register Low
CAN_MSGCFGH12 0x200496 Message Object 12 Message Configuration Register High
CAN_MSGFGCRL12 0x200498 Message Object 12 FIFO/Gateway Control Register Low
CAN_MSGFGCRH12 0x20049A Message Object 12 FIFO/Gateway Control Register High
CAN_MSGDRL130 0x2004A0 Message Object 13 Data Register 0 Low
CAN_MSGDRH130 0x2004A2 Message Object 13 Data Register 0 High
CAN_MSGDRL134 0x2004A4 Message Object 13 Data Register 4 Low
CAN_MSGDRH134 0x2004A6 Message Object 13 Data Register 4 High
CAN_MSGARL13 0x2004A8 Message Object 13 Arbitration Register Low
CAN_MSGARH13 0x2004AA Message Object 13 Arbitration Register High
CAN_MSGAMRL13 0x2004AC Message Object 13 Arbitration Mask Register Low
CAN_MSGAMRH13 0x2004AE Message Object 13 Arbitration Mask Register High
CAN_MSGCTRL13 0x2004B0 Message Object 13 Message Control Register Low
CAN_MSGCTRH13 0x2004B2 Message Object 13 Message Control Register High
CAN_MSGCFGL13 0x2004B4 Message Object 13 Message Configuration Register Low
CAN_MSGCFGH13 0x2004B6 Message Object 13 Message Configuration Register High
CAN_MSGFGCRL13 0x2004B8 Message Object 13 FIFO/Gateway Control Register Low
CAN_MSGFGCRH13 0x2004BA Message Object 13 FIFO/Gateway Control Register High
CAN_MSGDRL140 0x2004C0 Message Object 14 Data Register 0 Low
CAN_MSGDRH140 0x2004C2 Message Object 14 Data Register 0 High
CAN_MSGDRL144 0x2004C4 Message Object 14 Data Register 4 Low
CAN_MSGDRH144 0x2004C6 Message Object 14 Data Register 4 High
CAN_MSGARL14 0x2004C8 Message Object 14 Arbitration Register Low
CAN_MSGARH14 0x2004CA Message Object 14 Arbitration Register High
CAN_MSGAMRL14 0x2004CC Message Object 14 Arbitration Mask Register Low
CAN_MSGAMRH14 0x2004CE Message Object 14 Arbitration Mask Register High
CAN_MSGCTRL14 0x2004D0 Message Object 14 Message Control Register Low
CAN_MSGCTRH14 0x2004D2 Message Object 14 Message Control Register High
CAN_MSGCFGL14 0x2004D4 Message Object 14 Message Configuration Reg Low
CAN_MSGCFGH14 0x2004D6 Message Object 14 Message Configuration Register High
CAN_MSGFGCRL14 0x2004D8 Message Object 14 FIFO/Gateway Control Register Low
CAN_MSGFGCRH14 0x2004DA Message Object 14 FIFO/Gateway Control Register High
CAN_MSGDRL150 0x2004E0 Message Object 15 Data Register 0 Low
CAN_MSGDRH150 0x2004E2 Message Object 15 Data Register 0 High
CAN_MSGDRL154 0x2004E4 Message Object 15 Data Register 4 Low
CAN_MSGDRH154 0x2004E6 Message Object 15 Data Register 4 High
CAN_MSGARL15 0x2004E8 Message Object 15 Arbitration Register Low
CAN_MSGARH15 0x2004EA Message Object 15 Arbitration Register High
CAN_MSGAMRL15 0x2004EC Message Object 15 Arbitration Mask Register Low
CAN_MSGAMRH15 0x2004EE Message Object 15 Arbitration Mask Register High
CAN_MSGCTRL15 0x2004F0 Message Object 15 Message Control Register Low
CAN_MSGCTRH15 0x2004F2 Message Object 15 Message Control Register High
CAN_MSGCFGL15 0x2004F4 Message Object 15 Message Configuration Register Low
CAN_MSGCFGH15 0x2004F6 Message Object 15 Message Configuration Register High
CAN_MSGFGCRL15 0x2004F8 Message Object 15 FIFO/Gateway Control Register Low
CAN_MSGFGCRH15 0x2004FA Message Object 15 FIFO/Gateway Control Register High
CAN_MSGDRL160 0x200500 Message Object 16 Data Register 0 Low
CAN_MSGDRH160 0x200502 Message Object 16 Data Register 0 High
CAN_MSGDRL164 0x200504 Message Object 16 Data Register 4 Low
CAN_MSGDRH164 0x200506 Message Object 16 Data Register 4 High
CAN_MSGARL16 0x200508 Message Object 16 Arbitration Register Low
CAN_MSGARH16 0x20050A Message Object 16 Arbitration Register High
CAN_MSGAMRL16 0x20050C Message Object 16 Arbitration Mask Register Low
CAN_MSGAMRH16 0x20050E Message Object 16 Arbitration Mask Register High
CAN_MSGCTRL16 0x200510 Message Object 16 Message Control Register Low
CAN_MSGCTRH16 0x200512 Message Object 16 Message Control Register High
CAN_MSGCFGL16 0x200514 Message Object 16 Message Configuration Register Low
CAN_MSGCFGH16 0x200516 Message Object 16 Message Configuration Register High
CAN_MSGFGCRL16 0x200518 Message Object 16 FIFO/Gateway Control Register Low
CAN_MSGFGCRH16 0x20051A Message Object 16 FIFO/Gateway Control Register High
CAN_MSGDRL170 0x200520 Message Object 17 Data Register 0 Low
CAN_MSGDRH170 0x200522 Message Object 17 Data Register 0 High
CAN_MSGDRL174 0x200524 Message Object 17 Data Register 4 Low
CAN_MSGDRH174 0x200526 Message Object 17 Data Register 4 High
CAN_MSGARL17 0x200528 Message Object 17 Arbitration Register Low
CAN_MSGARH17 0x20052A Message Object 17 Arbitration Register High
CAN_MSGAMRL17 0x20052C Message Object 17 Arbitration Mask Register Low
CAN_MSGAMRH17 0x20052E Message Object 17 Arbitration Mask Register High
CAN_MSGCTRL17 0x200530 Message Object 17 Message Control Register Low
CAN_MSGCTRH17 0x200532 Message Object 17 Message Control Register High
CAN_MSGCFGL17 0x200534 Message Object 17 Message Configuration Register Low
CAN_MSGCFGH17 0x200536 Message Object 17 Message Configuration Register High
CAN_MSGFGCRL17 0x200538 Message Object 17 FIFO/Gateway Control Register Low
CAN_MSGFGCRH17 0x20053A Message Object 17 FIFO/Gateway Control Register High
CAN_MSGDRL180 0x200540 Message Object 18 Data Register 0 Low
CAN_MSGDRH180 0x200542 Message Object 18 Data Register 0 High
CAN_MSGDRL184 0x200544 Message Object 18 Data Register 4 Low
CAN_MSGDRH184 0x200546 Message Object 18 Data Register 4 High
CAN_MSGARL18 0x200548 Message Object 18 Arbitration Register Low
CAN_MSGARH18 0x20054A Message Object 18 Arbitration Register High
CAN_MSGAMRL18 0x20054C Message Object 18 Arbitration Mask Register Low
CAN_MSGAMRH18 0x20054E Message Object 18 Arbitration Mask Register High
CAN_MSGCTRL18 0x200550 Message Object 18 Message Control Register Low
CAN_MSGCTRH18 0x200552 Message Object 18 Message Control Register High
CAN_MSGCFGL18 0x200554 Message Object 18 Message Configuration Register Low
CAN_MSGCFGH18 0x200556 Message Object 18 Message Configuration Register High
CAN_MSGFGCRL18 0x200558 Message Object 18 FIFO/Gateway Control Register Low
CAN_MSGFGCRH18 0x20055A Message Object 18 FIFO/Gateway Control Register High
CAN_MSGDRL190 0x200560 Message Object 19 Data Register 0 Low
CAN_MSGDRH190 0x200562 Message Object 19 Data Register 0 High
CAN_MSGDRL194 0x200564 Message Object 19 Data Register 4 Low
CAN_MSGDRH194 0x200566 Message Object 19 Data Register 4 High
CAN_MSGARL19 0x200568 Message Object 19 Arbitration Register Low
CAN_MSGARH19 0x20056A Message Object 19 Arbitration Register High
CAN_MSGAMRL19 0x20056C Message Object 19 Arbitration Mask Register Low
CAN_MSGAMRH19 0x20056E Message Object 19 Arbitration Mask Register High
CAN_MSGCTRL19 0x200570 Message Object 19 Message Control Register Low
CAN_MSGCTRH19 0x200572 Message Object 19 Message Control Register High
CAN_MSGCFGL19 0x200574 Message Object 19 Message Configuration Register Low
CAN_MSGCFGH19 0x200576 Message Object 19 Message Configuration Register High
CAN_MSGFGCRL19 0x200578 Message Object 19 FIFO/Gateway Control Register Low
CAN_MSGFGCRH19 0x20057A Message Object 19 FIFO/Gateway Control Register High
CAN_MSGDRL200 0x200580 Message Object 20 Data Register 0 Low
CAN_MSGDRH200 0x200582 Message Object 20 Data Register 0 High
CAN_MSGDRL204 0x200584 Message Object 20 Data Register 4 Low
CAN_MSGDRH204 0x200586 Message Object 20 Data Register 4 High
CAN_MSGARL20 0x200588 Message Object 20 Arbitration Register Low
CAN_MSGARH20 0x20058A Message Object 20 Arbitration Register High
CAN_MSGAMRL20 0x20058C Message Object 20 Arbitration Mask Register Low
CAN_MSGAMRH20 0x20058E Message Object 20 Arbitration Mask Register High
CAN_MSGCTRL20 0x200590 Message Object 20 Message Control Register Low
CAN_MSGCTRH20 0x200592 Message Object 20 Message Control Register High
CAN_MSGCFGL20 0x200594 Message Object 20 Message Configuration Register Low
CAN_MSGCFGH20 0x200596 Message Object 20 Message Configuration Register High
CAN_MSGFGCRL20 0x200598 Message Object 20 FIFO/Gateway Control Register Low
CAN_MSGFGCRH20 0x20059A Message Object 20 FIFO/Gateway Control Register High
CAN_MSGDRL210 0x2005A0 Message Object 21 Data Register 0 Low
CAN_MSGDRH210 0x2005A2 Message Object 21 Data Register 0 High
CAN_MSGDRL214 0x2005A4 Message Object 21 Data Register 4 Low
CAN_MSGDRH214 0x2005A6 Message Object 21 Data Register 4 High
CAN_MSGARL21 0x2005A8 Message Object 21 Arbitration Register Low
CAN_MSGARH21 0x2005AA Message Object 21 Arbitration Register High
CAN_MSGAMRL21 0x2005AC Message Object 21 Arbitration Mask Register Low
CAN_MSGAMRH21 0x2005AE Message Object 21 Arbitration Mask Register High
CAN_MSGCTRL21 0x2005B0 Message Object 21 Message Control Register Low
CAN_MSGCTRH21 0x2005B2 Message Object 21 Message Control Register High
CAN_MSGCFGL21 0x2005B4 Message Object 21 Message Configuration Register Low
CAN_MSGCFGH21 0x2005B6 Message Object 21 Message Configuration Register High
CAN_MSGFGCRL21 0x2005B8 Message Object 21 FIFO/Gateway Control Register Low
CAN_MSGFGCRH21 0x2005BA Message Object 21 FIFO/Gateway Control Register High
CAN_MSGDRL220 0x2005C0 Message Object 22 Data Register 0 Low
CAN_MSGDRH220 0x2005C2 Message Object 22 Data Register 0 High
CAN_MSGDRL224 0x2005C4 Message Object 22 Data Register 4 Low
CAN_MSGDRH224 0x2005C6 Message Object 22 Data Register 4 High
CAN_MSGARL22 0x2005C8 Message Object 22 Arbitration Register Low
CAN_MSGARH22 0x2005CA Message Object 22 Arbitration Register High
CAN_MSGAMRL22 0x2005CC Message Object 22 Arbitration Mask Register Low
CAN_MSGAMRH22 0x2005CE Message Object 22 Arbitration Mask Register High
CAN_MSGCTRL22 0x2005D0 Message Object 22 Message Control Register Low
CAN_MSGCTRH22 0x2005D2 Message Object 22 Message Control Register High
CAN_MSGCFGL22 0x2005D4 Message Object 22 Message Configuration Register Low
CAN_MSGCFGH22 0x2005D6 Message Object 22 Message Configuration Register High
CAN_MSGFGCRL22 0x2005D8 Message Object 22 FIFO/Gateway Control Register Low
CAN_MSGFGCRH22 0x2005DA Message Object 22 FIFO/Gateway Control Register High
CAN_MSGDRL230 0x2005E0 Message Object 23 Data Register 0 Low
CAN_MSGDRH230 0x2005E2 Message Object 23 Data Register 0 High
CAN_MSGDRL234 0x2005E4 Message Object 23 Data Register 4 Low
CAN_MSGDRH234 0x2005E6 Message Object 23 Data Register 4 High
CAN_MSGARL23 0x2005E8 Message Object 23 Arbitration Register Low
CAN_MSGARH23 0x2005EA Message Object 23 Arbitration Register High
CAN_MSGAMRL23 0x2005EC Message Object 23 Arbitration Mask Register Low
CAN_MSGAMRH23 0x2005EE Message Object 23 Arbitration Mask Register High
CAN_MSGCTRL23 0x2005F0 Message Object 23 Message Control Register Low
CAN_MSGCTRH23 0x2005F2 Message Object 23 Message Control Register High
CAN_MSGCFGL23 0x2005F4 Message Object 23 Message Configuration Register Low
CAN_MSGCFGH23 0x2005F6 Message Object 23 Message Configuration Register High
CAN_MSGFGCRL23 0x2005F8 Message Object 23 FIFO/Gateway Control Register Low
CAN_MSGFGCRH23 0x2005FA Message Object 23 FIFO/Gateway Control Register High
CAN_MSGDRL240 0x200600 Message Object 24 Data Register 0 Low
CAN_MSGDRH240 0x200602 Message Object 24 Data Register 0 High
CAN_MSGDRL244 0x200604 Message Object 24 Data Register 4 Low
CAN_MSGDRH244 0x200606 Message Object 24 Data Register 4 High
CAN_MSGARL24 0x200608 Message Object 24 Arbitration Register Low
CAN_MSGARH24 0x20060A Message Object 24 Arbitration Register High
CAN_MSGAMRL24 0x20060C Message Object 24 Arbitration Mask Register Low
CAN_MSGAMRH24 0x20060E Message Object 24 Arbitration Mask Register High
CAN_MSGCTRL24 0x200610 Message Object 24 Message Control Register Low
CAN_MSGCTRH24 0x200612 Message Object 24 Message Control Register High
CAN_MSGCFGL24 0x200614 Message Object 24 Message Configuration Register Low
CAN_MSGCFGH24 0x200616 Message Object 24 Message Configuration Register High
CAN_MSGFGCRL24 0x200618 Message Object 24 FIFO/Gateway Control Register Low
CAN_MSGFGCRH24 0x20061A Message Object 24 FIFO/Gateway Control Register High
CAN_MSGDRL250 0x200620 Message Object 25 Data Register 0 Low
CAN_MSGDRH250 0x200622 Message Object 25 Data Register 0 High
CAN_MSGDRL254 0x200624 Message Object 25 Data Register 4 Low
CAN_MSGDRH254 0x200626 Message Object 25 Data Register 4 High
CAN_MSGARL25 0x200628 Message Object 25 Arbitration Register Low
CAN_MSGARH25 0x20062A Message Object 25 Arbitration Register High
CAN_MSGAMRL25 0x20062C Message Object 25 Arbitration Mask Register Low
CAN_MSGAMRH25 0x20062E Message Object 25 Arbitration Mask Register High
CAN_MSGCTRL25 0x200630 Message Object 25 Message Control Register Low
CAN_MSGCTRH25 0x200632 Message Object 25 Message Control Register High
CAN_MSGCFGL25 0x200634 Message Object 25 Message Configuration Register Low
CAN_MSGCFGH25 0x200636 Message Object 25 Message Configuration Register High
CAN_MSGFGCRL25 0x200638 Message Object 25 FIFO/Gateway Control Register Low
CAN_MSGFGCRH25 0x20063A Message Object 25 FIFO/Gateway Control Register High
CAN_MSGDRL260 0x200640 Message Object 26 Data Register 0 Low
CAN_MSGDRH260 0x200642 Message Object 26 Data Register 0 High
CAN_MSGDRL264 0x200644 Message Object 26 Data Register 4 Low
CAN_MSGDRH264 0x200646 Message Object 26 Data Register 4 High
CAN_MSGARL26 0x200648 Message Object 26 Arbitration Register Low
CAN_MSGARH26 0x20064A Message Object 26 Arbitration Register High
CAN_MSGAMRL26 0x20064C Message Object 26 Arbitration Mask Register Low
CAN_MSGAMRH26 0x20064E Message Object 26 Arbitration Mask Register High
CAN_MSGCTRL26 0x200650 Message Object 26 Message Control Register Low
CAN_MSGCTRH26 0x200652 Message Object 26 Message Control Register High
CAN_MSGCFGL26 0x200654 Message Object 26 Message Configuration Register Low
CAN_MSGCFGH26 0x200656 Message Object 26 Message Configuration Register High
CAN_MSGFGCRL26 0x200658 Message Object 26 FIFO/Gateway Control Register Low
CAN_MSGFGCRH26 0x20065A Message Object 26 FIFO/Gateway Control Register High
CAN_MSGDRL270 0x200660 Message Object 27 Data Register 0 Low
CAN_MSGDRH270 0x200662 Message Object 27 Data Register 0 High
CAN_MSGDRL274 0x200664 Message Object 27 Data Register 4 Low
CAN_MSGDRH274 0x200666 Message Object 27 Data Register 4 High
CAN_MSGARL27 0x200668 Message Object 27 Arbitration Register Low
CAN_MSGARH27 0x20066A Message Object 27 Arbitration Register High
CAN_MSGAMRL27 0x20066C Message Object 27 Arbitration Mask Register Low
CAN_MSGAMRH27 0x20066E Message Object 27 Arbitration Mask Register High
CAN_MSGCTRL27 0x200670 Message Object 27 Message Control Register Low
CAN_MSGCTRH27 0x200672 Message Object 27 Message Control Register High
CAN_MSGCFGL27 0x200674 Message Object 27 Message Configuration Register Low
CAN_MSGCFGH27 0x200676 Message Object 27 Message Configuration Register High
CAN_MSGFGCRL27 0x200678 Message Object 27 FIFO/Gateway Control Register Low
CAN_MSGFGCRH27 0x20067A Message Object 27 FIFO/Gateway Control Register High
CAN_MSGDRL280 0x200680 Message Object 28 Data Register 0 Low
CAN_MSGDRH280 0x200682 Message Object 28 Data Register 0 High
CAN_MSGDRL284 0x200684 Message Object 28 Data Register 4 Low
CAN_MSGDRH284 0x200686 Message Object 28 Data Register 4 High
CAN_MSGARL28 0x200688 Message Object 28 Arbitration Register Low
CAN_MSGARH28 0x20068A Message Object 28 Arbitration Register High
CAN_MSGAMRL28 0x20068C Message Object 28 Arbitration Mask Register Low
CAN_MSGAMRH28 0x20068E Message Object 28 Arbitration Mask Register High
CAN_MSGCTRL28 0x200690 Message Object 28 Message Control Register Low
CAN_MSGCTRH28 0x200692 Message Object 28 Message Control Register High
CAN_MSGCFGL28 0x200694 Message Object 28 Message Configuration Register Low
CAN_MSGCFGH28 0x200696 Message Object 28 Message Configuration Register High
CAN_MSGFGCRL28 0x200698 Message Object 28 FIFO/Gateway Control Register Low
CAN_MSGFGCRH28 0x20069A Message Object 28 FIFO/Gateway Control Register High
CAN_MSGDRL290 0x2006A0 Message Object 29 Data Register 0 Low
CAN_MSGDRH290 0x2006A2 Message Object 29 Data Register 0 High
CAN_MSGDRL294 0x2006A4 Message Object 29 Data Register 4 Low
CAN_MSGDRH294 0x2006A6 Message Object 29 Data Register 4 High
CAN_MSGARL29 0x2006A8 Message Object 29 Arbitration Register Low
CAN_MSGARH29 0x2006AA Message Object 29 Arbitration Register High
CAN_MSGAMRL29 0x2006AC Message Object 29 Arbitration Mask Register Low
CAN_MSGAMRH29 0x2006AE Message Object 29 Arbitration Mask Register High
CAN_MSGCTRL29 0x2006B0 Message Object 29 Message Control Register Low
CAN_MSGCTRH29 0x2006B2 Message Object 29 Message Control Register High
CAN_MSGCFGL29 0x2006B4 Message Object 29 Message Configuration Register Low
CAN_MSGCFGH29 0x2006B6 Message Object 29 Message Configuration Register High
CAN_MSGFGCRL29 0x2006B8 Message Object 29 FIFO/Gateway Control Register Low
CAN_MSGFGCRH29 0x2006BA Message Object 29 FIFO/Gateway Control Register High
CAN_MSGDRL300 0x2006C0 Message Object 30 Data Register 0 Low
CAN_MSGDRH300 0x2006C2 Message Object 30 Data Register 0 High
CAN_MSGDRL304 0x2006C4 Message Object 30 Data Register 4 Low
CAN_MSGDRH304 0x2006C6 Message Object 30 Data Register 4 High
CAN_MSGARL30 0x2006C8 Message Object 30 Arbitration Register Low
CAN_MSGARH30 0x2006CA Message Object 30 Arbitration Register High
CAN_MSGAMRL30 0x2006CC Message Object 30 Arbitration Mask Register Low
CAN_MSGAMRH30 0x2006CE Message Object 30 Arbitration Mask Register High
CAN_MSGCTRL30 0x2006D0 Message Object 30 Message Control Register Low
CAN_MSGCTRH30 0x2006D2 Message Object 30 Message Control Register High
CAN_MSGCFGL30 0x2006D4 Message Object 30 Message Configuration Register Low
CAN_MSGCFGH30 0x2006D6 Message Object 30 Message Configuration Register High
CAN_MSGFGCRL30 0x2006D8 Message Object 30 FIFO/Gateway Control Register Low
CAN_MSGFGCRH30 0x2006DA Message Object 30 FIFO/Gateway Control Register High
CAN_MSGDRL310 0x2006E0 Message Object 31 Data Register 0 Low
CAN_MSGDRH310 0x2006E2 Message Object 31 Data Register 0 High
CAN_MSGDRL314 0x2006E4 Message Object 31 Data Register 4 Low
CAN_MSGDRH314 0x2006E6 Message Object 31 Data Register 4 High
CAN_MSGARL31 0x2006E8 Message Object 31 Arbitration Register Low
CAN_MSGARH31 0x2006EA Message Object 31 Arbitration Register High
CAN_MSGAMRL31 0x2006EC Message Object 31 Arbitration Mask Register Low
CAN_MSGAMRH31 0x2006EE Message Object 31 Arbitration Mask Register High
CAN_MSGCTRL31 0x2006F0 Message Object 31 Message Control Register Low
CAN_MSGCTRH31 0x2006F2 Message Object 31 Message Control Register High
CAN_MSGCFGL31 0x2006F4 Message Object 31 Message Configuration Register Low
CAN_MSGCFGH31 0x2006F6 Message Object 31 Message Configuration Register High
CAN_MSGFGCRL31 0x2006F8 Message Object 31 FIFO/Gateway Control Register Low
CAN_MSGFGCRH31 0x2006FA Message Object 31 FIFO/Gateway Control Register High
.XC167CI
; MEMORY MAP
area DATA EXT_MEM 0x0000:0x8000 External Memory
area BSS RESERVED 0x8000:0xC000 Reserved for Internal Data SRAM
area DATA IRAM 0xC000:0xD000
area BSS RESERVED 0xD000:0xE000
area BSS RESERVED 0xE000:0xE600
area DATA XSFR_1 0xE600:0xEA00 XSFR Area
area BSS RESERVED 0xEA00:0xEC00
area DATA XSFR_2 0xEC00:0xF000 XSFR Area
area DATA E_SFR 0xF000:0xF200
area BSS RESERVED 0xF200:0xF600 Reserved for DPRAM
area DATA DPRAM 0xF600:0xFE00
area DATA SFR 0xFE00:0x10000 SFR Area
; Interrupt and reset vector assignments
entry RESET_ 0x0000 RESET
entry NMITRAP_ 0x0008 Non-Maskable Interrupt (Class A Hardware Traps)
entry STOTRAP_ 0x0010 Stack Overflow (Class A Hardware Traps)
entry STUTRAP_ 0x0018 Stack Underflow (Class A Hardware Traps)
entry SBRKTRAP_ 0x0020 Software Break (Class A Hardware Traps)
entry BTRAP_ 0x0028 BTRAP (Class B Hardware Traps)
entry CC1_CC0IC_ 0x0040 CAPCOM Register 0
entry CC1_CC1IC_ 0x0044 CAPCOM Register 1
entry CC1_CC2IC_ 0x0048 CAPCOM Register 2
entry CC1_CC3IC_ 0x004C CAPCOM Register 3
entry CC1_CC4IC_ 0x0050 CAPCOM Register 4
entry CC1_CC5IC_ 0x0054 CAPCOM Register 5
entry CC1_CC6IC_ 0x0058 CAPCOM Register 6
entry CC1_CC7IC_ 0x005C CAPCOM Register 7
entry CC1_CC8IC_ 0x0060 CAPCOM Register 8
entry CC1_CC9IC_ 0x0064 CAPCOM Register 9
entry CC1_CC10IC_ 0x0068 CAPCOM Register 10
entry CC1_CC11IC_ 0x006C CAPCOM Register 11
entry CC1_CC12IC_ 0x0070 CAPCOM Register 12
entry CC1_CC13IC_ 0x0074 CAPCOM Register 13
entry CC1_CC14IC_ 0x0078 CAPCOM Register 14
entry CC1_CC15IC_ 0x007C CAPCOM Register 15
entry CC1_T0IC_ 0x0080 CAPCOM Timer 0
entry CC1_T1IC_ 0x0084 CAPCOM Timer 1
entry GPT12E_T2IC_ 0x0088 GPT1 Timer 2
entry GPT12E_T3IC_ 0x008C GPT1 Timer 3
entry GPT12E_T4IC_ 0x0090 GPT1 Timer 4
entry GPT12E_T5IC_ 0x0094 GPT2 Timer 5
entry GPT12E_T6IC_ 0x0098 GPT2 Timer 6
entry GPT12E_CRIC_ 0x009C GPT2 CAPREL Reg.
entry ADC_CIC_ 0x00A0 A/D Conversion Compl.
entry ADC_EIC_ 0x00A4 A/D Overrun Error
entry ASC0_TIC_ 0x00A8 ASC0 Transmit
entry ASC0_RIC_ 0x00AC ASC0 Receive
entry ASC0_EIC_ 0x00B0 ASC0 Error
entry SSC0_TIC_ 0x00B4 SSC0 Transmit
entry SSC0_RIC_ 0x00B8 SSC0 Receive
entry SSC0_EIC_ 0x00BC SSC0 Error
entry CC2_CC16IC_ 0x00C0 CAPCOM Register 16
entry CC2_CC17IC_ 0x00C4 CAPCOM Register 17
entry CC2_CC18IC_ 0x00C8 CAPCOM Register 18
entry CC2_CC19IC_ 0x00CC CAPCOM Register 19
entry CC2_CC20IC_ 0x00D0 CAPCOM Register 20
entry CC2_CC21IC_ 0x00D4 CAPCOM Register 21
entry CC2_CC22IC_ 0x00D8 CAPCOM Register 22
entry CC2_CC23IC_ 0x00DC CAPCOM Register 23
entry CC2_CC24IC_ 0x00E0 CAPCOM Register 24
entry CC2_CC25IC_ 0x00E4 CAPCOM Register 25
entry CC2_CC26IC_ 0x00E8 CAPCOM Register 26
entry CC2_CC27IC_ 0x00EC CAPCOM Register 27
entry CC2_CC28IC_ 0x00F0 CAPCOM Register 28
entry CC2_T7IC_ 0x00F4 CAPCOM Timer 7
entry GG2_T8IC_ 0x00F8 CAPCOM Timer 8
entry ASC1_ABIC_ 0x0108 ASC1 Autobaud
entry PLLIC_ 0x010C PLL/OWD
entry CC2_CC29IC_ 0x0110 CAPCOM Register 29
entry CC2_CC30IC_ 0x0114 CAPCOM Register 30
entry CC2_CC31IC_ 0x0118 CAPCOM Register 31
entry ASC0_TBIC_ 0x011C ASC0 Transmit Buffer
entry ASC1_TIC_ 0x0120 ASC1 Transmit 2
entry ASC1_RIC_ 0x0124 ASC1 Receive
entry ASC1_EIC_ 0x0128 ASC1 Error
entry EOPIC_ 0x0130 End of PEC Subch.
entry CCU6_T12IC_ 0x0134 CAPCOM6 Timer T12
entry CCU6_T13IC_ 0x0138 CAPCOM6 Timer T13
entry CCU6_EIC_ 0x013C CAPCOM6 Emergency
entry CCU6_IC_ 0x0140 CAPCOM6
entry SSC1_TIC_ 0x0144 SSC1 Transmit
entry SSC1_RIC_ 0x0148 SSC1 Receive
entry SSC1_EIC_ 0x014C SSC1 Error
entry CAN_0IC_ 0x0150 CAN0
entry CAN_1IC_ 0x0154 CAN1
entry CAN_2IC_ 0x0158 CAN2
entry CAN_3IC_ 0x015C CAN3
entry CAN_4IC_ 0x0164 CAN4
entry CAN_5IC_ 0x0168 CAN5
entry CAN_6IC_ 0x016C CAN6
entry CAN_7IC_ 0x0170 CAN7
entry RTC_IC_ 0x0174 RTC
entry ASC1_TBIC_ 0x0178 ASC1 Transmit Buffer
entry ASC0_ABIC_ 0x017C ASC0 Autobaud
; INPUT/OUTPUT PORTS
; Addressing Modes to Access Word-GPRs (p.100)
; R0 General Purpose Register 0
; R0 General Purpose Register 0
; R1 General Purpose Register 1
; R1 General Purpose Register 1
; R10 General Purpose Register 10
; R10 General Purpose Register 10
; R11 General Purpose Register 11
; R11 General Purpose Register 11
; R12 General Purpose Register 12
; R12 General Purpose Register 12
; R13 General Purpose Register 13
; R13 General Purpose Register 13
; R14 General Purpose Register 14
; R14 General Purpose Register 14
; R15 General Purpose Register 15
; R15 General Purpose Register 15
; R2 General Purpose Register 2
; R2 General Purpose Register 2
; R3 General Purpose Register 3
; R3 General Purpose Register 3
; R4 General Purpose Register 4
; R4 General Purpose Register 4
; R5 General Purpose Register 5
; R5 General Purpose Register 5
; R6 General Purpose Register 6
; R6 General Purpose Register 6
; R7 General Purpose Register 7
; R7 General Purpose Register 7
; R8 General Purpose Register 8
; R8 General Purpose Register 8
; R9 General Purpose Register 9
; R9 General Purpose Register 9
IIC_CFG 0xE600 IIC Configuration Register
IIC_CON 0xE602 IIC Control Register
IIC_ST 0xE604 IIC Status Register
IIC_ADR 0xE606 IIC Address Register
IIC_RTBL 0xE608 IIC Receive/Transmit Buffer Low Register
IIC_RTBH 0xE60A IIC Receive/Transmit Buffer High Register
IIC_ID 0xE60C IIC Module Identification Register
CCU6_PISEL 0xE884 Port Input Select Register
CCU6_ID 0xE888 Module Identification Register
CCU6_T12 0xE890 Timer T12 Counter Register
CCU6_T12PR 0xE892 Timer 12 Period Register
CCU6_T12DTC 0xE894 Dead-Time Control Register for Timer 12
CCU6_CC60R 0xE898 Capture/Compare Register for Channel CC60
CCU6_CC61R 0xE89A Capture/Compare Register for Channel CC61
CCU6_CC62R 0xE89C Capture/Compare Register for Channel CC62
CCU6_CC60SR 0xE8A0 Capture/Compare Shadow Register for Channel 0
CCU6_CC61SR 0xE8A2 Capture/Compare Shadow Register for Channel 1
CCU6_CC62SR 0xE8A4 Capture/Compare Shadow Register for Channel 2
CCU6_TCTR4 0xE8A6 Timer Control Register 4
CCU6_CMPSTAT 0xE8A8 Compare Status Register
CCU6_CMPMODIF 0xE8AA Compare State Modification Register
CCU6_TCTR0 0xE8AC Timer Control Register 0
CCU6_TCTR2 0xE8AE Timer Control Register 2
CCU6_T13 0xE8B0 Timer T13 Counter Register
CCU6_T13PR 0xE8B2 Timer 13 Period Register
CCU6_CC63R 0xE8B4 Compare Register for Channel CC63
CCU6_CC63SR 0xE8B6 Compare Shadow Register for Channel CC63
CCU6_MODCTR 0xE8C0 Modulation Control Register
CCU6_TRPCTR 0xE8C2 Trap Control Register
CCU6_PSLR 0xE8C4 Passive State Level Register
CCU6_T12MSEL 0xE8C6 T12 Capture/Compare Mode Select Register
CCU6_MCMOUTS 0xE8CA Multi-Channel Mode Output Shadow Register
CCU6_MCMOUT 0xE8CC Multi-Channel Mode Output Register
CCU6_MCMCTR 0xE8CE Multi-Channel Mode Control Register
CCU6_IS 0xE8D0 Capture/Compare Interrupt Status Register
CCU6_ISS 0xE8D2 Capture/Compare Interrupt Status Set Register
CCU6_ISR 0xE8D4 Capture/Compare Interrupt Status Reset Register
CCU6_INP 0xE8D6 Capture/Compare Interrupt Node Pointer Register
CCU6_IEN 0xE8D8 Capture/Compare Interrupt Enable Register
SDLM_PISEL 0xE904 SDLM Port Input Select Register
SDLM_ID 0xE908 SDLM Module Identification Register
SDLM_GLOBCON 0xE910 Global Control Register
SDLM_CLKDIV 0xE914 Clock Divider Register
SDLM_TXDELAY 0xE916 Transceiver Delay Register
SDLM_IFRVAL 0xE918 In-Frame Response Value Register
SDLM_BUFFSTAT 0xE91C Buffer Status Register
SDLM_TRANSSTAT 0xE91E Transfer Register
SDLM_BUSSTAT 0xE920 Bus Status Register
SDLM_ERRSTAT 0xE922 Error Status Register
SDLM_BUFFCON 0xE924 Buffer Control Register
SDLM_FLAGRST 0xE928 Flag Reset Register
SDLM_INTCON 0xE92C Interrupt Control Register
SDLM_TXD0 0xE930 Transmit Data Register
SDLM_TXD2 0xE932 Transmit Data Register
SDLM_TXD4 0xE934 Transmit Data Register
SDLM_TXD6 0xE936 Transmit Data Register
SDLM_TXD8 0xE938 Transmit Data Register
SDLM_TXD10 0xE93A Transmit Data Register
SDLM_TXCNT 0xE93C Bus Transmit Byte Counter
SDLM_TXCPU 0xE93E CPU Transmit Byte Counter
SDLM_RXD00 0xE940 Receive Data Register
SDLM_RXD02 0xE942 Receive Data Register
SDLM_RXD04 0xE944 Receive Data Register
SDLM_RXD06 0xE946 Receive Data Register
SDLM_RXD08 0xE948 Receive Data Register
SDLM_RXD010 0xE94A Receive Data Register
SDLM_RXCNT 0xE94C Bus Receive Byte Counter
SDLM_RXCPU 0xE94E CPU Receive Byte Counter
SDLM_RXD10 0xE950 Receive Data Register
SDLM_RXD12 0xE952 Receive Data Register
SDLM_RXD14 0xE954 Receive Data Register
SDLM_RXD16 0xE956 Receive Data Register
SDLM_RXD18 0xE958 Receive Data Register
SDLM_RXD110 0xE95A Receive Data Register
SDLM_RXCNTB 0xE95C Bus Receive Byte Counter Register (on bus side)
SDLM_SOFPTR 0xE960 Start-of-Frame Pointer Register
FINT0CSP 0xEC00 Fast Interrupt Control Register 0
FINT0CSP.EN 15 Fast Interrupt Enable
FINT0CSP.GPX 12 Group Priority Extension
FINT0CSP.ILVL_11 11 Interrupt Priority Level bit 11
FINT0CSP.ILVL_10 10 Interrupt Priority Level bit 10
FINT0CSP.GLVL_9 9 Group Priority Level bit 9
FINT0CSP.GLVL_8 8 Group Priority Level bit 8
FINT0CSP.SEG_7 7 Segment Number of Interrupt Service Routine bit 7
FINT0CSP.SEG_6 6 Segment Number of Interrupt Service Routine bit 6
FINT0CSP.SEG_5 5 Segment Number of Interrupt Service Routine bit 5
FINT0CSP.SEG_4 4 Segment Number of Interrupt Service Routine bit 4
FINT0CSP.SEG_3 3 Segment Number of Interrupt Service Routine bit 3
FINT0CSP.SEG_2 2 Segment Number of Interrupt Service Routine bit 2
FINT0CSP.SEG_1 1 Segment Number of Interrupt Service Routine bit 1
FINT0CSP.SEG_0 0 Segment Number of Interrupt Service Routine bit 0
FINT0ADDR 0xEC02 Fast Interrupt Address Register 0
FINT0ADDR.ADDR_15 15 Address of Interrupt Service Routine bit 15
FINT0ADDR.ADDR_14 14 Address of Interrupt Service Routine bit 14
FINT0ADDR.ADDR_13 13 Address of Interrupt Service Routine bit 13
FINT0ADDR.ADDR_12 12 Address of Interrupt Service Routine bit 12
FINT0ADDR.ADDR_11 11 Address of Interrupt Service Routine bit 11
FINT0ADDR.ADDR_10 10 Address of Interrupt Service Routine bit 10
FINT0ADDR.ADDR_9 9 Address of Interrupt Service Routine bit 9
FINT0ADDR.ADDR_8 8 Address of Interrupt Service Routine bit 8
FINT0ADDR.ADDR_7 7 Address of Interrupt Service Routine bit 7
FINT0ADDR.ADDR_6 6 Address of Interrupt Service Routine bit 6
FINT0ADDR.ADDR_5 5 Address of Interrupt Service Routine bit 5
FINT0ADDR.ADDR_4 4 Address of Interrupt Service Routine bit 4
FINT0ADDR.ADDR_3 3 Address of Interrupt Service Routine bit 3
FINT0ADDR.ADDR_2 2 Address of Interrupt Service Routine bit 2
FINT0ADDR.ADDR_1 1 Address of Interrupt Service Routine bit 1
FINT1CSP 0xEC04 Fast Interrupt Control Register 1
FINT1CSP.EN 15 Fast Interrupt Enable
FINT1CSP.GPX 12 Group Priority Extension
FINT1CSP.ILVL_11 11 Interrupt Priority Level bit 11
FINT1CSP.ILVL_10 10 Interrupt Priority Level bit 10
FINT1CSP.GLVL_9 9 Group Priority Level bit 9
FINT1CSP.GLVL_8 8 Group Priority Level bit 8
FINT1CSP.SEG_7 7 Segment Number of Interrupt Service Routine bit 7
FINT1CSP.SEG_6 6 Segment Number of Interrupt Service Routine bit 6
FINT1CSP.SEG_5 5 Segment Number of Interrupt Service Routine bit 5
FINT1CSP.SEG_4 4 Segment Number of Interrupt Service Routine bit 4
FINT1CSP.SEG_3 3 Segment Number of Interrupt Service Routine bit 3
FINT1CSP.SEG_2 2 Segment Number of Interrupt Service Routine bit 2
FINT1CSP.SEG_1 1 Segment Number of Interrupt Service Routine bit 1
FINT1CSP.SEG_0 0 Segment Number of Interrupt Service Routine bit 0
FINT1ADDR 0xEC06 Fast Interrupt Address Register 1
FINT1ADDR.ADDR_15 15 Address of Interrupt Service Routine bit 15
FINT1ADDR.ADDR_14 14 Address of Interrupt Service Routine bit 14
FINT1ADDR.ADDR_13 13 Address of Interrupt Service Routine bit 13
FINT1ADDR.ADDR_12 12 Address of Interrupt Service Routine bit 12
FINT1ADDR.ADDR_11 11 Address of Interrupt Service Routine bit 11
FINT1ADDR.ADDR_10 10 Address of Interrupt Service Routine bit 10
FINT1ADDR.ADDR_9 9 Address of Interrupt Service Routine bit 9
FINT1ADDR.ADDR_8 8 Address of Interrupt Service Routine bit 8
FINT1ADDR.ADDR_7 7 Address of Interrupt Service Routine bit 7
FINT1ADDR.ADDR_6 6 Address of Interrupt Service Routine bit 6
FINT1ADDR.ADDR_5 5 Address of Interrupt Service Routine bit 5
FINT1ADDR.ADDR_4 4 Address of Interrupt Service Routine bit 4
FINT1ADDR.ADDR_3 3 Address of Interrupt Service Routine bit 3
FINT1ADDR.ADDR_2 2 Address of Interrupt Service Routine bit 2
FINT1ADDR.ADDR_1 1 Address of Interrupt Service Routine bit 1
BNKSEL0 0xEC20 Register Bank Selection Register 0 (??? p.206)
BNKSEL0.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL0.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL0.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL0.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL0.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL0.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL0.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL0.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL0.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL0.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL0.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL0.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL0.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL0.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL0.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL0.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL1 0xEC22 Register Bank Selection Register 1
BNKSEL1.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL1.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL1.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL1.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL1.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL1.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL1.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL1.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL1.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL1.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL1.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL1.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL1.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL1.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL1.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL1.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL2 0xEC24 Register Bank Selection Register 2
BNKSEL2.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL2.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL2.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL2.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL2.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL2.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL2.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL2.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL2.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL2.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL2.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL2.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL2.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL2.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL2.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL2.GPRSEL0_0 0 Register Bank Selection 0_0
BNKSEL3 0xEC26 Register Bank Selection Register 3
BNKSEL3.GPRSEL7_15 15 Register Bank Selection 7_15
BNKSEL3.GPRSEL7_14 14 Register Bank Selection 7_14
BNKSEL3.GPRSEL6_13 13 Register Bank Selection 6_13
BNKSEL3.GPRSEL6_12 12 Register Bank Selection 6_12
BNKSEL3.GPRSEL5_11 11 Register Bank Selection 5_11
BNKSEL3.GPRSEL5_10 10 Register Bank Selection 5_10
BNKSEL3.GPRSEL4_9 9 Register Bank Selection 4_9
BNKSEL3.GPRSEL4_8 8 Register Bank Selection 4_8
BNKSEL3.GPRSEL3_7 7 Register Bank Selection 3_7
BNKSEL3.GPRSEL3_6 6 Register Bank Selection 3_6
BNKSEL3.GPRSEL2_5 5 Register Bank Selection 2_5
BNKSEL3.GPRSEL2_4 4 Register Bank Selection 2_4
BNKSEL3.GPRSEL1_3 3 Register Bank Selection 1_3
BNKSEL3.GPRSEL1_2 2 Register Bank Selection 1_2
BNKSEL3.GPRSEL0_1 1 Register Bank Selection 0_1
BNKSEL3.GPRSEL0_0 0 Register Bank Selection 0_0
SRCP0 0xEC40 PEC Channel 0 Source Pointer
SRCP0.SRCP0_15 15 Source Pointer Address of Channel 0 bit 15
SRCP0.SRCP0_14 14 Source Pointer Address of Channel 0 bit 14
SRCP0.SRCP0_13 13 Source Pointer Address of Channel 0 bit 13
SRCP0.SRCP0_12 12 Source Pointer Address of Channel 0 bit 12
SRCP0.SRCP0_11 11 Source Pointer Address of Channel 0 bit 11
SRCP0.SRCP0_10 10 Source Pointer Address of Channel 0 bit 10
SRCP0.SRCP0_9 9 Source Pointer Address of Channel 0 bit 9
SRCP0.SRCP0_8 8 Source Pointer Address of Channel 0 bit 8
SRCP0.SRCP0_7 7 Source Pointer Address of Channel 0 bit 7
SRCP0.SRCP0_6 6 Source Pointer Address of Channel 0 bit 6
SRCP0.SRCP0_5 5 Source Pointer Address of Channel 0 bit 5
SRCP0.SRCP0_4 4 Source Pointer Address of Channel 0 bit 4
SRCP0.SRCP0_3 3 Source Pointer Address of Channel 0 bit 3
SRCP0.SRCP0_2 2 Source Pointer Address of Channel 0 bit 2
SRCP0.SRCP0_1 1 Source Pointer Address of Channel 0 bit 1
SRCP0.SRCP0_0 0 Source Pointer Address of Channel 0 bit 0
DSTP0 0xEC42 PEC Channel 0 Destination Pointer
DSTP0.DSTP0_15 15 Destination Pointer Address of Channel 0 bit 15
DSTP0.DSTP0_14 14 Destination Pointer Address of Channel 0 bit 14
DSTP0.DSTP0_13 13 Destination Pointer Address of Channel 0 bit 13
DSTP0.DSTP0_12 12 Destination Pointer Address of Channel 0 bit 12
DSTP0.DSTP0_11 11 Destination Pointer Address of Channel 0 bit 11
DSTP0.DSTP0_10 10 Destination Pointer Address of Channel 0 bit 10
DSTP0.DSTP0_9 9 Destination Pointer Address of Channel 0 bit 9
DSTP0.DSTP0_8 8 Destination Pointer Address of Channel 0 bit 8
DSTP0.DSTP0_7 7 Destination Pointer Address of Channel 0 bit 7
DSTP0.DSTP0_6 6 Destination Pointer Address of Channel 0 bit 6
DSTP0.DSTP0_5 5 Destination Pointer Address of Channel 0 bit 5
DSTP0.DSTP0_4 4 Destination Pointer Address of Channel 0 bit 4
DSTP0.DSTP0_3 3 Destination Pointer Address of Channel 0 bit 3
DSTP0.DSTP0_2 2 Destination Pointer Address of Channel 0 bit 2
DSTP0.DSTP0_1 1 Destination Pointer Address of Channel 0 bit 1
DSTP0.DSTP0_0 0 Destination Pointer Address of Channel 0 bit 0
SRCP1 0xEC44 PEC Channel 1 Source Pointer
SRCP1.SRCP1_15 15 Source Pointer Address of Channel 1 bit 15
SRCP1.SRCP1_14 14 Source Pointer Address of Channel 1 bit 14
SRCP1.SRCP1_13 13 Source Pointer Address of Channel 1 bit 13
SRCP1.SRCP1_12 12 Source Pointer Address of Channel 1 bit 12
SRCP1.SRCP1_11 11 Source Pointer Address of Channel 1 bit 11
SRCP1.SRCP1_10 10 Source Pointer Address of Channel 1 bit 10
SRCP1.SRCP1_9 9 Source Pointer Address of Channel 1 bit 9
SRCP1.SRCP1_8 8 Source Pointer Address of Channel 1 bit 8
SRCP1.SRCP1_7 7 Source Pointer Address of Channel 1 bit 7
SRCP1.SRCP1_6 6 Source Pointer Address of Channel 1 bit 6
SRCP1.SRCP1_5 5 Source Pointer Address of Channel 1 bit 5
SRCP1.SRCP1_4 4 Source Pointer Address of Channel 1 bit 4
SRCP1.SRCP1_3 3 Source Pointer Address of Channel 1 bit 3
SRCP1.SRCP1_2 2 Source Pointer Address of Channel 1 bit 2
SRCP1.SRCP1_1 1 Source Pointer Address of Channel 1 bit 1
SRCP1.SRCP1_0 0 Source Pointer Address of Channel 1 bit 0
DSTP1 0xEC46 PEC Channel 1 Destination Pointer
DSTP1.DSTP1_15 15 Destination Pointer Address of Channel 1 bit 15
DSTP1.DSTP1_14 14 Destination Pointer Address of Channel 1 bit 14
DSTP1.DSTP1_13 13 Destination Pointer Address of Channel 1 bit 13
DSTP1.DSTP1_12 12 Destination Pointer Address of Channel 1 bit 12
DSTP1.DSTP1_11 11 Destination Pointer Address of Channel 1 bit 11
DSTP1.DSTP1_10 10 Destination Pointer Address of Channel 1 bit 10
DSTP1.DSTP1_9 9 Destination Pointer Address of Channel 1 bit 9
DSTP1.DSTP1_8 8 Destination Pointer Address of Channel 1 bit 8
DSTP1.DSTP1_7 7 Destination Pointer Address of Channel 1 bit 7
DSTP1.DSTP1_6 6 Destination Pointer Address of Channel 1 bit 6
DSTP1.DSTP1_5 5 Destination Pointer Address of Channel 1 bit 5
DSTP1.DSTP1_4 4 Destination Pointer Address of Channel 1 bit 4
DSTP1.DSTP1_3 3 Destination Pointer Address of Channel 1 bit 3
DSTP1.DSTP1_2 2 Destination Pointer Address of Channel 1 bit 2
DSTP1.DSTP1_1 1 Destination Pointer Address of Channel 1 bit 1
DSTP1.DSTP1_0 0 Destination Pointer Address of Channel 1 bit 0
SRCP2 0xEC48 PEC Channel 2 Source Pointer
SRCP2.SRCP2_15 15 Source Pointer Address of Channel 2 bit 15
SRCP2.SRCP2_14 14 Source Pointer Address of Channel 2 bit 14
SRCP2.SRCP2_13 13 Source Pointer Address of Channel 2 bit 13
SRCP2.SRCP2_12 12 Source Pointer Address of Channel 2 bit 12
SRCP2.SRCP2_11 11 Source Pointer Address of Channel 2 bit 11
SRCP2.SRCP2_10 10 Source Pointer Address of Channel 2 bit 10
SRCP2.SRCP2_9 9 Source Pointer Address of Channel 2 bit 9
SRCP2.SRCP2_8 8 Source Pointer Address of Channel 2 bit 8
SRCP2.SRCP2_7 7 Source Pointer Address of Channel 2 bit 7
SRCP2.SRCP2_6 6 Source Pointer Address of Channel 2 bit 6
SRCP2.SRCP2_5 5 Source Pointer Address of Channel 2 bit 5
SRCP2.SRCP2_4 4 Source Pointer Address of Channel 2 bit 4
SRCP2.SRCP2_3 3 Source Pointer Address of Channel 2 bit 3
SRCP2.SRCP2_2 2 Source Pointer Address of Channel 2 bit 2
SRCP2.SRCP2_1 1 Source Pointer Address of Channel 2 bit 1
SRCP2.SRCP2_0 0 Source Pointer Address of Channel 2 bit 0
DSTP2 0xEC4A PEC Channel 2 Destination Pointer
DSTP2.DSTP2_15 15 Destination Pointer Address of Channel 2 bit 15
DSTP2.DSTP2_14 14 Destination Pointer Address of Channel 2 bit 14
DSTP2.DSTP2_13 13 Destination Pointer Address of Channel 2 bit 13
DSTP2.DSTP2_12 12 Destination Pointer Address of Channel 2 bit 12
DSTP2.DSTP2_11 11 Destination Pointer Address of Channel 2 bit 11
DSTP2.DSTP2_10 10 Destination Pointer Address of Channel 2 bit 10
DSTP2.DSTP2_9 9 Destination Pointer Address of Channel 2 bit 9
DSTP2.DSTP2_8 8 Destination Pointer Address of Channel 2 bit 8
DSTP2.DSTP2_7 7 Destination Pointer Address of Channel 2 bit 7
DSTP2.DSTP2_6 6 Destination Pointer Address of Channel 2 bit 6
DSTP2.DSTP2_5 5 Destination Pointer Address of Channel 2 bit 5
DSTP2.DSTP2_4 4 Destination Pointer Address of Channel 2 bit 4
DSTP2.DSTP2_3 3 Destination Pointer Address of Channel 2 bit 3
DSTP2.DSTP2_2 2 Destination Pointer Address of Channel 2 bit 2
DSTP2.DSTP2_1 1 Destination Pointer Address of Channel 2 bit 1
DSTP2.DSTP2_0 0 Destination Pointer Address of Channel 2 bit 0
SRCP3 0xEC4C PEC Channel 3 Source Pointer
SRCP3.SRCP3_15 15 Source Pointer Address of Channel 3 bit 15
SRCP3.SRCP3_14 14 Source Pointer Address of Channel 3 bit 14
SRCP3.SRCP3_13 13 Source Pointer Address of Channel 3 bit 13
SRCP3.SRCP3_12 12 Source Pointer Address of Channel 3 bit 12
SRCP3.SRCP3_11 11 Source Pointer Address of Channel 3 bit 11
SRCP3.SRCP3_10 10 Source Pointer Address of Channel 3 bit 10
SRCP3.SRCP3_9 9 Source Pointer Address of Channel 3 bit 9
SRCP3.SRCP3_8 8 Source Pointer Address of Channel 3 bit 8
SRCP3.SRCP3_7 7 Source Pointer Address of Channel 3 bit 7
SRCP3.SRCP3_6 6 Source Pointer Address of Channel 3 bit 6
SRCP3.SRCP3_5 5 Source Pointer Address of Channel 3 bit 5
SRCP3.SRCP3_4 4 Source Pointer Address of Channel 3 bit 4
SRCP3.SRCP3_3 3 Source Pointer Address of Channel 3 bit 3
SRCP3.SRCP3_2 2 Source Pointer Address of Channel 3 bit 2
SRCP3.SRCP3_1 1 Source Pointer Address of Channel 3 bit 1
SRCP3.SRCP3_0 0 Source Pointer Address of Channel 3 bit 0
DSTP3 0xEC4E PEC Channel 3 Destination Pointer
DSTP3.DSTP3_15 15 Destination Pointer Address of Channel 3 bit 15
DSTP3.DSTP3_14 14 Destination Pointer Address of Channel 3 bit 14
DSTP3.DSTP3_13 13 Destination Pointer Address of Channel 3 bit 13
DSTP3.DSTP3_12 12 Destination Pointer Address of Channel 3 bit 12
DSTP3.DSTP3_11 11 Destination Pointer Address of Channel 3 bit 11
DSTP3.DSTP3_10 10 Destination Pointer Address of Channel 3 bit 10
DSTP3.DSTP3_9 9 Destination Pointer Address of Channel 3 bit 9
DSTP3.DSTP3_8 8 Destination Pointer Address of Channel 3 bit 8
DSTP3.DSTP3_7 7 Destination Pointer Address of Channel 3 bit 7
DSTP3.DSTP3_6 6 Destination Pointer Address of Channel 3 bit 6
DSTP3.DSTP3_5 5 Destination Pointer Address of Channel 3 bit 5
DSTP3.DSTP3_4 4 Destination Pointer Address of Channel 3 bit 4
DSTP3.DSTP3_3 3 Destination Pointer Address of Channel 3 bit 3
DSTP3.DSTP3_2 2 Destination Pointer Address of Channel 3 bit 2
DSTP3.DSTP3_1 1 Destination Pointer Address of Channel 3 bit 1
DSTP3.DSTP3_0 0 Destination Pointer Address of Channel 3 bit 0
SRCP4 0xEC50 PEC Channel 4 Source Pointer
SRCP4.SRCP4_15 15 Source Pointer Address of Channel 4 bit 15
SRCP4.SRCP4_14 14 Source Pointer Address of Channel 4 bit 14
SRCP4.SRCP4_13 13 Source Pointer Address of Channel 4 bit 13
SRCP4.SRCP4_12 12 Source Pointer Address of Channel 4 bit 12
SRCP4.SRCP4_11 11 Source Pointer Address of Channel 4 bit 11
SRCP4.SRCP4_10 10 Source Pointer Address of Channel 4 bit 10
SRCP4.SRCP4_9 9 Source Pointer Address of Channel 4 bit 9
SRCP4.SRCP4_8 8 Source Pointer Address of Channel 4 bit 8
SRCP4.SRCP4_7 7 Source Pointer Address of Channel 4 bit 7
SRCP4.SRCP4_6 6 Source Pointer Address of Channel 4 bit 6
SRCP4.SRCP4_5 5 Source Pointer Address of Channel 4 bit 5
SRCP4.SRCP4_4 4 Source Pointer Address of Channel 4 bit 4
SRCP4.SRCP4_3 3 Source Pointer Address of Channel 4 bit 3
SRCP4.SRCP4_2 2 Source Pointer Address of Channel 4 bit 2
SRCP4.SRCP4_1 1 Source Pointer Address of Channel 4 bit 1
SRCP4.SRCP4_0 0 Source Pointer Address of Channel 4 bit 0
DSTP4 0xEC52 PEC Channel 4 Destination Pointer
DSTP4.DSTP4_15 15 Destination Pointer Address of Channel 4 bit 15
DSTP4.DSTP4_14 14 Destination Pointer Address of Channel 4 bit 14
DSTP4.DSTP4_13 13 Destination Pointer Address of Channel 4 bit 13
DSTP4.DSTP4_12 12 Destination Pointer Address of Channel 4 bit 12
DSTP4.DSTP4_11 11 Destination Pointer Address of Channel 4 bit 11
DSTP4.DSTP4_10 10 Destination Pointer Address of Channel 4 bit 10
DSTP4.DSTP4_9 9 Destination Pointer Address of Channel 4 bit 9
DSTP4.DSTP4_8 8 Destination Pointer Address of Channel 4 bit 8
DSTP4.DSTP4_7 7 Destination Pointer Address of Channel 4 bit 7
DSTP4.DSTP4_6 6 Destination Pointer Address of Channel 4 bit 6
DSTP4.DSTP4_5 5 Destination Pointer Address of Channel 4 bit 5
DSTP4.DSTP4_4 4 Destination Pointer Address of Channel 4 bit 4
DSTP4.DSTP4_3 3 Destination Pointer Address of Channel 4 bit 3
DSTP4.DSTP4_2 2 Destination Pointer Address of Channel 4 bit 2
DSTP4.DSTP4_1 1 Destination Pointer Address of Channel 4 bit 1
DSTP4.DSTP4_0 0 Destination Pointer Address of Channel 4 bit 0
SRCP5 0xEC54 PEC Channel 5 Source Pointer
SRCP5.SRCP5_15 15 Source Pointer Address of Channel 5 bit 15
SRCP5.SRCP5_14 14 Source Pointer Address of Channel 5 bit 14
SRCP5.SRCP5_13 13 Source Pointer Address of Channel 5 bit 13
SRCP5.SRCP5_12 12 Source Pointer Address of Channel 5 bit 12
SRCP5.SRCP5_11 11 Source Pointer Address of Channel 5 bit 11
SRCP5.SRCP5_10 10 Source Pointer Address of Channel 5 bit 10
SRCP5.SRCP5_9 9 Source Pointer Address of Channel 5 bit 9
SRCP5.SRCP5_8 8 Source Pointer Address of Channel 5 bit 8
SRCP5.SRCP5_7 7 Source Pointer Address of Channel 5 bit 7
SRCP5.SRCP5_6 6 Source Pointer Address of Channel 5 bit 6
SRCP5.SRCP5_5 5 Source Pointer Address of Channel 5 bit 5
SRCP5.SRCP5_4 4 Source Pointer Address of Channel 5 bit 4
SRCP5.SRCP5_3 3 Source Pointer Address of Channel 5 bit 3
SRCP5.SRCP5_2 2 Source Pointer Address of Channel 5 bit 2
SRCP5.SRCP5_1 1 Source Pointer Address of Channel 5 bit 1
SRCP5.SRCP5_0 0 Source Pointer Address of Channel 5 bit 0
DSTP5 0xEC56 PEC Channel 5 Destination Pointer
DSTP5.DSTP5_15 15 Destination Pointer Address of Channel 5 bit 15
DSTP5.DSTP5_14 14 Destination Pointer Address of Channel 5 bit 14
DSTP5.DSTP5_13 13 Destination Pointer Address of Channel 5 bit 13
DSTP5.DSTP5_12 12 Destination Pointer Address of Channel 5 bit 12
DSTP5.DSTP5_11 11 Destination Pointer Address of Channel 5 bit 11
DSTP5.DSTP5_10 10 Destination Pointer Address of Channel 5 bit 10
DSTP5.DSTP5_9 9 Destination Pointer Address of Channel 5 bit 9
DSTP5.DSTP5_8 8 Destination Pointer Address of Channel 5 bit 8
DSTP5.DSTP5_7 7 Destination Pointer Address of Channel 5 bit 7
DSTP5.DSTP5_6 6 Destination Pointer Address of Channel 5 bit 6
DSTP5.DSTP5_5 5 Destination Pointer Address of Channel 5 bit 5
DSTP5.DSTP5_4 4 Destination Pointer Address of Channel 5 bit 4
DSTP5.DSTP5_3 3 Destination Pointer Address of Channel 5 bit 3
DSTP5.DSTP5_2 2 Destination Pointer Address of Channel 5 bit 2
DSTP5.DSTP5_1 1 Destination Pointer Address of Channel 5 bit 1
DSTP5.DSTP5_0 0 Destination Pointer Address of Channel 5 bit 0
SRCP6 0xEC58 PEC Channel 6 Source Pointer
SRCP6.SRCP6_15 15 Source Pointer Address of Channel 6 bit 15
SRCP6.SRCP6_14 14 Source Pointer Address of Channel 6 bit 14
SRCP6.SRCP6_13 13 Source Pointer Address of Channel 6 bit 13
SRCP6.SRCP6_12 12 Source Pointer Address of Channel 6 bit 12
SRCP6.SRCP6_11 11 Source Pointer Address of Channel 6 bit 11
SRCP6.SRCP6_10 10 Source Pointer Address of Channel 6 bit 10
SRCP6.SRCP6_9 9 Source Pointer Address of Channel 6 bit 9
SRCP6.SRCP6_8 8 Source Pointer Address of Channel 6 bit 8
SRCP6.SRCP6_7 7 Source Pointer Address of Channel 6 bit 7
SRCP6.SRCP6_6 6 Source Pointer Address of Channel 6 bit 6
SRCP6.SRCP6_5 5 Source Pointer Address of Channel 6 bit 5
SRCP6.SRCP6_4 4 Source Pointer Address of Channel 6 bit 4
SRCP6.SRCP6_3 3 Source Pointer Address of Channel 6 bit 3
SRCP6.SRCP6_2 2 Source Pointer Address of Channel 6 bit 2
SRCP6.SRCP6_1 1 Source Pointer Address of Channel 6 bit 1
SRCP6.SRCP6_0 0 Source Pointer Address of Channel 6 bit 0
DSTP6 0xEC5A PEC Channel 6 Destination Pointer
DSTP6.DSTP6_15 15 Destination Pointer Address of Channel 6 bit 15
DSTP6.DSTP6_14 14 Destination Pointer Address of Channel 6 bit 14
DSTP6.DSTP6_13 13 Destination Pointer Address of Channel 6 bit 13
DSTP6.DSTP6_12 12 Destination Pointer Address of Channel 6 bit 12
DSTP6.DSTP6_11 11 Destination Pointer Address of Channel 6 bit 11
DSTP6.DSTP6_10 10 Destination Pointer Address of Channel 6 bit 10
DSTP6.DSTP6_9 9 Destination Pointer Address of Channel 6 bit 9
DSTP6.DSTP6_8 8 Destination Pointer Address of Channel 6 bit 8
DSTP6.DSTP6_7 7 Destination Pointer Address of Channel 6 bit 7
DSTP6.DSTP6_6 6 Destination Pointer Address of Channel 6 bit 6
DSTP6.DSTP6_5 5 Destination Pointer Address of Channel 6 bit 5
DSTP6.DSTP6_4 4 Destination Pointer Address of Channel 6 bit 4
DSTP6.DSTP6_3 3 Destination Pointer Address of Channel 6 bit 3
DSTP6.DSTP6_2 2 Destination Pointer Address of Channel 6 bit 2
DSTP6.DSTP6_1 1 Destination Pointer Address of Channel 6 bit 1
DSTP6.DSTP6_0 0 Destination Pointer Address of Channel 6 bit 0
SRCP7 0xEC5C PEC Channel 7 Source Pointer
SRCP7.SRCP7_15 15 Source Pointer Address of Channel 7 bit 15
SRCP7.SRCP7_14 14 Source Pointer Address of Channel 7 bit 14
SRCP7.SRCP7_13 13 Source Pointer Address of Channel 7 bit 13
SRCP7.SRCP7_12 12 Source Pointer Address of Channel 7 bit 12
SRCP7.SRCP7_11 11 Source Pointer Address of Channel 7 bit 11
SRCP7.SRCP7_10 10 Source Pointer Address of Channel 7 bit 10
SRCP7.SRCP7_9 9 Source Pointer Address of Channel 7 bit 9
SRCP7.SRCP7_8 8 Source Pointer Address of Channel 7 bit 8
SRCP7.SRCP7_7 7 Source Pointer Address of Channel 7 bit 7
SRCP7.SRCP7_6 6 Source Pointer Address of Channel 7 bit 6
SRCP7.SRCP7_5 5 Source Pointer Address of Channel 7 bit 5
SRCP7.SRCP7_4 4 Source Pointer Address of Channel 7 bit 4
SRCP7.SRCP7_3 3 Source Pointer Address of Channel 7 bit 3
SRCP7.SRCP7_2 2 Source Pointer Address of Channel 7 bit 2
SRCP7.SRCP7_1 1 Source Pointer Address of Channel 7 bit 1
SRCP7.SRCP7_0 0 Source Pointer Address of Channel 7 bit 0
DSTP7 0xEC5E PEC Channel 7 Destination
DSTP7.DSTP7_15 15 Destination Pointer Address of Channel 7 bit 15
DSTP7.DSTP7_14 14 Destination Pointer Address of Channel 7 bit 14
DSTP7.DSTP7_13 13 Destination Pointer Address of Channel 7 bit 13
DSTP7.DSTP7_12 12 Destination Pointer Address of Channel 7 bit 12
DSTP7.DSTP7_11 11 Destination Pointer Address of Channel 7 bit 11
DSTP7.DSTP7_10 10 Destination Pointer Address of Channel 7 bit 10
DSTP7.DSTP7_9 9 Destination Pointer Address of Channel 7 bit 9
DSTP7.DSTP7_8 8 Destination Pointer Address of Channel 7 bit 8
DSTP7.DSTP7_7 7 Destination Pointer Address of Channel 7 bit 7
DSTP7.DSTP7_6 6 Destination Pointer Address of Channel 7 bit 6
DSTP7.DSTP7_5 5 Destination Pointer Address of Channel 7 bit 5
DSTP7.DSTP7_4 4 Destination Pointer Address of Channel 7 bit 4
DSTP7.DSTP7_3 3 Destination Pointer Address of Channel 7 bit 3
DSTP7.DSTP7_2 2 Destination Pointer Address of Channel 7 bit 2
DSTP7.DSTP7_1 1 Destination Pointer Address of Channel 7 bit 1
DSTP7.DSTP7_0 0 Destination Pointer Address of Channel 7 bit 0
PECSEG0 0xEC80 PEC Pointer 0 Segment Address Register
PECSEG0.SRCSEG0_15 15 Source Pointer Segment Address of Channel 0 bit 15
PECSEG0.SRCSEG0_14 14 Source Pointer Segment Address of Channel 0 bit 14
PECSEG0.SRCSEG0_13 13 Source Pointer Segment Address of Channel 0 bit 13
PECSEG0.SRCSEG0_12 12 Source Pointer Segment Address of Channel 0 bit 12
PECSEG0.SRCSEG0_11 11 Source Pointer Segment Address of Channel 0 bit 11
PECSEG0.SRCSEG0_10 10 Source Pointer Segment Address of Channel 0 bit 10
PECSEG0.SRCSEG0_9 9 Source Pointer Segment Address of Channel 0 bit 9
PECSEG0.SRCSEG0_8 8 Source Pointer Segment Address of Channel 0 bit 8
PECSEG0.DSTSEG0_7 7 Destination Pointer Segment Address of Channel 0 bit 7
PECSEG0.DSTSEG0_6 6 Destination Pointer Segment Address of Channel 0 bit 6
PECSEG0.DSTSEG0_5 5 Destination Pointer Segment Address of Channel 0 bit 5
PECSEG0.DSTSEG0_4 4 Destination Pointer Segment Address of Channel 0 bit 4
PECSEG0.DSTSEG0_3 3 Destination Pointer Segment Address of Channel 0 bit 3
PECSEG0.DSTSEG0_2 2 Destination Pointer Segment Address of Channel 0 bit 2
PECSEG0.DSTSEG0_1 1 Destination Pointer Segment Address of Channel 0 bit 1
PECSEG0.DSTSEG0_0 0 Destination Pointer Segment Address of Channel 0 bit 0
PECSEG1 0xEC82 PEC Pointer 1 Segment Address Register
PECSEG1.SRCSEG1_15 15 Source Pointer Segment Address of Channel 1 bit 15
PECSEG1.SRCSEG1_14 14 Source Pointer Segment Address of Channel 1 bit 14
PECSEG1.SRCSEG1_13 13 Source Pointer Segment Address of Channel 1 bit 13
PECSEG1.SRCSEG1_12 12 Source Pointer Segment Address of Channel 1 bit 12
PECSEG1.SRCSEG1_11 11 Source Pointer Segment Address of Channel 1 bit 11
PECSEG1.SRCSEG1_10 10 Source Pointer Segment Address of Channel 1 bit 10
PECSEG1.SRCSEG1_9 9 Source Pointer Segment Address of Channel 1 bit 9
PECSEG1.SRCSEG1_8 8 Source Pointer Segment Address of Channel 1 bit 8
PECSEG1.DSTSEG1_7 7 Destination Pointer Segment Address of Channel 1 bit 7
PECSEG1.DSTSEG1_6 6 Destination Pointer Segment Address of Channel 1 bit 6
PECSEG1.DSTSEG1_5 5 Destination Pointer Segment Address of Channel 1 bit 5
PECSEG1.DSTSEG1_4 4 Destination Pointer Segment Address of Channel 1 bit 4
PECSEG1.DSTSEG1_3 3 Destination Pointer Segment Address of Channel 1 bit 3
PECSEG1.DSTSEG1_2 2 Destination Pointer Segment Address of Channel 1 bit 2
PECSEG1.DSTSEG1_1 1 Destination Pointer Segment Address of Channel 1 bit 1
PECSEG1.DSTSEG1_0 0 Destination Pointer Segment Address of Channel 1 bit 0
PECSEG2 0xEC84 PEC Pointer 2 Segment Address Register
PECSEG2.SRCSEG2_15 15 Source Pointer Segment Address of Channel 2 bit 15
PECSEG2.SRCSEG2_14 14 Source Pointer Segment Address of Channel 2 bit 14
PECSEG2.SRCSEG2_13 13 Source Pointer Segment Address of Channel 2 bit 13
PECSEG2.SRCSEG2_12 12 Source Pointer Segment Address of Channel 2 bit 12
PECSEG2.SRCSEG2_11 11 Source Pointer Segment Address of Channel 2 bit 11
PECSEG2.SRCSEG2_10 10 Source Pointer Segment Address of Channel 2 bit 10
PECSEG2.SRCSEG2_9 9 Source Pointer Segment Address of Channel 2 bit 9
PECSEG2.SRCSEG2_8 8 Source Pointer Segment Address of Channel 2 bit 8
PECSEG2.DSTSEG2_7 7 Destination Pointer Segment Address of Channel 2 bit 7
PECSEG2.DSTSEG2_6 6 Destination Pointer Segment Address of Channel 2 bit 6
PECSEG2.DSTSEG2_5 5 Destination Pointer Segment Address of Channel 2 bit 5
PECSEG2.DSTSEG2_4 4 Destination Pointer Segment Address of Channel 2 bit 4
PECSEG2.DSTSEG2_3 3 Destination Pointer Segment Address of Channel 2 bit 3
PECSEG2.DSTSEG2_2 2 Destination Pointer Segment Address of Channel 2 bit 2
PECSEG2.DSTSEG2_1 1 Destination Pointer Segment Address of Channel 2 bit 1
PECSEG2.DSTSEG2_0 0 Destination Pointer Segment Address of Channel 2 bit 0
PECSEG3 0xEC86 PEC Pointer 3 Segment Address Register
PECSEG3.SRCSEG3_15 15 Source Pointer Segment Address of Channel 3 bit 15
PECSEG3.SRCSEG3_14 14 Source Pointer Segment Address of Channel 3 bit 14
PECSEG3.SRCSEG3_13 13 Source Pointer Segment Address of Channel 3 bit 13
PECSEG3.SRCSEG3_12 12 Source Pointer Segment Address of Channel 3 bit 12
PECSEG3.SRCSEG3_11 11 Source Pointer Segment Address of Channel 3 bit 11
PECSEG3.SRCSEG3_10 10 Source Pointer Segment Address of Channel 3 bit 10
PECSEG3.SRCSEG3_9 9 Source Pointer Segment Address of Channel 3 bit 9
PECSEG3.SRCSEG3_8 8 Source Pointer Segment Address of Channel 3 bit 8
PECSEG3.DSTSEG3_7 7 Destination Pointer Segment Address of Channel 3 bit 7
PECSEG3.DSTSEG3_6 6 Destination Pointer Segment Address of Channel 3 bit 6
PECSEG3.DSTSEG3_5 5 Destination Pointer Segment Address of Channel 3 bit 5
PECSEG3.DSTSEG3_4 4 Destination Pointer Segment Address of Channel 3 bit 4
PECSEG3.DSTSEG3_3 3 Destination Pointer Segment Address of Channel 3 bit 3
PECSEG3.DSTSEG3_2 2 Destination Pointer Segment Address of Channel 3 bit 2
PECSEG3.DSTSEG3_1 1 Destination Pointer Segment Address of Channel 3 bit 1
PECSEG3.DSTSEG3_0 0 Destination Pointer Segment Address of Channel 3 bit 0
PECSEG4 0xEC88 PEC Pointer 4 Segment Address Register
PECSEG4.SRCSEG4_15 15 Source Pointer Segment Address of Channel 4 bit 15
PECSEG4.SRCSEG4_14 14 Source Pointer Segment Address of Channel 4 bit 14
PECSEG4.SRCSEG4_13 13 Source Pointer Segment Address of Channel 4 bit 13
PECSEG4.SRCSEG4_12 12 Source Pointer Segment Address of Channel 4 bit 12
PECSEG4.SRCSEG4_11 11 Source Pointer Segment Address of Channel 4 bit 11
PECSEG4.SRCSEG4_10 10 Source Pointer Segment Address of Channel 4 bit 10
PECSEG4.SRCSEG4_9 9 Source Pointer Segment Address of Channel 4 bit 9
PECSEG4.SRCSEG4_8 8 Source Pointer Segment Address of Channel 4 bit 8
PECSEG4.DSTSEG4_7 7 Destination Pointer Segment Address of Channel 4 bit 7
PECSEG4.DSTSEG4_6 6 Destination Pointer Segment Address of Channel 4 bit 6
PECSEG4.DSTSEG4_5 5 Destination Pointer Segment Address of Channel 4 bit 5
PECSEG4.DSTSEG4_4 4 Destination Pointer Segment Address of Channel 4 bit 4
PECSEG4.DSTSEG4_3 3 Destination Pointer Segment Address of Channel 4 bit 3
PECSEG4.DSTSEG4_2 2 Destination Pointer Segment Address of Channel 4 bit 2
PECSEG4.DSTSEG4_1 1 Destination Pointer Segment Address of Channel 4 bit 1
PECSEG4.DSTSEG4_0 0 Destination Pointer Segment Address of Channel 4 bit 0
PECSEG5 0xEC8A PEC Pointer 5 Segment Address Register
PECSEG5.SRCSEG5_15 15 Source Pointer Segment Address of Channel 5 bit 15
PECSEG5.SRCSEG5_14 14 Source Pointer Segment Address of Channel 5 bit 14
PECSEG5.SRCSEG5_13 13 Source Pointer Segment Address of Channel 5 bit 13
PECSEG5.SRCSEG5_12 12 Source Pointer Segment Address of Channel 5 bit 12
PECSEG5.SRCSEG5_11 11 Source Pointer Segment Address of Channel 5 bit 11
PECSEG5.SRCSEG5_10 10 Source Pointer Segment Address of Channel 5 bit 10
PECSEG5.SRCSEG5_9 9 Source Pointer Segment Address of Channel 5 bit 9
PECSEG5.SRCSEG5_8 8 Source Pointer Segment Address of Channel 5 bit 8
PECSEG5.DSTSEG5_7 7 Destination Pointer Segment Address of Channel 5 bit 7
PECSEG5.DSTSEG5_6 6 Destination Pointer Segment Address of Channel 5 bit 6
PECSEG5.DSTSEG5_5 5 Destination Pointer Segment Address of Channel 5 bit 5
PECSEG5.DSTSEG5_4 4 Destination Pointer Segment Address of Channel 5 bit 4
PECSEG5.DSTSEG5_3 3 Destination Pointer Segment Address of Channel 5 bit 3
PECSEG5.DSTSEG5_2 2 Destination Pointer Segment Address of Channel 5 bit 2
PECSEG5.DSTSEG5_1 1 Destination Pointer Segment Address of Channel 5 bit 1
PECSEG5.DSTSEG5_0 0 Destination Pointer Segment Address of Channel 5 bit 0
PECSEG6 0xEC8C PEC Pointer 6 Segment Address Register
PECSEG6.SRCSEG6_15 15 Source Pointer Segment Address of Channel 6 bit 15
PECSEG6.SRCSEG6_14 14 Source Pointer Segment Address of Channel 6 bit 14
PECSEG6.SRCSEG6_13 13 Source Pointer Segment Address of Channel 6 bit 13
PECSEG6.SRCSEG6_12 12 Source Pointer Segment Address of Channel 6 bit 12
PECSEG6.SRCSEG6_11 11 Source Pointer Segment Address of Channel 6 bit 11
PECSEG6.SRCSEG6_10 10 Source Pointer Segment Address of Channel 6 bit 10
PECSEG6.SRCSEG6_9 9 Source Pointer Segment Address of Channel 6 bit 9
PECSEG6.SRCSEG6_8 8 Source Pointer Segment Address of Channel 6 bit 8
PECSEG6.DSTSEG6_7 7 Destination Pointer Segment Address of Channel 6 bit 7
PECSEG6.DSTSEG6_6 6 Destination Pointer Segment Address of Channel 6 bit 6
PECSEG6.DSTSEG6_5 5 Destination Pointer Segment Address of Channel 6 bit 5
PECSEG6.DSTSEG6_4 4 Destination Pointer Segment Address of Channel 6 bit 4
PECSEG6.DSTSEG6_3 3 Destination Pointer Segment Address of Channel 6 bit 3
PECSEG6.DSTSEG6_2 2 Destination Pointer Segment Address of Channel 6 bit 2
PECSEG6.DSTSEG6_1 1 Destination Pointer Segment Address of Channel 6 bit 1
PECSEG6.DSTSEG6_0 0 Destination Pointer Segment Address of Channel 6 bit 0
PECSEG7 0xEC8E PEC Pointer 7 Segment Address Register
PECSEG7.SRCSEG7_15 15 Source Pointer Segment Address of Channel 7 bit 15
PECSEG7.SRCSEG7_14 14 Source Pointer Segment Address of Channel 7 bit 14
PECSEG7.SRCSEG7_13 13 Source Pointer Segment Address of Channel 7 bit 13
PECSEG7.SRCSEG7_12 12 Source Pointer Segment Address of Channel 7 bit 12
PECSEG7.SRCSEG7_11 11 Source Pointer Segment Address of Channel 7 bit 11
PECSEG7.SRCSEG7_10 10 Source Pointer Segment Address of Channel 7 bit 10
PECSEG7.SRCSEG7_9 9 Source Pointer Segment Address of Channel 7 bit 9
PECSEG7.SRCSEG7_8 8 Source Pointer Segment Address of Channel 7 bit 8
PECSEG7.DSTSEG7_7 7 Destination Pointer Segment Address of Channel 7 bit 7
PECSEG7.DSTSEG7_6 6 Destination Pointer Segment Address of Channel 7 bit 6
PECSEG7.DSTSEG7_5 5 Destination Pointer Segment Address of Channel 7 bit 5
PECSEG7.DSTSEG7_4 4 Destination Pointer Segment Address of Channel 7 bit 4
PECSEG7.DSTSEG7_3 3 Destination Pointer Segment Address of Channel 7 bit 3
PECSEG7.DSTSEG7_2 2 Destination Pointer Segment Address of Channel 7 bit 2
PECSEG7.DSTSEG7_1 1 Destination Pointer Segment Address of Channel 7 bit 1
PECSEG7.DSTSEG7_0 0 Destination Pointer Segment Address of Channel 7 bit 0
EBCMOD0 0xEE00 EBC Mode Control Register 0
EBCMOD0.ALEDIS 13 ALE Pin Disable
EBCMOD0.BYTDIS 12 BHE Pin Disable
EBCMOD0.WRCFG 11 Configuration for Pins WR/WRL, BHE/WRH
EBCMOD0.EBCDIS 10 EBC Pins Disable
EBCMOD0.CSPEN_7 7 CSx Pins Enable (only external CSx) bit 7
EBCMOD0.CSPEN_6 6 CSx Pins Enable (only external CSx) bit 6
EBCMOD0.CSPEN_5 5 CSx Pins Enable (only external CSx) bit 5
EBCMOD0.CSPEN_4 4 CSx Pins Enable (only external CSx) bit 4
EBCMOD0.SAPEN_3 3 Segment Address Pins Enable bit 3
EBCMOD0.SAPEN_2 2 Segment Address Pins Enable bit 2
EBCMOD0.SAPEN_1 1 Segment Address Pins Enable bit 1
EBCMOD0.SAPEN_0 0 Segment Address Pins Enable bit 0
EBCMOD1 0xEE02 EBC Mode Control Register 1
EBCMOD1.WRPDIS 7 WR/WRL Pin Disable
EBCMOD1.DHPDIS 6 Data High Port Pins Disable
EBCMOD1.ALPDIS 5 Address Low Pins Disable
EBCMOD1.A0PDIS 4 Address Bit 0 Pin Disable
EBCMOD1.APDIS_3 3 Address Port Pins Disable bit 3
EBCMOD1.APDIS_2 2 Address Port Pins Disable bit 2
EBCMOD1.APDIS_1 1 Address Port Pins Disable bit 1
EBCMOD1.APDIS_0 0 Address Port Pins Disable bit 0
TCONCSMM 0xEE0C Monitor Memory CS Timing Configuration Register
TCONCSSM 0xEE0E Startup Memory CS Timing Configuration Register
TCONCS0 0xEE10 CS0 Timing Configuration Register
TCONCS0.WRPHF_14 14 Write Phase F bit 14
TCONCS0.WRPHF_13 13 Write Phase F bit 13
TCONCS0.RDPHF_12 12 Read Phase F bit 12
TCONCS0.RDPHF_11 11 Read Phase F bit 11
TCONCS0.PHE_10 10 Phase E bit 10
TCONCS0.PHE_9 9 Phase E bit 9
TCONCS0.PHE_8 8 Phase E bit 8
TCONCS0.PHE_7 7 Phase E bit 7
TCONCS0.PHE_6 6 Phase E bit 6
TCONCS0.PHD 5 Phase D
TCONCS0.PHC_4 4 Phase C bit 4
TCONCS0.PHC_3 3 Phase C bit 3
TCONCS0.PHB 2 Phase B
TCONCS0.PHA_1 1 Phase A bit 1
TCONCS0.PHA_0 0 Phase A bit 0
FCONCS0 0xEE12 CS0 Function Configuration Register
FCONCS0.BTYP_5 5 Bus Type Selection bit 5
FCONCS0.BTYP_4 4 Bus Type Selection bit 4
FCONCS0.ENCS 0 Enable Chip Select
TCONCS1 0xEE18 CS1 Timing Configuration Register
TCONCS1.WRPHF_14 14 Write Phase F bit 14
TCONCS1.WRPHF_13 13 Write Phase F bit 13
TCONCS1.RDPHF_12 12 Read Phase F bit 12
TCONCS1.RDPHF_11 11 Read Phase F bit 11
TCONCS1.PHE_10 10 Phase E bit 10
TCONCS1.PHE_9 9 Phase E bit 9
TCONCS1.PHE_8 8 Phase E bit 8
TCONCS1.PHE_7 7 Phase E bit 7
TCONCS1.PHE_6 6 Phase E bit 6
TCONCS1.PHD 5 Phase D
TCONCS1.PHC_4 4 Phase C bit 4
TCONCS1.PHC_3 3 Phase C bit 3
TCONCS1.PHB 2 Phase B
TCONCS1.PHA_1 1 Phase A bit 1
TCONCS1.PHA_0 0 Phase A bit 0
FCONCS1 0xEE1A CS1 Function Configuration Register
FCONCS1.BTYP_5 5 Bus Type Selection bit 5
FCONCS1.BTYP_4 4 Bus Type Selection bit 4
FCONCS1.RDYMOD 2 Ready Mode
FCONCS1.RDYEN 1 Ready enable
FCONCS1.ENCS 0 Enable Chip Select
ADDRSEL1 0xEE1E CS1 Address Range and Size Selection Register
ADDRSEL1.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL1.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL1.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL1.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL1.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL1.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL1.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL1.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL1.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL1.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL1.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL1.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL1.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL1.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL1.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL1.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS2 0xEE20 CS2 Timing Configuration Register
TCONCS2.WRPHF_14 14 Write Phase F bit 14
TCONCS2.WRPHF_13 13 Write Phase F bit 13
TCONCS2.RDPHF_12 12 Read Phase F bit 12
TCONCS2.RDPHF_11 11 Read Phase F bit 11
TCONCS2.PHE_10 10 Phase E bit 10
TCONCS2.PHE_9 9 Phase E bit 9
TCONCS2.PHE_8 8 Phase E bit 8
TCONCS2.PHE_7 7 Phase E bit 7
TCONCS2.PHE_6 6 Phase E bit 6
TCONCS2.PHD 5 Phase D
TCONCS2.PHC_4 4 Phase C bit 4
TCONCS2.PHC_3 3 Phase C bit 3
TCONCS2.PHB 2 Phase B
TCONCS2.PHA_1 1 Phase A bit 1
TCONCS2.PHA_0 0 Phase A bit 0
FCONCS2 0xEE22 CS2 Function Configuration Register
FCONCS2.BTYP_5 5 Bus Type Selection bit 5
FCONCS2.BTYP_4 4 Bus Type Selection bit 4
FCONCS2.RDYMOD 2 Ready Mode
FCONCS2.RDYEN 1 Ready enable
FCONCS2.ENCS 0 Enable Chip Select
ADDRSEL2 0xEE26 CS2 Address Range and Size Selection Register
ADDRSEL2.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL2.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL2.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL2.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL2.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL2.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL2.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL2.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL2.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL2.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL2.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL2.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL2.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL2.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL2.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL2.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS3 0xEE28 CS3 Timing Configuration Register
TCONCS3.WRPHF_14 14 Write Phase F bit 14
TCONCS3.WRPHF_13 13 Write Phase F bit 13
TCONCS3.RDPHF_12 12 Read Phase F bit 12
TCONCS3.RDPHF_11 11 Read Phase F bit 11
TCONCS3.PHE_10 10 Phase E bit 10
TCONCS3.PHE_9 9 Phase E bit 9
TCONCS3.PHE_8 8 Phase E bit 8
TCONCS3.PHE_7 7 Phase E bit 7
TCONCS3.PHE_6 6 Phase E bit 6
TCONCS3.PHD 5 Phase D
TCONCS3.PHC_4 4 Phase C bit 4
TCONCS3.PHC_3 3 Phase C bit 3
TCONCS3.PHB 2 Phase B
TCONCS3.PHA_1 1 Phase A bit 1
TCONCS3.PHA_0 0 Phase A bit 0
FCONCS3 0xEE2A CS3 Function Configuration Register
FCONCS3.BTYP_5 5 Bus Type Selection bit 5
FCONCS3.BTYP_4 4 Bus Type Selection bit 4
FCONCS3.RDYMOD 2 Ready Mode
FCONCS3.RDYEN 1 Ready enable
FCONCS3.ENCS 0 Enable Chip Select
ADDRSEL3 0xEE2E CS3 Address Range and Size Selection Register
ADDRSEL3.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL3.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL3.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL3.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL3.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL3.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL3.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL3.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL3.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL3.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL3.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL3.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL3.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL3.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL3.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL3.RGSZ_0 0 Address Range Size Selection bit 0
TCONCS4 0xEE30 CS4 Timing Configuration Register
FCONCS4 0xEE32 CS4 Function Configuration Register
ADDRSEL4 0xEE36 CS4 Address Range and Size Selection Register
TCONCS7 0xEE48 CS7 Timing Configuration Register
TCONCS7.WRPHF_14 14 Write Phase F bit 14
TCONCS7.WRPHF_13 13 Write Phase F bit 13
TCONCS7.RDPHF_12 12 Read Phase F bit 12
TCONCS7.RDPHF_11 11 Read Phase F bit 11
TCONCS7.PHE_10 10 Phase E bit 10
TCONCS7.PHE_9 9 Phase E bit 9
TCONCS7.PHE_8 8 Phase E bit 8
TCONCS7.PHE_7 7 Phase E bit 7
TCONCS7.PHE_6 6 Phase E bit 6
TCONCS7.PHD 5 Phase D
TCONCS7.PHC_4 4 Phase C bit 4
TCONCS7.PHC_3 3 Phase C bit 3
TCONCS7.PHB 2 Phase B
TCONCS7.PHA_1 1 Phase A bit 1
TCONCS7.PHA_0 0 Phase A bit 0
FCONCS7 0xEE4A CS7 Function Configuration Register
FCONCS7.BTYP_5 5 Bus Type Selection bit 5
FCONCS7.BTYP_4 4 Bus Type Selection bit 4
FCONCS7.RDYMOD 2 Ready Mode
FCONCS7.RDYEN 1 Ready enable
FCONCS7.ENCS 0 Enable Chip Select
ADDRSEL7 0xEE4E CS7 Address Range and Size Selection Register
ADDRSEL7.RGSAD_15 15 Address Range Start Address Selection bit 15
ADDRSEL7.RGSAD_14 14 Address Range Start Address Selection bit 14
ADDRSEL7.RGSAD_13 13 Address Range Start Address Selection bit 13
ADDRSEL7.RGSAD_12 12 Address Range Start Address Selection bit 12
ADDRSEL7.RGSAD_11 11 Address Range Start Address Selection bit 11
ADDRSEL7.RGSAD_10 10 Address Range Start Address Selection bit 10
ADDRSEL7.RGSAD_9 9 Address Range Start Address Selection bit 9
ADDRSEL7.RGSAD_8 8 Address Range Start Address Selection bit 8
ADDRSEL7.RGSAD_7 7 Address Range Start Address Selection bit 7
ADDRSEL7.RGSAD_6 6 Address Range Start Address Selection bit 6
ADDRSEL7.RGSAD_5 5 Address Range Start Address Selection bit 5
ADDRSEL7.RGSAD_4 4 Address Range Start Address Selection bit 4
ADDRSEL7.RGSZ_3 3 Address Range Size Selection bit 3
ADDRSEL7.RGSZ_2 2 Address Range Size Selection bit 2
ADDRSEL7.RGSZ_1 1 Address Range Size Selection bit 1
ADDRSEL7.RGSZ_0 0 Address Range Size Selection bit 0
QX0 0xF000 MAC Offset Register
QX0.QX_15 15 Modifiable portion of register QX0 bit 15
QX0.QX_14 14 Modifiable portion of register QX0 bit 14
QX0.QX_13 13 Modifiable portion of register QX0 bit 13
QX0.QX_12 12 Modifiable portion of register QX0 bit 12
QX0.QX_11 11 Modifiable portion of register QX0 bit 11
QX0.QX_10 10 Modifiable portion of register QX0 bit 10
QX0.QX_9 9 Modifiable portion of register QX0 bit 9
QX0.QX_8 8 Modifiable portion of register QX0 bit 8
QX0.QX_7 7 Modifiable portion of register QX0 bit 7
QX0.QX_6 6 Modifiable portion of register QX0 bit 6
QX0.QX_5 5 Modifiable portion of register QX0 bit 5
QX0.QX_4 4 Modifiable portion of register QX0 bit 4
QX0.QX_3 3 Modifiable portion of register QX0 bit 3
QX0.QX_2 2 Modifiable portion of register QX0 bit 2
QX0.QX_1 1 Modifiable portion of register QX0 bit 1
QX1 0xF002 MAC Offset Register
QX1.QX_15 15 Modifiable portion of register QX1 bit 15
QX1.QX_14 14 Modifiable portion of register QX1 bit 14
QX1.QX_13 13 Modifiable portion of register QX1 bit 13
QX1.QX_12 12 Modifiable portion of register QX1 bit 12
QX1.QX_11 11 Modifiable portion of register QX1 bit 11
QX1.QX_10 10 Modifiable portion of register QX1 bit 10
QX1.QX_9 9 Modifiable portion of register QX1 bit 9
QX1.QX_8 8 Modifiable portion of register QX1 bit 8
QX1.QX_7 7 Modifiable portion of register QX1 bit 7
QX1.QX_6 6 Modifiable portion of register QX1 bit 6
QX1.QX_5 5 Modifiable portion of register QX1 bit 5
QX1.QX_4 4 Modifiable portion of register QX1 bit 4
QX1.QX_3 3 Modifiable portion of register QX1 bit 3
QX1.QX_2 2 Modifiable portion of register QX1 bit 2
QX1.QX_1 1 Modifiable portion of register QX1 bit 1
QR0 0xF004 MAC Offset Register
QR0.QR_15 15 Modifiable portion of register QR0 bit 15
QR0.QR_14 14 Modifiable portion of register QR0 bit 14
QR0.QR_13 13 Modifiable portion of register QR0 bit 13
QR0.QR_12 12 Modifiable portion of register QR0 bit 12
QR0.QR_11 11 Modifiable portion of register QR0 bit 11
QR0.QR_10 10 Modifiable portion of register QR0 bit 10
QR0.QR_9 9 Modifiable portion of register QR0 bit 9
QR0.QR_8 8 Modifiable portion of register QR0 bit 8
QR0.QR_7 7 Modifiable portion of register QR0 bit 7
QR0.QR_6 6 Modifiable portion of register QR0 bit 6
QR0.QR_5 5 Modifiable portion of register QR0 bit 5
QR0.QR_4 4 Modifiable portion of register QR0 bit 4
QR0.QR_3 3 Modifiable portion of register QR0 bit 3
QR0.QR_2 2 Modifiable portion of register QR0 bit 2
QR0.QR_1 1 Modifiable portion of register QR0 bit 1
QR1 0xF006 MAC Offset Register
QR1.QR_15 15 Modifiable portion of register QR1 bit 15
QR1.QR_14 14 Modifiable portion of register QR1 bit 14
QR1.QR_13 13 Modifiable portion of register QR1 bit 13
QR1.QR_12 12 Modifiable portion of register QR1 bit 12
QR1.QR_11 11 Modifiable portion of register QR1 bit 11
QR1.QR_10 10 Modifiable portion of register QR1 bit 10
QR1.QR_9 9 Modifiable portion of register QR1 bit 9
QR1.QR_8 8 Modifiable portion of register QR1 bit 8
QR1.QR_7 7 Modifiable portion of register QR1 bit 7
QR1.QR_6 6 Modifiable portion of register QR1 bit 6
QR1.QR_5 5 Modifiable portion of register QR1 bit 5
QR1.QR_4 4 Modifiable portion of register QR1 bit 4
QR1.QR_3 3 Modifiable portion of register QR1 bit 3
QR1.QR_2 2 Modifiable portion of register QR1 bit 2
QR1.QR_1 1 Modifiable portion of register QR1 bit 1
CPUID 0xF00C CPU Identification Register
CC2_T7 0xF050 CAPCOM 2 Timer 7 Register
CC2_T8 0xF052 CAPCOM 2 Timer 8 Register
CC2_T7REL 0xF054 CAPCOM 2 Timer 7 Reload Register
CC2_T8REL 0xF056 CAPCOM 2 Timer 8 Reload Register
SSC1_TB 0xF05A SSC Transmit Buffer (WO)
SSC1_RB 0xF05C SSC Receive Buffer (RO)
SSC1_BR 0xF05E SSC Baudrate Register
CC1_PISEL 0xF060 Port Input Select Register
CC1_IOC 0xF062 CAPCOM1 IO Control
CC2_PISEL 0xF064 Port Input Select Register
CC2_IOC 0xF066 CAPCOM2 IO Control
COMDATA 0xF068 Communication Mode data register (Cerberus)
COMDATA.MTR_ADDR_15 15 Set bit 15 of selected
COMDATA.MTR_ADDR_14 14 Set bit 14 of selected
COMDATA.MTR_ADDR_13 13 Set bit 13 of selected
COMDATA.MTR_ADDR_12 12 Set bit 12 of selected
COMDATA.MTR_ADDR_11 11 Set bit 11 of selected
COMDATA.MTR_ADDR_10 10 Set bit 10 of selected
COMDATA.MTR_ADDR_9 9 Set bit 9 of selected
COMDATA.MTR_ADDR_8 8 Set bit 8 of selected
COMDATA.MTR_ADDR_7 7 Set bit 7 of selected
COMDATA.MTR_ADDR_6 6 Set bit 6 of selected
COMDATA.MTR_ADDR_5 5 Set bit 5 of selected
COMDATA.MTR_ADDR_4 4 Set bit 4 of selected
COMDATA.MTR_ADDR_3 3 Set bit 3 of selected
COMDATA.MTR_ADDR_2 2 Set bit 2 of selected
COMDATA.MTR_ADDR_1 1 Set bit 1 of selected
COMDATA.MTR_ADDR_0 0 Set bit 0 of selected
RWDATA 0xF06A RW mode data reg. (Cerberus)
RWDATA.MTR_SELECT_ADDR_9 9
RWDATA.MTR_SELECT_ADDR_8 8
RWDATA.MTR_ADDR_X_7 7 Set bit of selected 7
RWDATA.MTR_ADDR_X_6 6 Set bit of selected 6
RWDATA.MTR_ADDR_X_5 5 Set bit of selected 5
RWDATA.MTR_ADDR_X_4 4 Set bit of selected 4
RWDATA.MTR_ADDR_X_3 3 Set bit of selected 3
RWDATA.MTR_ADDR_X_2 2 Set bit of selected 2
RWDATA.MTR_ADDR_X_1 1 Set bit of selected 1
RWDATA.MTR_ADDR_X_0 0 Set bit of selected 0
IOSR 0xF06C Cerberus Status and Control Register
IOSR.MTR_CTL_P 15 Bit protection (MTR_CTL unchanged/can be changed)
IOSR.MTR_CTL 14 Monitor controlled tracing disabled/enabled
IOSR.CLNT_ON 9 Client not selected/selected
IOSR.DBG_ON 8 No external debugger present / External debugger present
IOSR.COM_SYNC 7 High level sync bit for Communication Mode
IOSR.CW_ACK 6 Write request acknowledge in Communication Mode
IOSR.CWSYNC 5 Write sync bit for Communication Mode
IOSR.CRSYNC 4 Read sync bit for Communication Mode
IOSR.RW_EN_P 3 Bit protection (RW_ENABLE unchanged / RW_ENABLE can be changed)
IOSR.RW_ENABLED 2 Used by user program for security
IOSR.RW_DIS_P 1 Bit protection (RW_DISABLE unchanged / RW_DISABLE can be changed)
IOSR.RW_DISABLE 0 RW mode protection
IDRT 0xF070 Identifier Silicon Correction
IDMEM2 0xF076 IDMEM2 Identifier
IDPROG 0xF078 IDPROG Identifier
IDMEM 0xF07A IDMEM Identifier
IDCHIP 0xF07C IDCHIP Identifier
IDMANUF 0xF07E IDMANUF Identifier
POCON0L 0xF080 Port 0L Output Control Register
POCON0H 0xF082 Port 0H Output Control Register
POCON1L 0xF084 Port 1L Output Control Register
POCON1H 0xF086 Port 1H Output Control Register
POCON3 0xF08A Port 3 Output Control Register
POCON4 0xF08C Port 4 Output Control Register
POCON6 0xF08E Port P6 Output Control Port
POCON7 0xF090 Port P7 Output Control Port
POCON9 0xF094 Port 9 Output Control Register
ADC_CTR2 0xF09C A/D Converter Control Register 2
ADC_CTR2IN 0xF09E A/D Converter Injection Control Register 2
ADC_DAT2 0xF0A0 A/D Converter Result Register 2
ASC1_TxFCON 0xF0A4 Transmit FIFO Control Register
ASC1_RxFCON 0xF0A6 Receive FIFO Control Register
POCON20 0xF0AA Port 20 Output Control Register
SSC0_TB 0xF0B0 SSC Transmit Buffer (WO)
SSC0_RB 0xF0B2 SSC Receive Buffer (RO)
SSC0_BR 0xF0B4 SSC Baudrate Register
ASC0_ABSTAT 0xF0B8 ASC0 Autobaud Status Register
ASC0_FSTAT 0xF0BA FIFO Status Register
ASC1_ABSTAT 0xF0BC ASC1 Autobaud Status Register
ASC1_FSTAT 0xF0BE FIFO Status Register
SCUSLC 0xF0C0 Security Level Command Reg.
SCUSLC.COMMAND_15 15 Security Level Control Command bit 15
SCUSLC.COMMAND_14 14 Security Level Control Command bit 14
SCUSLC.COMMAND_13 13 Security Level Control Command bit 13
SCUSLC.COMMAND_12 12 Security Level Control Command bit 12
SCUSLC.COMMAND_11 11 Security Level Control Command bit 11
SCUSLC.COMMAND_10 10 Security Level Control Command bit 10
SCUSLC.COMMAND_9 9 Security Level Control Command bit 9
SCUSLC.COMMAND_8 8 Security Level Control Command bit 8
SCUSLC.COMMAND_7 7 Security Level Control Command bit 7
SCUSLC.COMMAND_6 6 Security Level Control Command bit 6
SCUSLC.COMMAND_5 5 Security Level Control Command bit 5
SCUSLC.COMMAND_4 4 Security Level Control Command bit 4
SCUSLC.COMMAND_3 3 Security Level Control Command bit 3
SCUSLC.COMMAND_2 2 Security Level Control Command bit 2
SCUSLC.COMMAND_1 1 Security Level Control Command bit 1
SCUSLC.COMMAND_0 0 Security Level Control Command bit 0
SCUSLS 0xF0C2 Security Level Status Register
SCUSLS.STATE_15 15 Current State of Switching State Machine bit 15
SCUSLS.STATE_14 14 Current State of Switching State Machine bit 14
SCUSLS.STATE_13 13 Current State of Switching State Machine bit 13
SCUSLS.SL_12 12 Security Level bit 12
SCUSLS.SL_11 11 Security Level bit 11
SCUSLS.PASSWORD_7 7 Current Security Control Password bit 7
SCUSLS.PASSWORD_6 6 Current Security Control Password bit 6
SCUSLS.PASSWORD_5 5 Current Security Control Password bit 5
SCUSLS.PASSWORD_4 4 Current Security Control Password bit 4
SCUSLS.PASSWORD_3 3 Current Security Control Password bit 3
SCUSLS.PASSWORD_2 2 Current Security Control Password bit 2
SCUSLS.PASSWORD_1 1 Current Security Control Password bit 1
SCUSLS.PASSWORD_0 0 Current Security Control Password bit 0
ASC0_TxFCON 0xF0C4 Transmit FIFO Control Register
ASC0_RxFCON 0xF0C6 Receive FIFO Control Register
RTC_RELL 0xF0CC RTC Timer Reload Low Register
RTC_RELH 0xF0CE RTC Timer Reload High Register
RTC_T14REL 0xF0D0 Timer 14 Reload Register
RTC_T14 0xF0D2 Timer 14 Register
RTC_RTCL 0xF0D4 RTC Timer Low Register
RTC_RTCH 0xF0D6 RTC Timer High Register
DTIDR 0xF0D8 Task ID register
DTIDR.TASKID_15 15
DTIDR.TASKID_14 14
DTIDR.TASKID_13 13
DTIDR.TASKID_12 12
DTIDR.TASKID_11 11
DTIDR.TASKID_10 10
DTIDR.TASKID_9 9
DTIDR.TASKID_8 8
DTIDR.TASKID_7 7
DTIDR.TASKID_6 6
DTIDR.TASKID_5 5
DTIDR.TASKID_4 4
DTIDR.TASKID_3 3
DTIDR.TASKID_2 2
DTIDR.TASKID_1 1
DTIDR.TASKID_0 0
DCMPSP 0xF0EC Select and Programming Register for DCMPx
DCMPSP.GPR 15 Selects the GPR address format
DCMPSP.SELECT_DCMP_11 11 Select the Comparison Register bit 11
DCMPSP.SELECT_DCMP_10 10 Select the Comparison Register bit 10
DCMPSP.SELECT_DCMP_9 9 Select the Comparison Register bit 9
DCMPSP.SELECT_DCMP_8 8 Select the Comparison Register bit 8
DCMPSP.DCMP_DATA_X_7 7 Sets bit 23 of selected
DCMPSP.DCMP_DATA_X_6 6 Sets bit 22 of selected
DCMPSP.DCMP_DATA_X_5 5 Sets bit 21 of selected
DCMPSP.DCMP_DATA_X_4 4 Sets bit 20 of selected
DCMPSP.DCMP_DATA_X_3 3 Sets bit 19 of selected
DCMPSP.DCMP_DATA_X_2 2 Sets bit 18 of selected
DCMPSP.DCMP_DATA_X_1 1 Sets bit 17 of selected
DCMPSP.DCMP_DATA_X_0 0 Sets bit 16 of selected
DCMPDP 0xF0EE Data programming register for DCMPx
DCMPDP.DCMP_DATA_15 15 Set bit 15 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_14 14 Set bit 14 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_13 13 Set bit 13 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_12 12 Set bit 12 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_11 11 Set bit 11 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_10 10 Set bit 10 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_9 9 Set bit 9 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_8 8 Set bit 8 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_7 7 Set bit 7 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_6 6 Set bit 6 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_5 5 Set bit 5 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_4 4 Set bit 4 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_3 3 Set bit 3 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_2 2 Set bit 2 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_1 1 Set bit 1 of selected (SELECT_DCMP) DCMP register
DCMPDP.DCMP_DATA_0 0 Set bit 0 of selected (SELECT_DCMP) DCMP register
DTREVT 0xF0F0 Hardware Trigger Combination Debug Event Control Register
DTREVT.COM_RE 15 Equal and range comparison combination
DTREVT.SELECT_E_14 14 Selects equal/range comparison bit 14
DTREVT.SELECT_E_13 13 Selects equal/range comparison bit 13
DTREVT.MODE_E 12 Controls the complex watch point generation
DTREVT.COM_R_11 11 Select range comparison bit 11
DTREVT.COM_R_10 10 Select range comparison bit 10
DTREVT.MUX_E_9 9 Equal comp. input mux control bit 9
DTREVT.MUX_E_8 8 Equal comp. input mux control bit 8
DTREVT.MUX_R_7 7 Range comparison input mux bit 7
DTREVT.MUX_R_6 6 Range comparison input mux bit 6
DTREVT.ACTIVATE_PIN 5 Identical to ACTIVATE_PIN in DEXEVT
DTREVT.ACT_S_R 4 Activate Second Range for DCMP1 & DCMP2
DTREVT.PERIPHERALS_STOP 3 Identical to PERIPHERALS_STOP in DEXEVT
DTREVT.EVENT_ACTION_1 1 Identical to EVENT_ACTION in DEXEVT bit 1
DTREVT.EVENT_ACTION_0 0 Identical to EVENT_ACTION in DEXEVT bit 0
DEXEVT 0xF0F2 Break Pin Event Control Register
DEXEVT.ACTIVATE_PIN 5
DEXEVT.PERIPHERALS_STOP 3
DEXEVT.EVENT_ACTION_1 1
DEXEVT.EVENT_ACTION_0 0
DSWEVT 0xF0F4 Software Debug Event Control Register
DSWEVT.ACTIVATE_PIN 5
DSWEVT.PERIPHERALS_STOP 3
DSWEVT.EVENT_ACTION_1 1
DSWEVT.EVENT_ACTION_0 0
CMADR 0xF0F8 Call a monitor target address register
CMADR.ADDR_15 15 Bit 15 of the Call A Monitor target address
CMADR.ADDR_14 14 Bit 14 of the Call A Monitor target address
CMADR.ADDR_13 13 Bit 13 of the Call A Monitor target address
CMADR.ADDR_12 12 Bit 12 of the Call A Monitor target address
CMADR.ADDR_11 11 Bit 11 of the Call A Monitor target address
CMADR.ADDR_10 10 Bit 10 of the Call A Monitor target address
CMADR.ADDR_9 9 Bit 9 of the Call A Monitor target address
CMADR.ADDR_8 8 Bit 8 of the Call A Monitor target address
CMADR.ADDR_7 7 Bit 7 of the Call A Monitor target address
CMADR.ADDR_6 6 Bit 6 of the Call A Monitor target address
CMADR.ADDR_5 5 Bit 5 of the Call A Monitor target address
CMADR.ADDR_4 4 Bit 4 of the Call A Monitor target address
CMADR.ADDR_3 3 Bit 3 of the Call A Monitor target address
CMADR.ADDR_2 2 Bit 2 of the Call A Monitor target address
CMADR.ADDR_1 1 Bit 1 of the Call A Monitor target address
CMADR.ADDR_0 0 Bit 0 of the Call A Monitor target address
CMCTR 0xF0FA Call a Monitor Control Register
CMCTR.LEVEL_15 15 Injection Level bit 15
CMCTR.LEVEL_14 14 Injection Level bit 14
CMCTR.LEVEL_13 13 Injection Level bit 13
CMCTR.LEVEL_12 12 Injection Level bit 12
CMCTR.LEVEL_11 11 Injection Level bit 11
CMCTR.BSEL_9 9 Selects the GPR Register Bank bit 9
CMCTR.BSEL_8 8 Selects the GPR Register Bank bit 8
CMCTR.ADDR_7 7 Bit 23 of the Call A Monitor target addres
CMCTR.ADDR_6 6 Bit 22 of the Call A Monitor target addres
CMCTR.ADDR_5 5 Bit 21 of the Call A Monitor target addres
CMCTR.ADDR_4 4 Bit 20 of the Call A Monitor target addres
CMCTR.ADDR_3 3 Bit 19 of the Call A Monitor target addres
CMCTR.ADDR_2 2 Bit 18 of the Call A Monitor target addres
CMCTR.ADDR_1 1 Bit 17 of the Call A Monitor target addres
CMCTR.ADDR_0 0 Bit 16 of the Call A Monitor target addres
DBGSR 0xF0FC Debug Status Register
DBGSR.EVENT_SOURCE_15 15 Reports source of the last debug event bit 15
DBGSR.EVENT_SOURCE_14 14 Reports source of the last debug event bit 14
DBGSR.EVENT_SOURCE_13 13 Reports source of the last debug event bit 13
DBGSR.DBGMOD 11 Specifies the debug mode to be entered in case of a break event
DBGSR.TRGEVT_E_CMP2 10
DBGSR.TRGEVT_E_CMP1 9
DBGSR.TRGEVT_E_CMP0 8
DBGSR.TRGEVT_R_CMP 7
DBGSR.SBRKC 6 Software Break Conflict
DBGSR.CBBM 5 Conditional Break Before Make
DBGSR.OPS 4 OCDS_P_SUSPEND
DBGSR.DEBUG_STATE_3 3 Current debug state bit 3
DBGSR.DEBUG_STATE_2 2 Current debug state bit 2
DBGSR.EXE_ONE_INST 1 Execute one instruction request
DBGSR.DBG_EN 0
IMBCTR 0xF0FE Instruction Memory Block Control Register
IMBCTR.RPA 15 Read Protection Activated
IMBCTR.DDF 9 Disable Data Read from Flas Memory
IMBCTR.DCF 8 Disable Code Fetch from Flas Memory
IMBCTR.WSRAM 2 Wait State Control for programm RAM acsess
IMBCTR.WSFLASH_1 1 Wait States for the Flas Memory bit 1
IMBCTR.WSFLASH_0 0 Wait States for the Flas Memory bit 0
DP0L 0xF100 P0L Direction Control Register
DP0L.P7 7
DP0L.P6 6
DP0L.P5 5
DP0L.P4 4
DP0L.P3 3
DP0L.P2 2
DP0L.P1 1
DP0L.P0 0
DP0H 0xF102 P0H Direction Control Register
DP0H.P7 7
DP0H.P6 6
DP0H.P5 5
DP0H.P4 4
DP0H.P3 3
DP0H.P2 2
DP0H.P1 1
DP0H.P0 0
DP1L 0xF104 P1L Direction Control Register
DP1L.P7 7
DP1L.P6 6
DP1L.P5 5
DP1L.P4 4
DP1L.P3 3
DP1L.P2 2
DP1L.P1 1
DP1L.P0 0
DP1H 0xF106 P1H Direction Control Register
DP1H.P7 7
DP1H.P6 6
DP1H.P5 5
DP1H.P4 4
DP1H.P3 3
DP1H.P2 2
DP1H.P1 1
DP1H.P0 0
RSTCFG 0xF108 Reset Configuration Register
RSTCFG.CLKCFG_15 15 Clock Generation Mode Configuration bit 15
RSTCFG.CLKCFG_14 14 Clock Generation Mode Configuration bit 14
RSTCFG.CLKCFG_13 13 Clock Generation Mode Configuration bit 13
RSTCFG.SALSEL_12 12 Segment Address Line Select bit 12
RSTCFG.SALSEL_11 11 Segment Address Line Select bit 11
RSTCFG.CSSEL_10 10 Chip Select Line Select bit
RSTCFG.CSSEL_9 9 Chip Select Line Select bit
RSTCFG.WRC 8 Write Configuration
RSTCFG.BUSTYP_7 7 External Bus Type bit 7
RSTCFG.BUSTYP_6 6 External Bus Type bit 6
RSTCFG.SMOD_5 5 Special Modes bit 5
RSTCFG.SMOD_4 4 Special Modes bit 4
RSTCFG.SMOD_3 3 Special Modes bit 3
RSTCFG.SMOD_2 2 Special Modes bit 2
RSTCFG.ADP 1 Adapt Mode
RSTCFG.ROC 0 RSTOUT Control
RTC_ISNC 0xF10C RTC Interrupt Sub Node Control Register Low
RTC_ISNC.CNT3IR 9
RTC_ISNC.CNT3IE 8
RTC_ISNC.CNT2IR 7
RTC_ISNC.CNT2IE 6
RTC_ISNC.CNT1IR 5
RTC_ISNC.CNT1IE 4
RTC_ISNC.CNT0IR 3
RTC_ISNC.CNT0IE 2
RTC_ISNC.T14IR 1
RTC_ISNC.T14IE 0
RTC_ISNCH 0xF10E RTC Interrupt Sub Node Control Register High
RTC_CONL 0xF110 RTC Control Register Low
RTC_CONL.ACCPOS 15
RTC_CONL.REFCLK 4
RTC_CONL.T14INC 3
RTC_CONL.T14DEC 2
RTC_CONL.PRE 1
RTC_CONL.RUN 0
RTC_CONH 0xF112 RTC Control Register High
ALTSEL0P1H 0xF120 Alternate I/O Source 0 Port P1H
ALTSEL0P1H.P7 7
ALTSEL0P1H.P6 6
ALTSEL0P1H.P5 5
ALTSEL0P1H.P4 4
ALTSEL0P1H.P3 3
ALTSEL0P1H.P2 2
ALTSEL0P1H.P1 1
ALTSEL0P1H.P0 0
ALTSEL0P3 0xF126 Alternate I/O Source Port 3 Selection
ALTSEL0P3.P13 13
ALTSEL0P3.P11 11
ALTSEL0P3.P10 10
ALTSEL0P3.P9 9
ALTSEL0P3.P8 8
ALTSEL0P3.P3 3
ALTSEL0P3.P1 1
ALTSEL1P3 0xF128 Alternate I/O Source 1 Port P3
ALTSEL1P3.P1 1
ALTSEL0P4 0xF12A Alternate I/O Source 0 Port P4
ALTSEL0P4.P7 7
ALTSEL0P4.P6 6
ALTSEL0P6 0xF12C Alternate I/O Source 0 Port P6
ALTSEL0P1L 0xF130 P1L Alternate Select Register 0
ALTSEL0P1L.P7 7
ALTSEL0P1L.P6 6
ALTSEL0P1L.P5 5
ALTSEL0P1L.P4 4
ALTSEL0P1L.P3 3
ALTSEL0P1L.P2 2
ALTSEL0P1L.P1 1
ALTSEL0P1L.P0 0
ALTSEL1P4 0xF136 Alternate I/O Source 1 Port P4
ALTSEL1P4.P7 7
ALTSEL0P9 0xF138 Alternate I/O Source 0 Port P9
ALTSEL0P9.P5 5
ALTSEL0P9.P4 4
ALTSEL0P9.P3 3
ALTSEL0P9.P2 2
ALTSEL0P9.P1 1
ALTSEL0P9.P0 0
ALTSEL1P9 0xF13A Alternate I/O Source 1 Port P9
ALTSEL1P9.P5 5
ALTSEL1P9.P4 4
ALTSEL1P9.P3 3
ALTSEL1P9.P2 2
ALTSEL1P9.P1 1
ALTSEL1P9.P0 0
ALTSEL0P7 0xF13C Alternate I/O Source 0 Port P7
ALTSEL1P7 0xF13E Alternate I/O Source 1 Port P7
CCU6_IC 0xF140 CAPCOM 6 Interrupt Control Register
CCU6_IC.GPX 8 Group Priority Extension
CCU6_IC.IR 7 Interrupt Request Flag
CCU6_IC.IE 6 Interrupt Enable Control Bit
CCU6_IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_IC.GLVL_1 1 Group Priority Level bit 1
CCU6_IC.GLVL_0 0 Group Priority Level bit 0
CAN_1IC 0xF142 CAN Mode 1 Interrupt Control register
CAN_1IC.GPX 8 Group Priority Extension
CAN_1IC.IR 7 Interrupt Request Flag
CAN_1IC.IE 6 Interrupt Enable Control Bit
CAN_1IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_1IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_1IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_1IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_1IC.GLVL_1 1 Group Priority Level bit 1
CAN_1IC.GLVL_0 0 Group Priority Level bit 0
CAN_2IC 0xF144 CAN Mode 2 Interrupt Control register
CAN_2IC.GPX 8 Group Priority Extension
CAN_2IC.IR 7 Interrupt Request Flag
CAN_2IC.IE 6 Interrupt Enable Control Bit
CAN_2IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_2IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_2IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_2IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_2IC.GLVL_1 1 Group Priority Level bit 1
CAN_2IC.GLVL_0 0 Group Priority Level bit 0
CAN_3IC 0xF146 CAN Mode 3 Interrupt Control register
CAN_3IC.GPX 8 Group Priority Extension
CAN_3IC.IR 7 Interrupt Request Flag
CAN_3IC.IE 6 Interrupt Enable Control Bit
CAN_3IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_3IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_3IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_3IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_3IC.GLVL_1 1 Group Priority Level bit 1
CAN_3IC.GLVL_0 0 Group Priority Level bit 0
CAN_4IC 0xF148 CAN Mode 4 Interrupt Control register
CAN_4IC.GPX 8 Group Priority Extension
CAN_4IC.IR 7 Interrupt Request Flag
CAN_4IC.IE 6 Interrupt Enable Control Bit
CAN_4IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_4IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_4IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_4IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_4IC.GLVL_1 1 Group Priority Level bit 1
CAN_4IC.GLVL_0 0 Group Priority Level bit 0
CAN_5IC 0xF14A CAN Mode 5 Interrupt Control register
CAN_5IC.GPX 8 Group Priority Extension
CAN_5IC.IR 7 Interrupt Request Flag
CAN_5IC.IE 6 Interrupt Enable Control Bit
CAN_5IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_5IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_5IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_5IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_5IC.GLVL_1 1 Group Priority Level bit 1
CAN_5IC.GLVL_0 0 Group Priority Level bit 0
CAN_6IC 0xF14C CAN Mode 6 Interrupt Control register
CAN_6IC.GPX 8 Group Priority Extension
CAN_6IC.IR 7 Interrupt Request Flag
CAN_6IC.IE 6 Interrupt Enable Control Bit
CAN_6IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_6IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_6IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_6IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_6IC.GLVL_1 1 Group Priority Level bit 1
CAN_6IC.GLVL_0 0 Group Priority Level bit 0
CAN_7IC 0xF14E CAN Mode 7 Interrupt Control register
CAN_7IC.GPX 8 Group Priority Extension
CAN_7IC.IR 7 Interrupt Request Flag
CAN_7IC.IE 6 Interrupt Enable Control Bit
CAN_7IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_7IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_7IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_7IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_7IC.GLVL_1 1 Group Priority Level bit 1
CAN_7IC.GLVL_0 0 Group Priority Level bit 0
ASC1_TBIC 0xF150 ASC1 Transmit Buffer Interrupt Control Register
ASC1_TBIC.GPX 8 Group Priority Extension
ASC1_TBIC.IR 7 Interrupt Request Flag
ASC1_TBIC.IE 6 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_TBIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_TBIC.GLVL_1 1 Group Priority Level bit 1
ASC1_TBIC.GLVL_0 0 Group Priority Level bit 0
ASC0_ABIC 0xF15C ASC0 Autobaud Interrupt Control Register
ASC0_ABIC.GPX 8 Group Priority Extension
ASC0_ABIC.IR 7 Interrupt Request Flag
ASC0_ABIC.IE 6 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_ABIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_ABIC.GLVL_1 1 Group Priority Level bit 1
ASC0_ABIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC16IC 0xF160 CAPCOM Channel 16 Interrupt Control Register
CC2_CC16IC.GPX 8 Group Priority Extension
CC2_CC16IC.IR 7 Interrupt Request Flag
CC2_CC16IC.IE 6 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC16IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC16IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC16IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC17IC 0xF162 CAPCOM Channel 17 Interrupt Control Register
CC2_CC17IC.GPX 8 Group Priority Extension
CC2_CC17IC.IR 7 Interrupt Request Flag
CC2_CC17IC.IE 6 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC17IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC17IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC17IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC18IC 0xF164 CAPCOM Channel 18 Interrupt Control Register
CC2_CC18IC.GPX 8 Group Priority Extension
CC2_CC18IC.IR 7 Interrupt Request Flag
CC2_CC18IC.IE 6 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC18IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC18IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC18IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC19IC 0xF166 CAPCOM Channel 19 Interrupt Control Register
CC2_CC19IC.GPX 8 Group Priority Extension
CC2_CC19IC.IR 7 Interrupt Request Flag
CC2_CC19IC.IE 6 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC19IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC19IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC19IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC20IC 0xF168 CAPCOM Channel 20 Interrupt Control Register
CC2_CC20IC.GPX 8 Group Priority Extension
CC2_CC20IC.IR 7 Interrupt Request Flag
CC2_CC20IC.IE 6 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC20IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC20IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC20IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC21IC 0xF16A CAPCOM Channel 21 Interrupt Control Register
CC2_CC21IC.GPX 8 Group Priority Extension
CC2_CC21IC.IR 7 Interrupt Request Flag
CC2_CC21IC.IE 6 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC21IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC21IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC21IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC22IC 0xF16C CAPCOM Channel 22 Interrupt Control Register
CC2_CC22IC.GPX 8 Group Priority Extension
CC2_CC22IC.IR 7 Interrupt Request Flag
CC2_CC22IC.IE 6 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC22IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC22IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC22IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC23IC 0xF16E CAPCOM Channel 23 Interrupt Control Register
CC2_CC23IC.GPX 8 Group Priority Extension
CC2_CC23IC.IR 7 Interrupt Request Flag
CC2_CC23IC.IE 6 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC23IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC23IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC23IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC24IC 0xF170 CAPCOM Channel 24 Interrupt Control Register
CC2_CC24IC.GPX 8 Group Priority Extension
CC2_CC24IC.IR 7 Interrupt Request Flag
CC2_CC24IC.IE 6 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC24IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC24IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC24IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC25IC 0xF172 CAPCOM Channel 25 Interrupt Control Register
CC2_CC25IC.GPX 8 Group Priority Extension
CC2_CC25IC.IR 7 Interrupt Request Flag
CC2_CC25IC.IE 6 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC25IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC25IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC25IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC26IC 0xF174 CAPCOM Channel 26 Interrupt Control Register
CC2_CC26IC.GPX 8 Group Priority Extension
CC2_CC26IC.IR 7 Interrupt Request Flag
CC2_CC26IC.IE 6 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC26IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC26IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC26IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC27IC 0xF176 CAPCOM Channel 27 Interrupt Control Register
CC2_CC27IC.GPX 8 Group Priority Extension
CC2_CC27IC.IR 7 Interrupt Request Flag
CC2_CC27IC.IE 6 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC27IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC27IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC27IC.GLVL_0 0 Group Priority Level bit 0
CC2_CC28IC 0xF178 CAPCOM Channel 28 Interrupt Control Register
CC2_CC28IC.GPX 8 Group Priority Extension
CC2_CC28IC.IR 7 Interrupt Request Flag
CC2_CC28IC.IE 6 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC28IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC28IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC28IC.GLVL_0 0 Group Priority Level bit 0
CC2_T7IC 0xF17A CAPCOM 2 Timer 7 Interrupt Control Register
CC2_T7IC.GPX 8 Group Priority Extension
CC2_T7IC.IR 7 Interrupt Request Flag
CC2_T7IC.IE 6 Interrupt Enable Control Bit
CC2_T7IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_T7IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_T7IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_T7IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_T7IC.GLVL_1 1 Group Priority Level bit 1
CC2_T7IC.GLVL_0 0 Group Priority Level bit 0
CC2_T8IC 0xF17C CAPCOM 2 Timer 8 Interrupt Control Register
CC2_T8IC.GPX 8 Group Priority Extension
CC2_T8IC.IR 7 Interrupt Request Flag
CC2_T8IC.IE 6 Interrupt Enable Control Bit
CC2_T8IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_T8IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_T8IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_T8IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_T8IC.GLVL_1 1 Group Priority Level bit 1
CC2_T8IC.GLVL_0 0 Group Priority Level bit 0
EOPIC 0xF180 End of PEC Interrupt Control Register
EOPIC.GPX 8 Group Priority Extension
EOPIC.IR 7 Interrupt Request Flag
EOPIC.IE 6 Interrupt Enable Control Bit
EOPIC.ILVL_5 5 Interrupt Enable Control Bit
EOPIC.ILVL_4 4 Interrupt Enable Control Bit
EOPIC.ILVL_3 3 Interrupt Enable Control Bit
EOPIC.ILVL_2 2 Interrupt Enable Control Bit
EOPIC.GLVL_1 1 Group Priority Level bit 1
EOPIC.GLVL_0 0 Group Priority Level bit 0
ASC1_TIC 0xF182 ASC1 Transmit Interrupt Control Register
ASC1_TIC.GPX 8 Group Priority Extension
ASC1_TIC.IR 7 Interrupt Request Flag
ASC1_TIC.IE 6 Interrupt Enable Control Bit
ASC1_TIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_TIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_TIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_TIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_TIC.GLVL_1 1 Group Priority Level bit 1
ASC1_TIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC29IC 0xF184 CAPCOM Channel 29 Interrupt Control Register
CC2_CC29IC.GPX 8 Group Priority Extension
CC2_CC29IC.IR 7 Interrupt Request Flag
CC2_CC29IC.IE 6 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC29IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC29IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC29IC.GLVL_0 0 Group Priority Level bit 0
IIC_DIC 0xF186 IIC Data Interrupt Control Register
CCU6_EIC 0xF188 CAPCOM 6 Emergency Interrupt Control Register
CCU6_EIC.GPX 8 Group Priority Extension
CCU6_EIC.IR 7 Interrupt Request Flag
CCU6_EIC.IE 6 Interrupt Enable Control Bit
CCU6_EIC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_EIC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_EIC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_EIC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_EIC.GLVL_1 1 Group Priority Level bit 1
CCU6_EIC.GLVL_0 0 Group Priority Level bit 0
ASC1_RIC 0xF18A ASC1 Receive Interrupt Control Register
ASC1_RIC.GPX 8 Group Priority Extension
ASC1_RIC.IR 7 Interrupt Request Flag
ASC1_RIC.IE 6 Interrupt Enable Control Bit
ASC1_RIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_RIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_RIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_RIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_RIC.GLVL_1 1 Group Priority Level bit 1
ASC1_RIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC30IC 0xF18C CAPCOM Channel 30 Interrupt Control Register
CC2_CC30IC.GPX 8 Group Priority Extension
CC2_CC30IC.IR 7 Interrupt Request Flag
CC2_CC30IC.IE 6 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC30IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC30IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC30IC.GLVL_0 0 Group Priority Level bit 0
IIC_PEIC 0xF18E IIC Protocol Event Interrupt Control Register
CCU6_T12IC 0xF190 CAPCOM 6 Timer 12 Interrupt Control Register
CCU6_T12IC.GPX 8 Group Priority Extension
CCU6_T12IC.IR 7 Interrupt Request Flag
CCU6_T12IC.IE 6 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_T12IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_T12IC.GLVL_1 1 Group Priority Level bit 1
CCU6_T12IC.GLVL_0 0 Group Priority Level bit 0
ASC1_EIC 0xF192 ASC1 Error Interrupt Control Register
ASC1_EIC.GPX 8 Group Priority Extension
ASC1_EIC.IR 7 Interrupt Request Flag
ASC1_EIC.IE 6 Interrupt Enable Control Bit
ASC1_EIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_EIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_EIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_EIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_EIC.GLVL_1 1 Group Priority Level bit 1
ASC1_EIC.GLVL_0 0 Group Priority Level bit 0
CC2_CC31IC 0xF194 CAPCOM Channel 31 Interrupt Control Register
CC2_CC31IC.GPX 8 Group Priority Extension
CC2_CC31IC.IR 7 Interrupt Request Flag
CC2_CC31IC.IE 6 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_5 5 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_4 4 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_3 3 Interrupt Enable Control Bit
CC2_CC31IC.ILVL_2 2 Interrupt Enable Control Bit
CC2_CC31IC.GLVL_1 1 Group Priority Level bit 1
CC2_CC31IC.GLVL_0 0 Group Priority Level bit 0
CAN_0IC 0xF196 CAN Mode 0 Interrupt Control register
CAN_0IC.GPX 8 Group Priority Extension
CAN_0IC.IR 7 Interrupt Request Flag
CAN_0IC.IE 6 Interrupt Enable Control Bit
CAN_0IC.ILVL_5 5 Interrupt Enable Control Bit
CAN_0IC.ILVL_4 4 Interrupt Enable Control Bit
CAN_0IC.ILVL_3 3 Interrupt Enable Control Bit
CAN_0IC.ILVL_2 2 Interrupt Enable Control Bit
CAN_0IC.GLVL_1 1 Group Priority Level bit 1
CAN_0IC.GLVL_0 0 Group Priority Level bit 0
CCU6_T13IC 0xF198 CAPCOM 6 Timer 13 Interrupt Control Register
CCU6_T13IC.GPX 8 Group Priority Extension
CCU6_T13IC.IR 7 Interrupt Request Flag
CCU6_T13IC.IE 6 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_5 5 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_4 4 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_3 3 Interrupt Enable Control Bit
CCU6_T13IC.ILVL_2 2 Interrupt Enable Control Bit
CCU6_T13IC.GLVL_1 1 Group Priority Level bit 1
CCU6_T13IC.GLVL_0 0 Group Priority Level bit 0
SDLM_IC 0xF19A SDLM Interrupt Control Register
ASC0_TBIC 0xF19C ASC0 Transmit Buffer Interrupt Control Register
ASC0_TBIC.GPX 8 Group Priority Extension
ASC0_TBIC.IR 7 Interrupt Request Flag
ASC0_TBIC.IE 6 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_TBIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_TBIC.GLVL_1 1 Group Priority Level bit 1
ASC0_TBIC.GLVL_0 0 Group Priority Level bit 0
PLLIC 0xF19E PLL Interrupt Control Register
PLLIC.GPX 8 Group Priority Extension
PLLIC.IR 7 Interrupt Request Flag
PLLIC.IE 6 Interrupt Enable Control Bit
PLLIC.ILVL_5 5 Interrupt Enable Control Bit
PLLIC.ILVL_4 4 Interrupt Enable Control Bit
PLLIC.ILVL_3 3 Interrupt Enable Control Bit
PLLIC.ILVL_2 2 Interrupt Enable Control Bit
PLLIC.GLVL_1 1 Group Priority Level bit 1
PLLIC.GLVL_0 0 Group Priority Level bit 0
RTC_IC 0xF1A0 RTC Interrupt Control Register
RTC_IC.GPX 8 Group Priority Extension
RTC_IC.IR 7 Interrupt Request Flag
RTC_IC.IE 6 Interrupt Enable Control Bit
RTC_IC.ILVL_5 5 Interrupt Enable Control Bit
RTC_IC.ILVL_4 4 Interrupt Enable Control Bit
RTC_IC.ILVL_3 3 Interrupt Enable Control Bit
RTC_IC.ILVL_2 2 Interrupt Enable Control Bit
RTC_IC.GLVL_1 1 Group Priority Level bit 1
RTC_IC.GLVL_0 0 Group Priority Level bit 0
SSC1_TIC 0xF1AA SSC1 Transmit Interrupt Control Register
SSC1_TIC.GPX 8 Group Priority Extension
SSC1_TIC.IR 7 Interrupt Request Flag
SSC1_TIC.IE 6 Interrupt Enable Control Bit
SSC1_TIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_TIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_TIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_TIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_TIC.GLVL_1 1 Group Priority Level bit 1
SSC1_TIC.GLVL_0 0 Group Priority Level bit 0
SSC1_RIC 0xF1AC SSC1 Receive Interrupt Control Register
SSC1_RIC.GPX 8 Group Priority Extension
SSC1_RIC.IR 7 Interrupt Request Flag
SSC1_RIC.IE 6 Interrupt Enable Control Bit
SSC1_RIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_RIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_RIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_RIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_RIC.GLVL_1 1 Group Priority Level bit 1
SSC1_RIC.GLVL_0 0 Group Priority Level bit 0
SSC1_EIC 0xF1AE SSC Error Interrupt Control Register
SSC1_EIC.GPX 8 Group Priority Extension
SSC1_EIC.IR 7 Interrupt Request Flag
SSC1_EIC.IE 6 Interrupt Enable Control Bit
SSC1_EIC.ILVL_5 5 Interrupt Enable Control Bit
SSC1_EIC.ILVL_4 4 Interrupt Enable Control Bit
SSC1_EIC.ILVL_3 3 Interrupt Enable Control Bit
SSC1_EIC.ILVL_2 2 Interrupt Enable Control Bit
SSC1_EIC.GLVL_1 1 Group Priority Level bit 1
SSC1_EIC.GLVL_0 0 Group Priority Level bit 0
ASC0_ABCON 0xF1B8 ASC0 Autobaud Control Register
ASC1_ABIC 0xF1BA ASC1 Autobaud Interrupt Control Register
ASC1_ABIC.GPX 8 Group Priority Extension
ASC1_ABIC.IR 7 Interrupt Request Flag
ASC1_ABIC.IE 6 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_5 5 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_4 4 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_3 3 Interrupt Enable Control Bit
ASC1_ABIC.ILVL_2 2 Interrupt Enable Control Bit
ASC1_ABIC.GLVL_1 1 Group Priority Level bit 1
ASC1_ABIC.GLVL_0 0 Group Priority Level bit 0
ASC1_ABCON 0xF1BC ASC1 Autobaud Control Register
ASC1_ABCON.RXINV 11
ASC1_ABCON.TXINV 10
ASC1_ABCON.FCDETEN 4
ASC1_ABCON.ABDETEN 3
ASC1_ABCON.ABSTEN 2
ASC1_ABCON.AUREN 1
ASC1_ABCON.ABEN 0
SYSCON0 0xF1BE General System Control Register
SYSCON0.RTCRST 15 RTC Reset Trigger
SYSCON0.RTCCM 14 RTC Clocking Mode
EXICON 0xF1C0 External Interrupt Control Register
EXICON.EXI7ES_15 15 External Interrupt 7 Edge Selection Field bit 15
EXICON.EXI7ES_14 14 External Interrupt 7 Edge Selection Field bit 14
EXICON.EXI6ES_13 13 External Interrupt 6 Edge Selection Field bit 13
EXICON.EXI6ES_12 12 External Interrupt 6 Edge Selection Field bit 12
EXICON.EXI5ES_11 11 External Interrupt 5 Edge Selection Field bit 11
EXICON.EXI5ES_10 10 External Interrupt 5 Edge Selection Field bit 10
EXICON.EXI4ES_9 9 External Interrupt 4 Edge Selection Field bit 9
EXICON.EXI4ES_8 8 External Interrupt 4 Edge Selection Field bit 8
EXICON.EXI3ES_7 7 External Interrupt 3 Edge Selection Field bit 7
EXICON.EXI3ES_6 6 External Interrupt 3 Edge Selection Field bit 6
EXICON.EXI2ES_5 5 External Interrupt 2 Edge Selection Field bit 5
EXICON.EXI2ES_4 4 External Interrupt 2 Edge Selection Field bit 4
EXICON.EXI1ES_3 3 External Interrupt 1 Edge Selection Field bit 3
EXICON.EXI1ES_2 2 External Interrupt 1 Edge Selection Field bit 2
EXICON.EXI0ES_1 1 External Interrupt 0 Edge Selection Field bit 1
EXICON.EXI0ES_0 0 External Interrupt 0 Edge Selection Field bit 0
ODP2 0xF1C2 Port 2 Open Drain Control Register
PICON 0xF1C4 Port Input Control Register
PICON.P20HIN 9
PICON.P20LIN 8
PICON.P9LIN 7
PICON.P4LIN 4
PICON.P3HIN 3
PICON.P3LIN 2
ODP3 0xF1C6 Port 3 Open Drain Control Register
ODP3.P13 13
ODP3.P12 12
ODP3.P11 11
ODP3.P10 10
ODP3.P9 9
ODP3.P8 8
ODP3.P7 7
ODP3.P6 6
ODP3.P5 5
ODP3.P4 4
ODP3.P3 3
ODP3.P2 2
ODP3.P1 1
ODP3.P0 0
ODP4 0xF1CA Port 4 Open Drain Control Register
ODP4.P7 7
ODP4.P6 6
ODP4.P5 5
ODP4.P4 4
ODP4.P3 3
ODP4.P2 2
ODP4.P1 1
ODP4.P0 0
ODP6 0xF1CE Port 6 Open Drain Control Register
ODP6.P7 7
ODP6.P6 6
ODP6.P5 5
ODP6.P4 4
ODP6.P3 3
ODP6.P2 2
ODP6.P1 1
ODP6.P0 0
PLLCON 0xF1D0 PLL Control Register
PLLCON.PLLWRI 15 PLLCON Write Ignore Flag
PLLCON.PLLCTRL_14 14 PLL Operation Control bit 14
PLLCON.PLLCTRL_13 13 PLL Operation Control bit 13
PLLCON.PLLMUL_12 12 PLL Multiplication Factor bit 12
PLLCON.PLLMUL_11 11 PLL Multiplication Factor bit 11
PLLCON.PLLMUL_10 10 PLL Multiplication Factor bit 10
PLLCON.PLLMUL_9 9 PLL Multiplication Factor bit 9
PLLCON.PLLMUL_8 8 PLL Multiplication Factor bit 8
PLLCON.PLLVB_7 7 PLL VCO Band Select bit 7
PLLCON.PLLVB_6 6 PLL VCO Band Select bit 6
PLLCON.PLLIDIV_5 5 PLL Input Divider bit 5
PLLCON.PLLIDIV_4 4 PLL Input Divider bit 4
PLLCON.PLLODIV_3 3 PLL Output Divider bit 3
PLLCON.PLLODIV_2 2 PLL Output Divider bit 2
PLLCON.PLLODIV_1 1 PLL Output Divider bit 1
PLLCON.PLLODIV_0 0 PLL Output Divider bit 0
ODP7 0xF1D2 Port 7 Open Drain Control Register
ODP7.P7 7
ODP7.P6 6
ODP7.P5 5
ODP7.P4 4
SYSCON3 0xF1D4 System Control Register 3
SYSCON3.SSC1DIS 15 Synchronous Serial Channel SSC1
SYSCON3.RTCDIS 14 Real Time Clock
SYSCON3.CANDIS 13 On-chip CAN Module
SYSCON3.SDLMDIS 12 On-chip SDLM (J1850 Module)
SYSCON3.I2CDIS 11 On-chip IIC Bus Module
SYSCON3.ASC1DIS 10 USART ASC1
SYSCON3.CC6DIS 8 CAPCOM6 Unit
SYSCON3.CC2DIS 7 CAPCOM Unit 2
SYSCON3.CC1DIS 6 CAPCOM Unit 1
SYSCON3.PFMDIS 5 Program Flash Module
SYSCON3.GPTDIS 3 General Purpose Timer Blocks
SYSCON3.SSC0DIS 2 Synchronous Serial Channel SSC0
SYSCON3.ASC0DIS 1 USART ASC0
SYSCON3.ADCDIS 0 Analog/Digital Converter
EXISEL1 0xF1D8 External Interrupt Input Select Register
EXISEL1.EXI7SS_15 15 External Interrupt 7 Source Selection Field bit 15
EXISEL1.EXI7SS_14 14 External Interrupt 7 Source Selection Field bit 14
EXISEL1.EXI7SS_13 13 External Interrupt 7 Source Selection Field bit 13
EXISEL1.EXI7SS_12 12 External Interrupt 7 Source Selection Field bit 12
EXISEL1.EXI6SS_11 11 External Interrupt 6 Source Selection Field bit 11
EXISEL1.EXI6SS_10 10 External Interrupt 6 Source Selection Field bit 10
EXISEL1.EXI6SS_9 9 External Interrupt 6 Source Selection Field bit 9
EXISEL1.EXI6SS_8 8 External Interrupt 6 Source Selection Field bit 8
EXISEL1.EXI5SS_7 7 External Interrupt 5 Source Selection Field bit 7
EXISEL1.EXI5SS_6 6 External Interrupt 5 Source Selection Field bit 6
EXISEL1.EXI5SS_5 5 External Interrupt 5 Source Selection Field bit 5
EXISEL1.EXI5SS_4 4 External Interrupt 5 Source Selection Field bit 4
EXISEL1.EXI4SS_3 3 External Interrupt 4 Source Selection Field bit 3
EXISEL1.EXI4SS_2 2 External Interrupt 4 Source Selection Field bit 2
EXISEL1.EXI4SS_1 1 External Interrupt 4 Source Selection Field bit 1
EXISEL1.EXI4SS_0 0 External Interrupt 4 Source Selection Field bit 0
EXISEL0 0xF1DA External Interrupt Input Select Register
EXISEL0.EXI3SS_15 15 External Interrupt 3 Source Selection Field bit 15
EXISEL0.EXI3SS_14 14 External Interrupt 3 Source Selection Field bit 14
EXISEL0.EXI3SS_13 13 External Interrupt 3 Source Selection Field bit 13
EXISEL0.EXI3SS_12 12 External Interrupt 3 Source Selection Field bit 12
EXISEL0.EXI2SS_11 11 External Interrupt 2 Source Selection Field bit 11
EXISEL0.EXI2SS_10 10 External Interrupt 2 Source Selection Field bit 10
EXISEL0.EXI2SS_9 9 External Interrupt 2 Source Selection Field bit 9
EXISEL0.EXI2SS_8 8 External Interrupt 2 Source Selection Field bit 8
EXISEL0.EXI1SS_7 7 External Interrupt 1 Source Selection Field bit 7
EXISEL0.EXI1SS_6 6 External Interrupt 1 Source Selection Field bit 6
EXISEL0.EXI1SS_5 5 External Interrupt 1 Source Selection Field bit 5
EXISEL0.EXI1SS_4 4 External Interrupt 1 Source Selection Field bit 4
EXISEL0.EXI0SS_3 3 External Interrupt 0 Source Selection Field bit 3
EXISEL0.EXI0SS_2 2 External Interrupt 0 Source Selection Field bit 2
EXISEL0.EXI0SS_1 1 External Interrupt 0 Source Selection Field bit 1
EXISEL0.EXI0SS_0 0 External Interrupt 0 Source Selection Field bit 0
SYSCON1 0xF1DC System Control Register 1
SYSCON1.CPSYS 8 Clock Prescaler for System
SYSCON1.PFCFG_5 5 Program Flash Configuration bit 5
SYSCON1.PFCFG_4 4 Program Flash Configuration bit 4
SYSCON1.PDCFG_3 3 Port Driver Configuration bit 3
SYSCON1.PDCFG_2 2 Port Driver Configuration bit 2
SYSCON1.SLEEPCON_1 1 SLEEP Mode Configuration bit 1
SYSCON1.SLEEPCON_0 0 SLEEP Mode Configuration bit 0
RSTCON 0xF1E0 Reset Control Register
RSTCON.RODIS 7 RSTOUT Disable Control
RSTCON.ROCON 6 RSTOUT Control Switching ON
RSTCON.ROCOFF 5 RSTOUT Control Switching Off
RSTCON.RORMV 4 RSTOUT Remove Control
RSTCON.RSTLEN_2 2 Reset Length Control bit 2
RSTCON.RSTLEN_1 1 Reset Length Control bit 1
RSTCON.RSTLEN_0 0 Reset Length Control bit 0
SYSSTAT 0xF1E4 System Status Register
SYSSTAT.OSCLOCK 15 Oscillator Signal Status Bit
SYSSTAT.PLLLOCK 14 PLL Signal Status Bit
SYSSTAT.CLKHIX 13 Input Clock High Limit Exceeded
SYSSTAT.CLKLOX 12 Input Clock Low Limit Exceeded
SYSSTAT.PLLEM 10 PLL Emergency Mode Flag
SYSSTAT.HWR 2 Hardware Reset Indication Flag
SYSSTAT.SWR 1 Software Reset Indication Flag
SYSSTAT.WDTR 0 Watchdog Timer Reset Indication Flag
DPP0 0xFE00 Data Page Pointer 0 Register
DPP0.PN_9 9 Data Page Number of DPP bit 9
DPP0.PN_8 8 Data Page Number of DPP bit 8
DPP0.PN_7 7 Data Page Number of DPP bit 7
DPP0.PN_6 6 Data Page Number of DPP bit 6
DPP0.PN_5 5 Data Page Number of DPP bit 5
DPP0.PN_4 4 Data Page Number of DPP bit 4
DPP0.PN_3 3 Data Page Number of DPP bit 3
DPP0.PN_2 2 Data Page Number of DPP bit 2
DPP0.PN_1 1 Data Page Number of DPP bit 1
DPP0.PN_0 0 Data Page Number of DPP bit 0
DPP1 0xFE02 Data Page Pointer 1 Register
DPP1.PN_9 9 Data Page Number of DPP bit 9
DPP1.PN_8 8 Data Page Number of DPP bit 8
DPP1.PN_7 7 Data Page Number of DPP bit 7
DPP1.PN_6 6 Data Page Number of DPP bit 6
DPP1.PN_5 5 Data Page Number of DPP bit 5
DPP1.PN_4 4 Data Page Number of DPP bit 4
DPP1.PN_3 3 Data Page Number of DPP bit 3
DPP1.PN_2 2 Data Page Number of DPP bit 2
DPP1.PN_1 1 Data Page Number of DPP bit 1
DPP1.PN_0 0 Data Page Number of DPP bit 0
DPP2 0xFE04 Data Page Pointer 2 Register
DPP2.PN_9 9 Data Page Number of DPP bit 9
DPP2.PN_8 8 Data Page Number of DPP bit 8
DPP2.PN_7 7 Data Page Number of DPP bit 7
DPP2.PN_6 6 Data Page Number of DPP bit 6
DPP2.PN_5 5 Data Page Number of DPP bit 5
DPP2.PN_4 4 Data Page Number of DPP bit 4
DPP2.PN_3 3 Data Page Number of DPP bit 3
DPP2.PN_2 2 Data Page Number of DPP bit 2
DPP2.PN_1 1 Data Page Number of DPP bit 1
DPP2.PN_0 0 Data Page Number of DPP bit 0
DPP3 0xFE06 Data Page Pointer 3 Register
DPP3.PN_9 9 Data Page Number of DPP bit 9
DPP3.PN_8 8 Data Page Number of DPP bit 8
DPP3.PN_7 7 Data Page Number of DPP bit 7
DPP3.PN_6 6 Data Page Number of DPP bit 6
DPP3.PN_5 5 Data Page Number of DPP bit 5
DPP3.PN_4 4 Data Page Number of DPP bit 4
DPP3.PN_3 3 Data Page Number of DPP bit 3
DPP3.PN_2 2 Data Page Number of DPP bit 2
DPP3.PN_1 1 Data Page Number of DPP bit 1
DPP3.PN_0 0 Data Page Number of DPP bit 0
CSP 0xFE08 Code Segment Pointer Register
CSP.SEGNR_7 7
CSP.SEGNR_6 6
CSP.SEGNR_5 5
CSP.SEGNR_4 4
CSP.SEGNR_3 3
CSP.SEGNR_2 2
CSP.SEGNR_1 1
CSP.SEGNR_0 0
EMUCON 0xFE0A Emulation Control Reg.
EMUCON.OCEN 2 OCDS/Cerberus Enable
EMUCON.OCDSIOEN 1 OCDS Break Input/Output Enable
MDH 0xFE0C Multiply Divide Register - High Word
MDH.MDH_15 15 High part of MD bit 15
MDH.MDH_14 14 High part of MD bit 14
MDH.MDH_13 13 High part of MD bit 13
MDH.MDH_12 12 High part of MD bit 12
MDH.MDH_11 11 High part of MD bit 11
MDH.MDH_10 10 High part of MD bit 10
MDH.MDH_9 9 High part of MD bit 9
MDH.MDH_8 8 High part of MD bit 8
MDH.MDH_7 7 High part of MD bit 7
MDH.MDH_6 6 High part of MD bit 6
MDH.MDH_5 5 High part of MD bit 5
MDH.MDH_4 4 High part of MD bit 4
MDH.MDH_3 3 High part of MD bit 3
MDH.MDH_2 2 High part of MD bit 2
MDH.MDH_1 1 High part of MD bit 1
MDH.MDH_0 0 High part of MD bit 0
MDL 0xFE0E Multiply Divide Register - Low Word
MDL.MDL_15 15 Low part of MD bit 15
MDL.MDL_14 14 Low part of MD bit 14
MDL.MDL_13 13 Low part of MD bit 13
MDL.MDL_12 12 Low part of MD bit 12
MDL.MDL_11 11 Low part of MD bit 11
MDL.MDL_10 10 Low part of MD bit 10
MDL.MDL_9 9 Low part of MD bit 9
MDL.MDL_8 8 Low part of MD bit 8
MDL.MDL_7 7 Low part of MD bit 7
MDL.MDL_6 6 Low part of MD bit 6
MDL.MDL_5 5 Low part of MD bit 5
MDL.MDL_4 4 Low part of MD bit 4
MDL.MDL_3 3 Low part of MD bit 3
MDL.MDL_2 2 Low part of MD bit 2
MDL.MDL_1 1 Low part of MD bit 1
MDL.MDL_0 0 Low part of MD bit 0
CP 0xFE10 Context Pointer Register
CP.CONTEXT_POINTER_11 11 Modifiable Portion of register CP bit 11
CP.CONTEXT_POINTER_10 10 Modifiable Portion of register CP bit 10
CP.CONTEXT_POINTER_9 9 Modifiable Portion of register CP bit 9
CP.CONTEXT_POINTER_8 8 Modifiable Portion of register CP bit 8
CP.CONTEXT_POINTER_7 7 Modifiable Portion of register CP bit 7
CP.CONTEXT_POINTER_6 6 Modifiable Portion of register CP bit 6
CP.CONTEXT_POINTER_5 5 Modifiable Portion of register CP bit 5
CP.CONTEXT_POINTER_4 4 Modifiable Portion of register CP bit 4
CP.CONTEXT_POINTER_3 3 Modifiable Portion of register CP bit 3
CP.CONTEXT_POINTER_2 2 Modifiable Portion of register CP bit 2
CP.CONTEXT_POINTER_1 1 Modifiable Portion of register CP bit 1
SP 0xFE12 Stack Pointer Register
SP.SP_15 15 Modifiable portion of register SP bit 15
SP.SP_14 14 Modifiable portion of register SP bit 14
SP.SP_13 13 Modifiable portion of register SP bit 13
SP.SP_12 12 Modifiable portion of register SP bit 12
SP.SP_11 11 Modifiable portion of register SP bit 11
SP.SP_10 10 Modifiable portion of register SP bit 10
SP.SP_9 9 Modifiable portion of register SP bit 9
SP.SP_8 8 Modifiable portion of register SP bit 8
SP.SP_7 7 Modifiable portion of register SP bit 7
SP.SP_6 6 Modifiable portion of register SP bit 6
SP.SP_5 5 Modifiable portion of register SP bit 5
SP.SP_4 4 Modifiable portion of register SP bit 4
SP.SP_3 3 Modifiable portion of register SP bit 3
SP.SP_2 2 Modifiable portion of register SP bit 2
SP.SP_1 1 Modifiable portion of register SP bit 1
STKOV 0xFE14 Stack Overflow Pointer Register
STKOV.STKOV_15 15 Modifiable portion of register STKOV bit 15
STKOV.STKOV_14 14 Modifiable portion of register STKOV bit 14
STKOV.STKOV_13 13 Modifiable portion of register STKOV bit 13
STKOV.STKOV_12 12 Modifiable portion of register STKOV bit 12
STKOV.STKOV_11 11 Modifiable portion of register STKOV bit 11
STKOV.STKOV_10 10 Modifiable portion of register STKOV bit 10
STKOV.STKOV_9 9 Modifiable portion of register STKOV bit 9
STKOV.STKOV_8 8 Modifiable portion of register STKOV bit 8
STKOV.STKOV_7 7 Modifiable portion of register STKOV bit 7
STKOV.STKOV_6 6 Modifiable portion of register STKOV bit 6
STKOV.STKOV_5 5 Modifiable portion of register STKOV bit 5
STKOV.STKOV_4 4 Modifiable portion of register STKOV bit 4
STKOV.STKOV_3 3 Modifiable portion of register STKOV bit 3
STKOV.STKOV_2 2 Modifiable portion of register STKOV bit 2
STKOV.STKOV_1 1 Modifiable portion of register STKOV bit 1
STKUN 0xFE16 Stack Underflow Pointer Register
STKUN.STKUN_15 15 Modifiable portion of register STKUN bit 15
STKUN.STKUN_14 14 Modifiable portion of register STKUN bit 14
STKUN.STKUN_13 13 Modifiable portion of register STKUN bit 13
STKUN.STKUN_12 12 Modifiable portion of register STKUN bit 12
STKUN.STKUN_11 11 Modifiable portion of register STKUN bit 11
STKUN.STKUN_10 10 Modifiable portion of register STKUN bit 10
STKUN.STKUN_9 9 Modifiable portion of register STKUN bit 9
STKUN.STKUN_8 8 Modifiable portion of register STKUN bit 8
STKUN.STKUN_7 7 Modifiable portion of register STKUN bit 7
STKUN.STKUN_6 6 Modifiable portion of register STKUN bit 6
STKUN.STKUN_5 5 Modifiable portion of register STKUN bit 5
STKUN.STKUN_4 4 Modifiable portion of register STKUN bit 4
STKUN.STKUN_3 3 Modifiable portion of register STKUN bit 3
STKUN.STKUN_2 2 Modifiable portion of register STKUN bit 2
STKUN.STKUN_1 1 Modifiable portion of register STKUN bit 1
CPUCON1 0xFE18 CPU Control Register 1
CPUCON1.VECSC_6 6 Scaling factor of Vector Table bit 6
CPUCON1.VECSC_5 5 Scaling factor of Vector Table bit 5
CPUCON1.WDTCTL 4 Configuration of Watch Dog Timer
CPUCON1.SGTDIS 3 Segmentation Disable/Enable Control
CPUCON1.INTSCXT 2 Enable Interruptibility of Switch Context
CPUCON1.BP 1 Enable Branch Prediction Unit
CPUCON1.ZCJ 0 Enable Zero Cycle Jump function
CPUCON2 0xFE1A CPU Control Register 2
CPUCON2.FIFODEPTH_15 15 FIFO Depth configuration bit 15
CPUCON2.FIFODEPTH_14 14 FIFO Depth configuration bit 14
CPUCON2.FIFODEPTH_13 13 FIFO Depth configuration bit 13
CPUCON2.FIFODEPTH_12 12 FIFO Depth configuration bit 12
CPUCON2.FIFOFED_11 11 FIFO Fed configuration bit 11
CPUCON2.FIFOFED_10 10 FIFO Fed configuration bit 10
CPUCON2.BYPPF 9 Prefetch Bypass control
CPUCON2.BYPF 8 Fetch Bypass control
CPUCON2.EIOIAEN 7 Early IO Injection Acknowledge Enable
CPUCON2.STEN 6 Stall Instruction Enable
CPUCON2.LFIC 5 Linear Follower Instruction Cache
CPUCON2.OVRUN 4 Pipeline control
CPUCON2.RETST 3 Enable return Stack
CPUCON2.DAID 1 Disable Atomic Injection Deny
CPUCON2.SL 0 Enables short loop mode
CC2_SEM 0xFE28 CAPCOM 2 Single Event Control Register
CC2_SEE 0xFE2A CAPCOM 2 Single Event Enable Register
CC1_SEM 0xFE2C CAPCOM 1 Single Event Control Register
CC1_SEE 0xFE2E CAPCOM 1 Single Event Enable Register
GPT12E_T2 0xFE40 GPT1 Timer 2 Register
GPT12E_T3 0xFE42 GPT1 Timer 3 Register
GPT12E_T4 0xFE44 GPT1 Timer 4 Register
GPT12E_T5 0xFE46 GPT2 Timer 5 Register
GPT12E_T6 0xFE48 GPT2 Timer 6 Register
GPT12E_CAPREL 0xFE4A GPT12 Capture/Reload Register
GPT12E_PISEL 0xFE4C Port Input Select Register
CC1_T0 0xFE50 CAPCOM 1 Timer 0 Register
CC1_T1 0xFE52 CAPCOM 1 Timer 1 Register
CC1_T0REL 0xFE54 CAPCOM 1 Timer 0 Reload Register
CC1_T1REL 0xFE56 CC Timer 1 Reloed Register
OPSEN 0xFE58 OCE/OCDS P-Susp. En. Reg
OPSEN.SSC1SEN 15 Module xx Suspend Enable
OPSEN.RTCSEN 14 Module xx Suspend Enable
OPSEN.CC6SEN 8 Module xx Suspend Enable
OPSEN.CC2SEN 7 Module xx Suspend Enable
OPSEN.CC1SEN 6 Module xx Suspend Enable
OPSEN.GPTSEN 2 Module xx Suspend Enable
OPSEN.SSC0SEN 1 Module xx Suspend Enable
OPSEN.ASC0SEN 0 Module xx Suspend Enable
TSTMOD 0xFE5A Test-Mode Register
MAL 0xFE5C MAC Accumulator Low Word
MAL.MAL_15 15 Low part of Accumulator bit 15
MAL.MAL_14 14 Low part of Accumulator bit 14
MAL.MAL_13 13 Low part of Accumulator bit 13
MAL.MAL_12 12 Low part of Accumulator bit 12
MAL.MAL_11 11 Low part of Accumulator bit 11
MAL.MAL_10 10 Low part of Accumulator bit 10
MAL.MAL_9 9 Low part of Accumulator bit 9
MAL.MAL_8 8 Low part of Accumulator bit 8
MAL.MAL_7 7 Low part of Accumulator bit 7
MAL.MAL_6 6 Low part of Accumulator bit 6
MAL.MAL_5 5 Low part of Accumulator bit 5
MAL.MAL_4 4 Low part of Accumulator bit 4
MAL.MAL_3 3 Low part of Accumulator bit 3
MAL.MAL_2 2 Low part of Accumulator bit 2
MAL.MAL_1 1 Low part of Accumulator bit 1
MAL.MAL_0 0 Low part of Accumulator bit 0
MAH 0xFE5E MAC Accumulator High Word
MAH.MAH_15 15 High part of Accumulator bit 15
MAH.MAH_14 14 High part of Accumulator bit 14
MAH.MAH_13 13 High part of Accumulator bit 13
MAH.MAH_12 12 High part of Accumulator bit 12
MAH.MAH_11 11 High part of Accumulator bit 11
MAH.MAH_10 10 High part of Accumulator bit 10
MAH.MAH_9 9 High part of Accumulator bit 9
MAH.MAH_8 8 High part of Accumulator bit 8
MAH.MAH_7 7 High part of Accumulator bit 7
MAH.MAH_6 6 High part of Accumulator bit 6
MAH.MAH_5 5 High part of Accumulator bit 5
MAH.MAH_4 4 High part of Accumulator bit 4
MAH.MAH_3 3 High part of Accumulator bit 3
MAH.MAH_2 2 High part of Accumulator bit 2
MAH.MAH_1 1 High part of Accumulator bit 1
MAH.MAH_0 0 High part of Accumulator bit 0
CC2_CC16 0xFE60 CAPCOM 2 Register 16
CC2_CC17 0xFE62 CAPCOM 2 Register 17
CC2_CC18 0xFE64 CAPCOM 2 Register 18
CC2_CC19 0xFE66 CAPCOM 2 Register 19
CC2_CC20 0xFE68 CAPCOM 2 Register 20
CC2_CC21 0xFE6A CAPCOM 2 Register 21
CC2_CC22 0xFE6C CAPCOM 2 Register 22
CC2_CC23 0xFE6E CAPCOM 2 Register 23
CC2_CC24 0xFE70 CAPCOM 2 Register 24
CC2_CC25 0xFE72 CAPCOM 2 Register 25
CC2_CC26 0xFE74 CAPCOM 2 Register 26
CC2_CC27 0xFE76 CAPCOM 2 Register 27
CC2_CC28 0xFE78 CAPCOM 2 Register 28
CC2_CC29 0xFE7A CAPCOM 2 Register 29
CC2_CC30 0xFE7C CAPCOM 2 Register 30
CC2_CC31 0xFE7E CAPCOM 2 Register 31
CC1_CC0 0xFE80 CAPCOM 1 Register 0
CC1_CC1 0xFE82 CAPCOM 1 Register 1
CC1_CC2 0xFE84 CAPCOM 1 Register 2
CC1_CC3 0xFE86 CAPCOM 1 Register 3
CC1_CC4 0xFE88 CAPCOM 1 Register 4
CC1_CC5 0xFE8A CAPCOM 1 Register 5
CC1_CC6 0xFE8C CAPCOM 1 Register 6
CC1_CC7 0xFE8E CAPCOM 1 Register 7
CC1_CC8 0xFE90 CAPCOM 1 Register 8
CC1_CC9 0xFE92 CAPCOM 1 Register 9
CC1_CC10 0xFE94 CAPCOM 1 Register 10
CC1_CC11 0xFE96 CAPCOM 1 Register 11
CC1_CC12 0xFE98 CAPCOM 1 Register 12
CC1_CC13 0xFE9A CAPCOM 1 Register 13
CC1_CC14 0xFE9C CAPCOM 1 Register 14
CC1_CC15 0xFE9E CAPCOM 1 Register 15
ADC_DAT 0xFEA0 A/D Converter Result Register
ADC_ID 0xFEA8 A/D Converter ID Register
ASC0_PMW 0xFEAA ASC0 IrDA Pulse Mode and Width Reg.
ASC1_PMW 0xFEAC ASC1 IrDA Pulse Mode and Width Reg.
WDT 0xFEAE Watchdog Timer Register (RO)
ASC0_TBUF 0xFEB0 Serial Channel 0 Transmitter Buffer Register (WO)
ASC0_RBUF 0xFEB2 Serial Channel 0 Receiver Buffer Register (RO)
ASC0_BG 0xFEB4 Serial Channel 0 Baud Rate Generator Reload Register
ASC0_FDV 0xFEB6 Fractional Divider Register
ASC1_TBUF 0xFEB8 Serial Channel 1 Transmitter Buffer Register (WO)
ASC1_RBUF 0xFEBA Serial Channel 1 Receiver Buffer Register (RO)
ASC1_BG 0xFEBC Serial Channel 1 Baud Rate Generator Reload Register
ASC1_FDV 0xFEBE Fractional Divider Register
PECC0 0xFEC0 PEC Channel 0 Control Register
PECC0.EOPINT 14 End of PEC Interrupt Selection
PECC0.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC0.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC0.CL 11 Channel Link Control
PECC0.INC_10 10 Increment Control bit 10
PECC0.INC_9 9 Increment Control bit 9
PECC0.BWT 8 Byte/Word Transfer Selection
PECC0.COUNT_7 7 PEC Transfer Count bit 7
PECC0.COUNT_6 6 PEC Transfer Count bit 6
PECC0.COUNT_5 5 PEC Transfer Count bit 5
PECC0.COUNT_4 4 PEC Transfer Count bit 4
PECC0.COUNT_3 3 PEC Transfer Count bit 3
PECC0.COUNT_2 2 PEC Transfer Count bit 2
PECC0.COUNT_1 1 PEC Transfer Count bit 1
PECC0.COUNT_0 0 PEC Transfer Count bit 0
PECC1 0xFEC2 PEC Channel 1 Control Register
PECC1.EOPINT 14 End of PEC Interrupt Selection
PECC1.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC1.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC1.CL 11 Channel Link Control
PECC1.INC_10 10 Increment Control bit 10
PECC1.INC_9 9 Increment Control bit 9
PECC1.BWT 8 Byte/Word Transfer Selection
PECC1.COUNT_7 7 PEC Transfer Count bit 7
PECC1.COUNT_6 6 PEC Transfer Count bit 6
PECC1.COUNT_5 5 PEC Transfer Count bit 5
PECC1.COUNT_4 4 PEC Transfer Count bit 4
PECC1.COUNT_3 3 PEC Transfer Count bit 3
PECC1.COUNT_2 2 PEC Transfer Count bit 2
PECC1.COUNT_1 1 PEC Transfer Count bit 1
PECC1.COUNT_0 0 PEC Transfer Count bit 0
PECC2 0xFEC4 PEC Channel 2 Control Register
PECC2.EOPINT 14 End of PEC Interrupt Selection
PECC2.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC2.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC2.CL 11 Channel Link Control
PECC2.INC_10 10 Increment Control bit 10
PECC2.INC_9 9 Increment Control bit 9
PECC2.BWT 8 Byte/Word Transfer Selection
PECC2.COUNT_7 7 PEC Transfer Count bit 7
PECC2.COUNT_6 6 PEC Transfer Count bit 6
PECC2.COUNT_5 5 PEC Transfer Count bit 5
PECC2.COUNT_4 4 PEC Transfer Count bit 4
PECC2.COUNT_3 3 PEC Transfer Count bit 3
PECC2.COUNT_2 2 PEC Transfer Count bit 2
PECC2.COUNT_1 1 PEC Transfer Count bit 1
PECC2.COUNT_0 0 PEC Transfer Count bit 0
PECC3 0xFEC6 PEC Channel 3 Control Register
PECC3.EOPINT 14 End of PEC Interrupt Selection
PECC3.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC3.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC3.CL 11 Channel Link Control
PECC3.INC_10 10 Increment Control bit 10
PECC3.INC_9 9 Increment Control bit 9
PECC3.BWT 8 Byte/Word Transfer Selection
PECC3.COUNT_7 7 PEC Transfer Count bit 7
PECC3.COUNT_6 6 PEC Transfer Count bit 6
PECC3.COUNT_5 5 PEC Transfer Count bit 5
PECC3.COUNT_4 4 PEC Transfer Count bit 4
PECC3.COUNT_3 3 PEC Transfer Count bit 3
PECC3.COUNT_2 2 PEC Transfer Count bit 2
PECC3.COUNT_1 1 PEC Transfer Count bit 1
PECC3.COUNT_0 0 PEC Transfer Count bit 0
PECC4 0xFEC8 PEC Channel 4 Control Register
PECC4.EOPINT 14 End of PEC Interrupt Selection
PECC4.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC4.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC4.CL 11 Channel Link Control
PECC4.INC_10 10 Increment Control bit 10
PECC4.INC_9 9 Increment Control bit 9
PECC4.BWT 8 Byte/Word Transfer Selection
PECC4.COUNT_7 7 PEC Transfer Count bit 7
PECC4.COUNT_6 6 PEC Transfer Count bit 6
PECC4.COUNT_5 5 PEC Transfer Count bit 5
PECC4.COUNT_4 4 PEC Transfer Count bit 4
PECC4.COUNT_3 3 PEC Transfer Count bit 3
PECC4.COUNT_2 2 PEC Transfer Count bit 2
PECC4.COUNT_1 1 PEC Transfer Count bit 1
PECC4.COUNT_0 0 PEC Transfer Count bit 0
PECC5 0xFECA PEC Channel 5 Control Register
PECC5.EOPINT 14 End of PEC Interrupt Selection
PECC5.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC5.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC5.CL 11 Channel Link Control
PECC5.INC_10 10 Increment Control bit 10
PECC5.INC_9 9 Increment Control bit 9
PECC5.BWT 8 Byte/Word Transfer Selection
PECC5.COUNT_7 7 PEC Transfer Count bit 7
PECC5.COUNT_6 6 PEC Transfer Count bit 6
PECC5.COUNT_5 5 PEC Transfer Count bit 5
PECC5.COUNT_4 4 PEC Transfer Count bit 4
PECC5.COUNT_3 3 PEC Transfer Count bit 3
PECC5.COUNT_2 2 PEC Transfer Count bit 2
PECC5.COUNT_1 1 PEC Transfer Count bit 1
PECC5.COUNT_0 0 PEC Transfer Count bit 0
PECC6 0xFECC PEC Channel 6 Control Register
PECC6.EOPINT 14 End of PEC Interrupt Selection
PECC6.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC6.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC6.CL 11 Channel Link Control
PECC6.INC_10 10 Increment Control bit 10
PECC6.INC_9 9 Increment Control bit 9
PECC6.BWT 8 Byte/Word Transfer Selection
PECC6.COUNT_7 7 PEC Transfer Count bit 7
PECC6.COUNT_6 6 PEC Transfer Count bit 6
PECC6.COUNT_5 5 PEC Transfer Count bit 5
PECC6.COUNT_4 4 PEC Transfer Count bit 4
PECC6.COUNT_3 3 PEC Transfer Count bit 3
PECC6.COUNT_2 2 PEC Transfer Count bit 2
PECC6.COUNT_1 1 PEC Transfer Count bit 1
PECC6.COUNT_0 0 PEC Transfer Count bit 0
PECC7 0xFECE PEC Channel 7 Control Register
PECC7.EOPINT 14 End of PEC Interrupt Selection
PECC7.PLEV_13 13 Programmable PEC Interrupt Level bit 13
PECC7.PLEV_12 12 Programmable PEC Interrupt Level bit 12
PECC7.CL 11 Channel Link Control
PECC7.INC_10 10 Increment Control bit 10
PECC7.INC_9 9 Increment Control bit 9
PECC7.BWT 8 Byte/Word Transfer Selection
PECC7.COUNT_7 7 PEC Transfer Count bit 7
PECC7.COUNT_6 6 PEC Transfer Count bit 6
PECC7.COUNT_5 5 PEC Transfer Count bit 5
PECC7.COUNT_4 4 PEC Transfer Count bit 4
PECC7.COUNT_3 3 PEC Transfer Count bit 3
PECC7.COUNT_2 2 PEC Transfer Count bit 2
PECC7.COUNT_1 1 PEC Transfer Count bit 1
PECC7.COUNT_0 0 PEC Transfer Count bit 0
P0L 0xFF00 PORT0 Low Register
P0L.P7 7
P0L.P6 6
P0L.P5 5
P0L.P4 4
P0L.P3 3
P0L.P2 2
P0L.P1 1
P0L.P0 0
P0H 0xFF02 Port 0 High Register (Upper half)
P0H.P7 7
P0H.P6 6
P0H.P5 5
P0H.P4 4
P0H.P3 3
P0H.P2 2
P0H.P1 1
P0H.P0 0
P1L 0xFF04 Port 1 Low Register
P1L.P7 7
P1L.P6 6
P1L.P5 5
P1L.P4 4
P1L.P3 3
P1L.P2 2
P1L.P1 1
P1L.P0 0
P1H 0xFF06 Port 1 High Register
P1H.P7 7
P1H.P6 6
P1H.P5 5
P1H.P4 4
P1H.P3 3
P1H.P2 2
P1H.P1 1
P1H.P0 0
IDX0 0xFF08 MAC Unit Address Pointer
IDX0.IDX_15 15 Modifiable portion of register IDX0 bit 15
IDX0.IDX_14 14 Modifiable portion of register IDX0 bit 14
IDX0.IDX_13 13 Modifiable portion of register IDX0 bit 13
IDX0.IDX_12 12 Modifiable portion of register IDX0 bit 12
IDX0.IDX_11 11 Modifiable portion of register IDX0 bit 11
IDX0.IDX_10 10 Modifiable portion of register IDX0 bit 10
IDX0.IDX_9 9 Modifiable portion of register IDX0 bit 9
IDX0.IDX_8 8 Modifiable portion of register IDX0 bit 8
IDX0.IDX_7 7 Modifiable portion of register IDX0 bit 7
IDX0.IDX_6 6 Modifiable portion of register IDX0 bit 6
IDX0.IDX_5 5 Modifiable portion of register IDX0 bit 5
IDX0.IDX_4 4 Modifiable portion of register IDX0 bit 4
IDX0.IDX_3 3 Modifiable portion of register IDX0 bit 3
IDX0.IDX_2 2 Modifiable portion of register IDX0 bit 2
IDX0.IDX_1 1 Modifiable portion of register IDX0 bit 1
IDX1 0xFF0A MAC Unit Address Pointer
IDX1.IDX_15 15 Modifiable portion of register IDX1 bit 15
IDX1.IDX_14 14 Modifiable portion of register IDX1 bit 14
IDX1.IDX_13 13 Modifiable portion of register IDX1 bit 13
IDX1.IDX_12 12 Modifiable portion of register IDX1 bit 12
IDX1.IDX_11 11 Modifiable portion of register IDX1 bit 11
IDX1.IDX_10 10 Modifiable portion of register IDX1 bit 10
IDX1.IDX_9 9 Modifiable portion of register IDX1 bit 9
IDX1.IDX_8 8 Modifiable portion of register IDX1 bit 8
IDX1.IDX_7 7 Modifiable portion of register IDX1 bit 7
IDX1.IDX_6 6 Modifiable portion of register IDX1 bit 6
IDX1.IDX_5 5 Modifiable portion of register IDX1 bit 5
IDX1.IDX_4 4 Modifiable portion of register IDX1 bit 4
IDX1.IDX_3 3 Modifiable portion of register IDX1 bit 3
IDX1.IDX_2 2 Modifiable portion of register IDX1 bit 2
IDX1.IDX_1 1 Modifiable portion of register IDX1 bit 1
SPSEG 0xFF0C Stack Pointer Segment Register
SPSEG.SPSEGNR_7 7 Stack Pointer Segment Number bit 7
SPSEG.SPSEGNR_6 6 Stack Pointer Segment Number bit 6
SPSEG.SPSEGNR_5 5 Stack Pointer Segment Number bit 5
SPSEG.SPSEGNR_4 4 Stack Pointer Segment Number bit 4
SPSEG.SPSEGNR_3 3 Stack Pointer Segment Number bit 3
SPSEG.SPSEGNR_2 2 Stack Pointer Segment Number bit 2
SPSEG.SPSEGNR_1 1 Stack Pointer Segment Number bit 1
SPSEG.SPSEGNR_0 0 Stack Pointer Segment Number bit 0
MDC 0xFF0E Multiply Divide Control Register
MDC.MDRIU 4 Multiply/Divide Register In Use
PSW 0xFF10 Processor Status Word
PSW.ILVL_15 15 CPU Priority Level bit 15
PSW.ILVL_14 14 CPU Priority Level bit 14
PSW.ILVL_13 13 CPU Priority Level bit 13
PSW.ILVL_12 12 CPU Priority Level bit 12
PSW.IEN 11 Interrupt/PEC Enable Bit (globally)
PSW.HLDEN 10 Hold Enable
PSW.BANK_9 9 Reserved for Register File Bank Selection bit 9
PSW.BANK_8 8 Reserved for Register File Bank Selection bit 8
PSW.USR1 7 General Purpose Flag
PSW.USR0 6 General Purpose Flag
PSW.MULIP 5 Multiplication/Division in progress
PSW.E 4 End of Table Flag
PSW.Z 3 Zero Flag
PSW.V 2 Overflow Flag
PSW.C 1 Carry Flag
PSW.N 0 Negative Result
VECSEG 0xFF12 Vector Segment Pointer
VECSEG.vecseg_7 7 Segment number of the Vector Table bit 7
VECSEG.vecseg_6 6 Segment number of the Vector Table bit 6
VECSEG.vecseg_5 5 Segment number of the Vector Table bit 5
VECSEG.vecseg_4 4 Segment number of the Vector Table bit 4
VECSEG.vecseg_3 3 Segment number of the Vector Table bit 3
VECSEG.vecseg_2 2 Segment number of the Vector Table bit 2
VECSEG.vecseg_1 1 Segment number of the Vector Table bit 1
VECSEG.vecseg_0 0 Segment number of the Vector Table bit 0
P9 0xFF16 Port 9 Data Register
P9.P5 5
P9.P4 4
P9.P3 3
P9.P2 2
P9.P1 1
P9.P0 0
DP9 0xFF18 Port 9 Direction Control Register
DP9.P5 5
DP9.P4 4
DP9.P3 3
DP9.P2 2
DP9.P1 1
DP9.P0 0
ODP9 0xFF1A Port 9 Open Drain Control Register
ODP9.P5 5
ODP9.P4 4
ODP9.P3 3
ODP9.P2 2
ODP9.P1 1
ODP9.P0 0
ZEROS 0xFF1C Constant Zeros Register
ONES 0xFF1E Constant Ones Register
CC2_T78CON 0xFF20 CAPCOM 2 Timer 7 and Timer 8 Control Register
CC2_T78CON.T8R 14
CC2_T78CON.T8M 11
CC2_T78CON.T7R 6
CC2_T78CON.T7M 3
CC2_M4 0xFF22 CC Mode Control Register 4
CC2_M4.ACC19 15
CC2_M4.ACC18 11
CC2_M4.ACC17 7
CC2_M4.ACC16 3
CC2_M5 0xFF24 CC Mode Control Register 5
CC2_M5.ACC23 15
CC2_M5.ACC22 11
CC2_M5.ACC21 7
CC2_M5.ACC20 3
CC2_M6 0xFF26 CC Mode Control Register 6
CC2_M6.ACC27 15
CC2_M6.ACC26 11
CC2_M6.ACC25 7
CC2_M6.ACC24 3
CC2_M7 0xFF28 CC Mode Control Register 7
CC2_M7.ACC31 15
CC2_M7.ACC30 11
CC2_M7.ACC29 7
CC2_M7.ACC28 3
CC2_DRM 0xFF2A CAPCOM 2 Double Register Mode Register
CC2_OUT 0xFF2C CAPCOM 2 Output Register
CC2_OUT.CC15IO 15
CC2_OUT.CC14IO 14
CC2_OUT.CC13IO 13
CC2_OUT.CC12IO 12
CC2_OUT.CC11IO 11
CC2_OUT.CC10IO 10
CC2_OUT.CC9IO 9
CC2_OUT.CC8IO 8
CC2_OUT.CC7IO 7
CC2_OUT.CC6IO 6
CC2_OUT.CC5IO 5
CC2_OUT.CC4IO 4
CC2_OUT.CC3IO 3
CC2_OUT.CC2IO 2
CC2_OUT.CC1IO 1
CC2_OUT.CC0IO 0
GPT12E_T2CON 0xFF40 GPT1 Timer 2 Control Register
GPT12E_T2CON.T2RDIR 15
GPT12E_T2CON.T2CHDIR 14
GPT12E_T2CON.T2EDGE 13
GPT12E_T2CON.T2IRDIS 12
GPT12E_T2CON.T2RC 9
GPT12E_T2CON.T2UDE 8
GPT12E_T2CON.T2UD 7
GPT12E_T2CON.T2R 6
GPT12E_T3CON 0xFF42 GPT1 Timer 3 Control Register
GPT12E_T3CON.T3RDIR 15
GPT12E_T3CON.T3CHDIR 14
GPT12E_T3CON.T3EDGE 13
GPT12E_T3CON.T3OTL 10
GPT12E_T3CON.T3OE 9
GPT12E_T3CON.T3UDE 8
GPT12E_T3CON.T3UD 7
GPT12E_T3CON.T3R 6
GPT12E_T4CON 0xFF44 GPT1 Timer 4 Control Register
GPT12E_T4CON.T4RDIR 15
GPT12E_T4CON.T4CHDIR 14
GPT12E_T4CON.T4EDGE 13
GPT12E_T4CON.T4IRDIS 12
GPT12E_T4CON.T4RC 9
GPT12E_T4CON.T4UDE 8
GPT12E_T4CON.T4UD 7
GPT12E_T4CON.T4R 6
GPT12E_T5CON 0xFF46 GPT2 Timer 5 Control Register
GPT12E_T5CON.T5SC 15
GPT12E_T5CON.T5CLR 14
GPT12E_T5CON.T5CC 11
GPT12E_T5CON.CT3 10
GPT12E_T5CON.T5RC 9
GPT12E_T5CON.T5UDE 8
GPT12E_T5CON.T5UD 7
GPT12E_T5CON.T5R 6
GPT12E_T6CON 0xFF48 GPT2 Timer 6 Control Register
GPT12E_T6CON.T6SR 15
GPT12E_T6CON.T6CLR 14
GPT12E_T6CON.T6OTL 10
GPT12E_T6CON.T6OE 9
GPT12E_T6CON.T6UDE 8
GPT12E_T6CON.T6UD 7
GPT12E_T6CON.T6R 6
CC1_T01CON 0xFF50 Timer 0/1 Control Register
CC1_T01CON.T1R 14
CC1_T01CON.T1M 11
CC1_T01CON.T0R 6
CC1_T01CON.T0M 3
CC1_M0 0xFF52 Capture/Compare Mode Registers for the CAPCOM Unit (CC0...CC3)
CC1_M0.ACC3 15
CC1_M0.ACC2 11
CC1_M0.ACC1 7
CC1_M0.ACC0 3
CC1_M1 0xFF54 Capture/Compare Mode Register for the CAPCOM Unit (CC4...CC79)
CC1_M1.ACC7 15
CC1_M1.ACC6 11
CC1_M1.ACC5 7
CC1_M1.ACC4 3
CC1_M2 0xFF56 Capture/Compare Mode Registers for the CAPCOM Unit (CC8...CC11)
CC1_M2.ACC11 15
CC1_M2.ACC10 11
CC1_M2.ACC9 7
CC1_M2.ACC8 3
CC1_M3 0xFF58 Capture/Compare Mode Registers for the CAPCOM Unit (CC12...CC15)
CC1_M3.ACC15 15
CC1_M3.ACC14 11
CC1_M3.ACC13 7
CC1_M3.ACC12 3
CC1_DRM 0xFF5A CAPCOM1 Double Register Mode Register
CC1_OUT 0xFF5C CAPCOM1 Output Register
CC1_OUT.CC0I15 15
CC1_OUT.CC0I14 14
CC1_OUT.CC0I13 13
CC1_OUT.CC0I12 12
CC1_OUT.CC0I11 11
CC1_OUT.CC0I10 10
CC1_OUT.CC0I9 9
CC1_OUT.CC0I8 8
CC1_OUT.CC0I7 7
CC1_OUT.CC0I6 6
CC1_OUT.CC0I5 5
CC1_OUT.CC0I4 4
CC1_OUT.CC0I3 3
CC1_OUT.CC0I2 2
CC1_OUT.CC0I1 1
CC1_OUT.CC0I0 0
SSC1_CON 0xFF5E SSC1 Control Register
SSC1_CON.EN 15
SSC1_CON.MS 14
SSC1_CON.AREN 12
SSC1_CON.BEN 11
SSC1_CON.PEN 10
SSC1_CON.REN 9
SSC1_CON.TEN 8
SSC1_CON.LB 7
SSC1_CON.PO 6
SSC1_CON.PH 5
SSC1_CON.HB 4
GPT12E_T2IC 0xFF60 GPT1 Timer 2 Interrupt Control Register
GPT12E_T2IC.GPX 8 Group Priority Extension
GPT12E_T2IC.IR 7 Interrupt Request Flag
GPT12E_T2IC.IE 6 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T2IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T2IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T2IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T3IC 0xFF62 GPT1 Timer 3 Interrupt Control Register
GPT12E_T3IC.GPX 8 Group Priority Extension
GPT12E_T3IC.IR 7 Interrupt Request Flag
GPT12E_T3IC.IE 6 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T3IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T3IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T3IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T4IC 0xFF64 GPT1 Timer 4 Interrupt Control Register
GPT12E_T4IC.GPX 8 Group Priority Extension
GPT12E_T4IC.IR 7 Interrupt Request Flag
GPT12E_T4IC.IE 6 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T4IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T4IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T4IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T5IC 0xFF66 GPT2 Timer 5 Interrupt Control Register
GPT12E_T5IC.GPX 8 Group Priority Extension
GPT12E_T5IC.IR 7 Interrupt Request Flag
GPT12E_T5IC.IE 6 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T5IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T5IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T5IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_T6IC 0xFF68 GPT2 Timer 6 Interrupt Control Register
GPT12E_T6IC.GPX 8 Group Priority Extension
GPT12E_T6IC.IR 7 Interrupt Request Flag
GPT12E_T6IC.IE 6 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_T6IC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_T6IC.GLVL_1 1 Group Priority Level bit 1
GPT12E_T6IC.GLVL_0 0 Group Priority Level bit 0
GPT12E_CRIC 0xFF6A GPT2 CAPREL Interrupt Control Register
GPT12E_CRIC.GPX 8 Group Priority Extension
GPT12E_CRIC.IR 7 Interrupt Request Flag
GPT12E_CRIC.IE 6 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_5 5 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_4 4 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_3 3 Interrupt Enable Control Bit
GPT12E_CRIC.ILVL_2 2 Interrupt Enable Control Bit
GPT12E_CRIC.GLVL_1 1 Group Priority Level bit 1
GPT12E_CRIC.GLVL_0 0 Group Priority Level bit 0
ASC0_TIC 0xFF6C ASC0 Transmit Interrupt Control Register
ASC0_TIC.GPX 8 Group Priority Extension
ASC0_TIC.IR 7 Interrupt Request Flag
ASC0_TIC.IE 6 Interrupt Enable Control Bit
ASC0_TIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_TIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_TIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_TIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_TIC.GLVL_1 1 Group Priority Level bit 1
ASC0_TIC.GLVL_0 0 Group Priority Level bit 0
ASC0_RIC 0xFF6E ASC0 Receive Interrupt Control Register
ASC0_RIC.GPX 8 Group Priority Extension
ASC0_RIC.IR 7 Interrupt Request Flag
ASC0_RIC.IE 6 Interrupt Enable Control Bit
ASC0_RIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_RIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_RIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_RIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_RIC.GLVL_1 1 Group Priority Level bit 1
ASC0_RIC.GLVL_0 0 Group Priority Level bit 0
ASC0_EIC 0xFF70 ASC0 Error Interrupt Control Register
ASC0_EIC.GPX 8 Group Priority Extension
ASC0_EIC.IR 7 Interrupt Request Flag
ASC0_EIC.IE 6 Interrupt Enable Control Bit
ASC0_EIC.ILVL_5 5 Interrupt Enable Control Bit
ASC0_EIC.ILVL_4 4 Interrupt Enable Control Bit
ASC0_EIC.ILVL_3 3 Interrupt Enable Control Bit
ASC0_EIC.ILVL_2 2 Interrupt Enable Control Bit
ASC0_EIC.GLVL_1 1 Group Priority Level bit 1
ASC0_EIC.GLVL_0 0 Group Priority Level bit 0
SSC0_TIC 0xFF72 SSC0 Transmit Interrupt Control Register
SSC0_TIC.GPX 8 Group Priority Extension
SSC0_TIC.IR 7 Interrupt Request Flag
SSC0_TIC.IE 6 Interrupt Enable Control Bit
SSC0_TIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_TIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_TIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_TIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_TIC.GLVL_1 1 Group Priority Level bit 1
SSC0_TIC.GLVL_0 0 Group Priority Level bit 0
SSC0_RIC 0xFF74 SSC0 Receive Interrupt Control Register
SSC0_RIC.GPX 8 Group Priority Extension
SSC0_RIC.IR 7 Interrupt Request Flag
SSC0_RIC.IE 6 Interrupt Enable Control Bit
SSC0_RIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_RIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_RIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_RIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_RIC.GLVL_1 1 Group Priority Level bit 1
SSC0_RIC.GLVL_0 0 Group Priority Level bit 0
SSC0_EIC 0xFF76 SSC0 Error Interrupt Control Register
SSC0_EIC.GPX 8 Group Priority Extension
SSC0_EIC.IR 7 Interrupt Request Flag
SSC0_EIC.IE 6 Interrupt Enable Control Bit
SSC0_EIC.ILVL_5 5 Interrupt Enable Control Bit
SSC0_EIC.ILVL_4 4 Interrupt Enable Control Bit
SSC0_EIC.ILVL_3 3 Interrupt Enable Control Bit
SSC0_EIC.ILVL_2 2 Interrupt Enable Control Bit
SSC0_EIC.GLVL_1 1 Group Priority Level bit 1
SSC0_EIC.GLVL_0 0 Group Priority Level bit 0
CC1_CC0IC 0xFF78 CAPCOM Channel 0 Interrupt Control Register
CC1_CC0IC.GPX 8 Group Priority Extension
CC1_CC0IC.IR 7 Interrupt Request Flag
CC1_CC0IC.IE 6 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC0IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC0IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC0IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC1IC 0xFF7A CAPCOM Channel 1 Interrupt Control Register
CC1_CC1IC.GPX 8 Group Priority Extension
CC1_CC1IC.IR 7 Interrupt Request Flag
CC1_CC1IC.IE 6 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC1IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC1IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC1IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC2IC 0xFF7C CAPCOM Channel 2 Interrupt Control Register
CC1_CC2IC.GPX 8 Group Priority Extension
CC1_CC2IC.IR 7 Interrupt Request Flag
CC1_CC2IC.IE 6 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC2IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC2IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC2IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC3IC 0xFF7E CAPCOM Channel 3 Interrupt Control Register
CC1_CC3IC.GPX 8 Group Priority Extension
CC1_CC3IC.IR 7 Interrupt Request Flag
CC1_CC3IC.IE 6 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC3IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC3IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC3IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC4IC 0xFF80 CAPCOM Channel 4 Interrupt Control Register
CC1_CC4IC.GPX 8 Group Priority Extension
CC1_CC4IC.IR 7 Interrupt Request Flag
CC1_CC4IC.IE 6 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC4IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC4IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC4IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC5IC 0xFF82 CAPCOM Channel 5 Interrupt Control Register
CC1_CC5IC.GPX 8 Group Priority Extension
CC1_CC5IC.IR 7 Interrupt Request Flag
CC1_CC5IC.IE 6 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC5IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC5IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC5IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC6IC 0xFF84 CAPCOM Channel 6 Interrupt Control Register
CC1_CC6IC.GPX 8 Group Priority Extension
CC1_CC6IC.IR 7 Interrupt Request Flag
CC1_CC6IC.IE 6 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC6IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC6IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC6IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC7IC 0xFF86 CC Register 7 Interrupt Control Register
CC1_CC7IC.GPX 8 Group Priority Extension
CC1_CC7IC.IR 7 Interrupt Request Flag
CC1_CC7IC.IE 6 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC7IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC7IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC7IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC8IC 0xFF88 CC Register 8 Interrupt Control Register
CC1_CC8IC.GPX 8 Group Priority Extension
CC1_CC8IC.IR 7 Interrupt Request Flag
CC1_CC8IC.IE 6 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC8IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC8IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC8IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC9IC 0xFF8A CC Register 9 Interrupt Control Register
CC1_CC9IC.GPX 8 Group Priority Extension
CC1_CC9IC.IR 7 Interrupt Request Flag
CC1_CC9IC.IE 6 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC9IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC9IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC9IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC10IC 0xFF8C CAPCOM Channel 10 Interrupt Control Register
CC1_CC10IC.GPX 8 Group Priority Extension
CC1_CC10IC.IR 7 Interrupt Request Flag
CC1_CC10IC.IE 6 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC10IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC10IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC10IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC11IC 0xFF8E CAPCOM Channel 11 Interrupt Control Register
CC1_CC11IC.GPX 8 Group Priority Extension
CC1_CC11IC.IR 7 Interrupt Request Flag
CC1_CC11IC.IE 6 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC11IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC11IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC11IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC12IC 0xFF90 CAPCOM Channel 12 Interrupt Control Register
CC1_CC12IC.GPX 8 Group Priority Extension
CC1_CC12IC.IR 7 Interrupt Request Flag
CC1_CC12IC.IE 6 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC12IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC12IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC12IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC13IC 0xFF92 CAPCOM Channel 13 Interrupt Control Register
CC1_CC13IC.GPX 8 Group Priority Extension
CC1_CC13IC.IR 7 Interrupt Request Flag
CC1_CC13IC.IE 6 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC13IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC13IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC13IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC14IC 0xFF94 CAPCOM Channel 14 Interrupt Control Register
CC1_CC14IC.GPX 8 Group Priority Extension
CC1_CC14IC.IR 7 Interrupt Request Flag
CC1_CC14IC.IE 6 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC14IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC14IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC14IC.GLVL_0 0 Group Priority Level bit 0
CC1_CC15IC 0xFF96 CAPCOM Channel 15 Interrupt Control Register
CC1_CC15IC.GPX 8 Group Priority Extension
CC1_CC15IC.IR 7 Interrupt Request Flag
CC1_CC15IC.IE 6 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_CC15IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_CC15IC.GLVL_1 1 Group Priority Level bit 1
CC1_CC15IC.GLVL_0 0 Group Priority Level bit 0
ADC_CIC 0xFF98 ADC End of Conversion Interrupt Control Register
ADC_CIC.GPX 8 Group Priority Extension
ADC_CIC.IR 7 Interrupt Request Flag
ADC_CIC.IE 6 Interrupt Enable Control Bit
ADC_CIC.ILVL_5 5 Interrupt Enable Control Bit
ADC_CIC.ILVL_4 4 Interrupt Enable Control Bit
ADC_CIC.ILVL_3 3 Interrupt Enable Control Bit
ADC_CIC.ILVL_2 2 Interrupt Enable Control Bit
ADC_CIC.GLVL_1 1 Group Priority Level bit 1
ADC_CIC.GLVL_0 0 Group Priority Level bit 0
ADC_EIC 0xFF9A ADC Overrun Error Control Register
ADC_EIC.GPX 8
ADC_EIC.IR 7
ADC_EIC.IE 6
CC1_T0IC 0xFF9C CAPCOM 1 Timer 0 Interrupt Control Register
CC1_T0IC.GPX 8 Group Priority Extension
CC1_T0IC.IR 7 Interrupt Request Flag
CC1_T0IC.IE 6 Interrupt Enable Control Bit
CC1_T0IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_T0IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_T0IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_T0IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_T0IC.GLVL_1 1 Group Priority Level bit 1
CC1_T0IC.GLVL_0 0 Group Priority Level bit 0
CC1_T1IC 0xFF9E CC Timer 1 Interrupt Control Register
CC1_T1IC.GPX 8 Group Priority Extension
CC1_T1IC.IR 7 Interrupt Request Flag
CC1_T1IC.IE 6 Interrupt Enable Control Bit
CC1_T1IC.ILVL_5 5 Interrupt Enable Control Bit
CC1_T1IC.ILVL_4 4 Interrupt Enable Control Bit
CC1_T1IC.ILVL_3 3 Interrupt Enable Control Bit
CC1_T1IC.ILVL_2 2 Interrupt Enable Control Bit
CC1_T1IC.GLVL_1 1 Group Priority Level bit 1
CC1_T1IC.GLVL_0 0 Group Priority Level bit 0
ADC_CON 0xFFA0 A/D Converter Control Register
P5 0xFFA2 Port 5 Data Register
P5.P15 15
P5.P14 14
P5.P13 13
P5.P12 12
P5.P11 11
P5.P10 10
P5.P7 7
P5.P6 6
P5.P5 5
P5.P4 4
P5.P3 3
P5.P2 2
P5.P1 1
P5.P0 0
P5DIDIS 0xFFA4 Port 5 Digital Input Disable
P5DIDIS.P15 15
P5DIDIS.P14 14
P5DIDIS.P13 13
P5DIDIS.P12 12
P5DIDIS.P11 11
P5DIDIS.P10 10
P5DIDIS.P7 7
P5DIDIS.P6 6
P5DIDIS.P5 5
P5DIDIS.P4 4
P5DIDIS.P3 3
P5DIDIS.P2 2
P5DIDIS.P1 1
P5DIDIS.P0 0
ADC_CON1 0xFFA6 A/D Converter Control Register 1
PECISNC 0xFFA8 PEC Interrupt Subnode Control Register
PECISNC.C7IR 15 Interrupt Sub Node Request Flag of PEC Channel 7
PECISNC.C7IE 14 Interrupt Sub Node Enable Control Bit of PEC Channel 7
PECISNC.C6IR 13 Interrupt Sub Node Request Flag of PEC Channel 6
PECISNC.C6IE 12 Interrupt Sub Node Enable Control Bit of PEC Channel 6
PECISNC.C5IR 11 Interrupt Sub Node Request Flag of PEC Channel 5
PECISNC.C5IE 10 Interrupt Sub Node Enable Control Bit of PEC Channel 5
PECISNC.C4IR 9 Interrupt Sub Node Request Flag of PEC Channel 4
PECISNC.C4IE 8 Interrupt Sub Node Enable Control Bit of PEC Channel 4
PECISNC.C3IR 7 Interrupt Sub Node Request Flag of PEC Channel 3
PECISNC.C3IE 6 Interrupt Sub Node Enable Control Bit of PEC Channel 3
PECISNC.C2IR 5 Interrupt Sub Node Request Flag of PEC Channel 2
PECISNC.C2IE 4 Interrupt Sub Node Enable Control Bit of PEC Channel 2
PECISNC.C1IR 3 Interrupt Sub Node Request Flag of PEC Channel 1
PECISNC.C1IE 2 Interrupt Sub Node Enable Control Bit of PEC Channel 1
PECISNC.C0IR 1 Interrupt Sub Node Request Flag of PEC Channel 0
PECISNC.C0IE 0 Interrupt Sub Node Enable Control Bit of PEC Channel 0
FOCON 0xFFAA Frequency Output Control Register
FOCON.FOEN 15 Frequency Output Enable
FOCON.FOSS 14 Frequency Output Signal Select
FOCON.FORV_13 13 Frequency Output Reload Value bit 13
FOCON.FORV_12 12 Frequency Output Reload Value bit 12
FOCON.FORV_11 11 Frequency Output Reload Value bit 11
FOCON.FORV_10 10 Frequency Output Reload Value bit 10
FOCON.FORV_9 9 Frequency Output Reload Value bit 9
FOCON.FORV_8 8 Frequency Output Reload Value bit 8
FOCON.CLKEN 7 CLKOUT Enable
FOCON.FOTL 6 Frequency Output Toggle Latch
FOCON.FOCNT_5 5 Frequency Output Counter bit 5
FOCON.FOCNT_4 4 Frequency Output Counter bit 4
FOCON.FOCNT_3 3 Frequency Output Counter bit 3
FOCON.FOCNT_2 2 Frequency Output Counter bit 2
FOCON.FOCNT_1 1 Frequency Output Counter bit 1
FOCON.FOCNT_0 0 Frequency Output Counter bit 0
TFR 0xFFAC Trap Flag Register
TFR.NMI 15 Non maskable interrupt flag
TFR.STKOF 14 Stack overflow flag
TFR.STKUF 13 Stack underflow flag
TFR.SOFTBRK 12 Software Break
TFR.UNDOPC 7 Undefined Opcode
TFR.PACER 4 Program Memory Interface Access Error
TFR.PRTFLT 3 Protection Fault
TFR.ILLOPA 2 Illegal word operand access
WDTCON 0xFFAE Watchdog Timer Control Register
WDTCON.WDTREL_15 15 Watchdog Timer Reload Value bit 15
WDTCON.WDTREL_14 14 Watchdog Timer Reload Value bit 14
WDTCON.WDTREL_13 13 Watchdog Timer Reload Value bit 13
WDTCON.WDTREL_12 12 Watchdog Timer Reload Value bit 12
WDTCON.WDTREL_11 11 Watchdog Timer Reload Value bit 11
WDTCON.WDTREL_10 10 Watchdog Timer Reload Value bit 10
WDTCON.WDTREL_9 9 Watchdog Timer Reload Value bit 9
WDTCON.WDTREL_8 8 Watchdog Timer Reload Value bit 8
WDTCON.WDTIN_1 1 Watchdog Timer Input Frequency Select bit 1
WDTCON.WDTIN_0 0 Watchdog Timer Input Frequency Select bit 0
ASC0_CON 0xFFB0 Serial Channel 0 Control Register
SSC0_CON 0xFFB2 SSC Control Register
SSC0_CON.EN 15
SSC0_CON.MS 14
SSC0_CON.AREN 12
SSC0_CON.BEN 11
SSC0_CON.PEN 10
SSC0_CON.REN 9
SSC0_CON.TEN 8
SSC0_CON.LB 7
SSC0_CON.PO 6
SSC0_CON.PH 5
SSC0_CON.HB 4
P20 0xFFB4 Port 20 Data Register
P20.P12 12
P20.P5 5
P20.P4 4
P20.P1 1
P20.P0 0
DP20 0xFFB6 Port 20 Direction Control Register
DP20.P12 12
DP20.P5 5
DP20.P4 4
DP20.P1 1
DP20.P0 0
ASC1_CON 0xFFB8 DCH Serial Channel 1 Control Register
ASC1_CON.R 15
ASC1_CON.LB 14
ASC1_CON.BRS 13
ASC1_CON.ODD 12
ASC1_CON.S0FDE 11
ASC1_CON.OE 10
ASC1_CON.FE 9
ASC1_CON.PE 8
ASC1_CON.OEN 7
ASC1_CON.FEN 6
ASC1_CON.PEN 5
ASC1_CON.REN 4
ASC1_CON.STP 3
ADC_CTR0 0xFFBE DFH A/D Converter Control Register 0
P2 0xFFC0 Port 2 Data Register
P2.P15 15
P2.P14 14
P2.P13 13
P2.P12 12
P2.P11 11
P2.P10 10
P2.P9 9
P2.P8 8
DP2 0xFFC2 Port 2 Direction Control Register
DP2.P15 15
DP2.P14 14
DP2.P13 13
DP2.P12 12
DP2.P11 11
DP2.P10 10
DP2.P9 9
DP2.P8 8
P3 0xFFC4 E2H Port 3 Data Register
P3.P15 15
P3.P13 13
P3.P12 12
P3.P11 11
P3.P10 10
P3.P9 9
P3.P8 8
P3.P7 7
P3.P6 6
P3.P5 5
P3.P4 4
P3.P3 3
P3.P2 2
P3.P1 1
P3.P0 0
DP3 0xFFC6 E3H Port 3 Direction Control Register
DP3.P15 15
DP3.P13 13
DP3.P12 12
DP3.P11 11
DP3.P10 10
DP3.P9 9
DP3.P8 8
DP3.P7 7
DP3.P6 6
DP3.P5 5
DP3.P4 4
DP3.P3 3
DP3.P2 2
DP3.P1 1
DP3.P0 0
P4 0xFFC8 E4H Port 4 Data Register
P4.P7 7
P4.P6 6
P4.P5 5
P4.P4 4
P4.P3 3
P4.P2 2
P4.P1 1
P4.P0 0
DP4 0xFFCA E5H Port 4 Direction Control Register
DP4.P7 7
DP4.P6 6
DP4.P5 5
DP4.P4 4
DP4.P3 3
DP4.P2 2
DP4.P1 1
DP4.P0 0
P6 0xFFCC Port 6 Data Register
P6.P7 7
P6.P6 6
P6.P5 5
P6.P4 4
P6.P3 3
P6.P2 2
P6.P1 1
P6.P0 0
DP6 0xFFCE Port 6 Direction Control Register
DP6.P7 7
DP6.P6 6
DP6.P5 5
DP6.P4 4
DP6.P3 3
DP6.P2 2
DP6.P1 1
DP6.P0 0
P7 0xFFD0 Port 7 Data Register
P7.P7 7
P7.P6 6
P7.P5 5
P7.P4 4
DP7 0xFFD2 Port 7 Direction Control Register
DP7.P7 7
DP7.P6 6
DP7.P5 5
DP7.P4 4
MRW 0xFFDA EDH MAC Repeat Word
MRW.REPEAT_COUNT_15 15 16-bit loop counter bit 15
MRW.REPEAT_COUNT_14 14 16-bit loop counter bit 14
MRW.REPEAT_COUNT_13 13 16-bit loop counter bit 13
MRW.REPEAT_COUNT_12 12 16-bit loop counter bit 12
MRW.REPEAT_COUNT_11 11 16-bit loop counter bit 11
MRW.REPEAT_COUNT_10 10 16-bit loop counter bit 10
MRW.REPEAT_COUNT_9 9 16-bit loop counter bit 9
MRW.REPEAT_COUNT_8 8 16-bit loop counter bit 8
MRW.REPEAT_COUNT_7 7 16-bit loop counter bit 7
MRW.REPEAT_COUNT_6 6 16-bit loop counter bit 6
MRW.REPEAT_COUNT_5 5 16-bit loop counter bit 5
MRW.REPEAT_COUNT_4 4 16-bit loop counter bit 4
MRW.REPEAT_COUNT_3 3 16-bit loop counter bit 3
MRW.REPEAT_COUNT_2 2 16-bit loop counter bit 2
MRW.REPEAT_COUNT_1 1 16-bit loop counter bit 1
MRW.REPEAT_COUNT_0 0 16-bit loop counter bit 0
MCW 0xFFDC EEH MAC Control Word
MCW.MP 10 One-bit scaler control
MCW.MS 9 Saturation control
MSW 0xFFDE EFH MAC Unit Status Word
MSW.MV 14 Overflow Flag
MSW.MSL 13 Sticky Limit Flag
MSW.ME 12 MAC Extension Flag
MSW.ME 11 Sticky Overflow Flag
MSW.MC 10 Carry Flag
MSW.MZ 9 Zero Flag
MSW.MN 8 Negative Result
MSW.MAE_7 7 The most significant bits of the 40-bit Accumulator bit 7
MSW.MAE_6 6 The most significant bits of the 40-bit Accumulator bit 6
MSW.MAE_5 5 The most significant bits of the 40-bit Accumulator bit 5
MSW.MAE_4 4 The most significant bits of the 40-bit Accumulator bit 4
MSW.MAE_3 3 The most significant bits of the 40-bit Accumulator bit 3
MSW.MAE_2 2 The most significant bits of the 40-bit Accumulator bit 2
MSW.MAE_1 1 The most significant bits of the 40-bit Accumulator bit 1
MSW.MAE_0 0 The most significant bits of the 40-bit Accumulator bit 0
ASC0_ID 0xFFE2 ASC0 Identification Register
SSC0_ID 0xFFE4 SSC0 Module Identification Register
GPT12E_ID 0xFFE6 GPT Identification Register
CC1_ID 0xFFEC CAPCOM1 Module Identification Register
CC2_ID 0xFFEE CAPCOM2 Module Identification Register
SSC1_ID 0xFFF6 Module Identification Register
RTC_IDH 0xFFFA RTC Identification Register High
; TWINCAN-16BIT
CAN_PISEL 0x200004 TwinCAN Port Input Select Register
CAN_ID 0x200008 CAN Module Identification Register
CAN_ACR 0x200200 Node A Control Register
CAN_ASR 0x200204 Node A Status Register
CAN_AIR 0x200208 Node A Interrupt Pending Register
CAN_ABTRL 0x20020C Node A Bit Timing Register Low
CAN_ABTRH 0x20020E Node A Bit Timing Register High
CAN_AGINP 0x200210 Node A Global Interrupt Node Pointer Register
CAN_AFCRL 0x200214 Node A Frame Counter Register Low
CAN_AFCRH 0x200216 Node A Frame Counter Register High
CAN_AIMRL0 0x200218 Node A INTID Mask Register 0 Low
CAN_AIMRH0 0x20021A Node A INTID Mask Register 0 High
CAN_AIMR4 0x20021C Node A INTID Mask Register 4 Low
CAN_AECNTL 0x200220 Node A Error Counter Register Low
CAN_AECNTH 0x200222 Node A Error Counter Register High
CAN_BCR 0x200240 Node B Control Register
CAN_BSR 0x200244 Node B Status Register
CAN_BIR 0x200248 Node B Interrupt Pending Register
CAN_BBTRL 0x20024C Node B Bit Timing Register Low
CAN_BBTRH 0x20024E Node B Bit Timing Register High
CAN_BGINP 0x200250 Node B Global Interrupt Node Pointer Register
CAN_BFCRL 0x200254 Node B Frame Counter Register Low
CAN_BFCRH 0x200256 Node B Frame Counter Register High
CAN_BIMRL0 0x200258 Node B INTID Mask Register 0 Low
CAN_BIMRH0 0x20025A Node B INTID Mask Register 0 High
CAN_BIMR4 0x20025C Node B INTID Mask Register 4 Low
CAN_BECNTL 0x200260 Node B Error Counter Register Low
CAN_BECNTH 0x200262 Node B Error Counter Register High
CAN_RXIPNDL 0x200284 Receive Interrupt Pending Register Low
CAN_RXIPNDH 0x200286 Receive Interrupt Pending Register High
CAN_TXIPNDL 0x200288 Transmit Interrupt Pending Register Low
CAN_TXIPNDH 0x20028A Transmit Interrupt Pending Register High
CAN_MSGDRL00 0x200300 Message Object 0 Data Register 0 Low
CAN_MSGDRH00 0x200302 Message Object 0 Data Register 0 High
CAN_MSGDRL04 0x200304 Message Object 0 Data Register 4 Low
CAN_MSGDRH04 0x200306 Message Object 0 Data Register 4 High
CAN_MSGARL0 0x200308 Message Object 0 Arbitration Register Low
CAN_MSGARH0 0x20030A Message Object 0 Arbitration Register High
CAN_MSGAMRL0 0x20030C Message Object 0 Arbitration Mask Register Low
CAN_MSGAMRH0 0x20030E Message Object 0 Arbitration Mask Register High
CAN_MSGCTRL0 0x200310 Message Object 0 Message Control Register Low
CAN_MSGCTRH0 0x200312 Message Object 0 Message Control Register High
CAN_MSGCFGL0 0x200314 Message Object 0 Message Configuration Register Low
CAN_MSGCFGH0 0x200316 Message Object 0 Message Configuration Register High
CAN_MSGFGCRL0 0x200318 Message Object 0 FIFO/Gateway Control Register Low
CAN_MSGFGCRH0 0x20031A Message Object 0 FIFO/Gateway Control Register High
CAN_MSGDRL10 0x200320 Message Object 1 Data Register 0 Low
CAN_MSGDRH10 0x200322 Message Object 1 Data Register 0 High
CAN_MSGDRL14 0x200324 Message Object 1 Data Register 4 Low
CAN_MSGDRH14 0x200326 Message Object 1 Data Register 4 High
CAN_MSGARL1 0x200328 Message Object 1 Arbitration Register Low
CAN_MSGARH1 0x20032A Message Object 1 Arbitration Register High
CAN_MSGAMRL1 0x20032C Message Object 1 Arbitration Mask Register Low
CAN_MSGAMRH1 0x20032E Message Object 1 Arbitration Mask Register High
CAN_MSGCTRL1 0x200330 Message Object 1 Message Control Register Low
CAN_MSGCTRH1 0x200332 Message Object 1 Message Control Register High
CAN_MSGCFGL1 0x200334 Message Object 1 Message Configuration Register Low
CAN_MSGCFGH1 0x200336 Message Object 1 Message Configuration Register High
CAN_MSGFGCRL1 0x200338 Message Object 1 FIFO/Gateway Control Register Low
CAN_MSGFGCRH1 0x20033A Message Object 1 FIFO/Gateway Control Register High
CAN_MSGDRL20 0x200340 Message Object 2 Data Register 0 Low
CAN_MSGDRH20 0x200342 Message Object 2 Data Register 0 High
CAN_MSGDRL24 0x200344 Message Object 2 Data Register 4 Low
CAN_MSGDRH24 0x200346 Message Object 2 Data Register 4 High
CAN_MSGARL2 0x200348 Message Object 2 Arbitration Register Low
CAN_MSGARH2 0x20034A Message Object 2 Arbitration Register High
CAN_MSGAMRL2 0x20034C Message Object 2 Arbitration Mask Register Low
CAN_MSGAMRH2 0x20034E Message Object 2 Arbitration Mask Register High
CAN_MSGCTRL2 0x200350 Message Object 2 Message Control Register Low
CAN_MSGCTRH2 0x200352 Message Object 2 Message Control Register High
CAN_MSGCFGL2 0x200354 Message Object 2 Message Configuration Register Low
CAN_MSGCFGH2 0x200356 Message Object 2 Message Configuration Register High
CAN_MSGFGCRL2 0x200358 Message Object 2 FIFO/Gateway Control Register Low
CAN_MSGFGCRH2 0x20035A Message Object 2 FIFO/Gateway Control Register High
CAN_MSGDRL30 0x200360 Message Object 3 Data Register 0 Low
CAN_MSGDRH30 0x200362 Message Object 3 Data Register 0 High
CAN_MSGDRL34 0x200364 Message Object 3 Data Register 4 Low
CAN_MSGDRH34 0x200366 Message Object 3 Data Register 4 High
CAN_MSGARL3 0x200368 Message Object 3 Arbitration Register Low
CAN_MSGARH3 0x20036A Message Object 3 Arbitration Register High
CAN_MSGAMRL3 0x20036C Message Object 3 Arbitration Mask Register Low
CAN_MSGAMRH3 0x20036E Message Object 3 Arbitration Mask Register High
CAN_MSGCTRL3 0x200370 Message Object 3 Message Control Register Low
CAN_MSGCTRH3 0x200372 Message Object 3 Message Control Register High
CAN_MSGCFGL3 0x200374 Message Object 3 Message Configuration Register Low
CAN_MSGCFGH3 0x200376 Message Object 3 Message Configuration Register High
CAN_MSGFGCRL3 0x200378 Message Object 3 FIFO/Gateway Control Register Low
CAN_MSGFGCRH3 0x20037A Message Object 3 FIFO/Gateway Control Register High
CAN_MSGDRL40 0x200380 Message Object 4 Data Register 0 Low
CAN_MSGDRH40 0x200382 Message Object 4 Data Register 0 High
CAN_MSGDRL44 0x200384 Message Object 4 Data Register 4 Low
CAN_MSGDRH44 0x200386 Message Object 4 Data Register 4 High
CAN_MSGARL4 0x200388 Message Object 4 Arbitration Register Low
CAN_MSGARH4 0x20038A Message Object 4 Arbitration Register High
CAN_MSGAMRL4 0x20038C Message Object 4 Arbitration Mask Register Low
CAN_MSGAMRH4 0x20038E Message Object 4 Arbitration Mask Register High
CAN_MSGCTRL4 0x200390 Message Object 4 Message Control Register Low
CAN_MSGCTRH4 0x200392 Message Object 4 Message Control Register High
CAN_MSGCFGL4 0x200394 Message Object 4 Message Configuration Register Low
CAN_MSGCFGH4 0x200396 Message Object 4 Message Configuration Register High
CAN_MSGFGCRL4 0x200398 Message Object 4 FIFO/Gateway Control Register Low
CAN_MSGFGCRH4 0x20039A Message Object 4 FIFO/Gateway Control Register High
CAN_MSGDRL50 0x2003A0 Message Object 5 Data Register 0 Low
CAN_MSGDRH50 0x2003A2 Message Object 5 Data Register 0 High
CAN_MSGDRL54 0x2003A4 Message Object 5 Data Register 4 Low
CAN_MSGDRH54 0x2003A6 Message Object 5 Data Register 4 High
CAN_MSGARL5 0x2003A8 Message Object 5 Arbitration Register Low
CAN_MSGARH5 0x2003AA Message Object 5 Arbitration Register High
CAN_MSGAMRL5 0x2003AC Message Object 5 Arbitration Mask Register Low
CAN_MSGAMRH5 0x2003AE Message Object 5 Arbitration Mask Register High
CAN_MSGCTRL5 0x2003B0 Message Object 5 Message Control Register Low
CAN_MSGCTRH5 0x2003B2 Message Object 5 Message Control Register High
CAN_MSGCFGL5 0x2003B4 Message Object 5 Message Configuration Register Low
CAN_MSGCFGH5 0x2003B6 Message Object 5 Message Configuration Register High
CAN_MSGFGCRL5 0x2003B8 Message Object 5 FIFO/Gateway Control Register Low
CAN_MSGFGCRH5 0x2003BA Message Object 5 FIFO/Gateway Control Register High
CAN_MSGDRL60 0x2003C0 Message Object 6 Data Register 0 Low
CAN_MSGDRH60 0x2003C2 Message Object 6 Data Register 0 High
CAN_MSGDRL64 0x2003C4 Message Object 6 Data Register 4 Low
CAN_MSGDRH64 0x2003C6 Message Object 6 Data Register 4 High
CAN_MSGARL6 0x2003C8 Message Object 6 Arbitration Register Low
CAN_MSGARH6 0x2003CA Message Object 6 Arbitration Register High
CAN_MSGAMRL6 0x2003CC Message Object 6 Arbitration Mask Register Low
CAN_MSGAMRH6 0x2003CE Message Object 6 Arbitration Mask Register High
CAN_MSGCTRL6 0x2003D0 Message Object 6 Message Control Register Low
CAN_MSGCTRH6 0x2003D2 Message Object 6 Message Control Register High
CAN_MSGCFGL6 0x2003D4 Message Object 6 Message Configuration Register Low
CAN_MSGCFGH6 0x2003D6 Message Object 6 Message Configuration Register High
CAN_MSGFGCRL6 0x2003D8 Message Object 6 FIFO/Gateway Control Register Low
CAN_MSGFGCRH6 0x2003DA Message Object 6 FIFO/Gateway Control Register High
CAN_MSGDRL70 0x2003E0 Message Object 7 Data Register 0 Low
CAN_MSGDRH70 0x2003E2 Message Object 7 Data Register 0 High
CAN_MSGDRL74 0x2003E4 Message Object 7 Data Register 4 Low
CAN_MSGDRH74 0x2003E6 Message Object 7 Data Register 4 High
CAN_MSGARL7 0x2003E8 Message Object 7 Arbitration Register Low
CAN_MSGARH7 0x2003EA Message Object 7 Arbitration Register High
CAN_MSGAMRL7 0x2003EC Message Object 7 Arbitration Mask Register Low
CAN_MSGAMRH7 0x2003EE Message Object 7 Arbitration Mask Register High
CAN_MSGCTRL7 0x2003F0 Message Object 7 Message Control Register Low
CAN_MSGCTRH7 0x2003F2 Message Object 7 Message Control Register High
CAN_MSGCFGL7 0x2003F4 Message Object 7 Message Configuration Register Low
CAN_MSGCFGH7 0x2003F6 Message Object 7 Message Configuration Register High
CAN_MSGFGCRL7 0x2003F8 Message Object 7 FIFO/Gateway Control Register Low
CAN_MSGFGCRH7 0x2003FA Message Object 7 FIFO/Gateway Control Register High
CAN_MSGDRL80 0x200400 Message Object 8 Data Register 0 Low
CAN_MSGDRH80 0x200402 Message Object 8 Data Register 0 High
CAN_MSGDRL84 0x200404 Message Object 8 Data Register 4 Low
CAN_MSGDRH84 0x200406 Message Object 8 Data Register 4 High
CAN_MSGARL8 0x200408 Message Object 8 Arbitration Register Low
CAN_MSGARH8 0x20040A Message Object 8 Arbitration Register High
CAN_MSGAMRL8 0x20040C Message Object 8 Arbitration Mask Register Low
CAN_MSGAMRH8 0x20040E Message Object 8 Arbitration Mask Register High
CAN_MSGCTRL8 0x200410 Message Object 8 Message Control Register Low
CAN_MSGCTRH8 0x200412 Message Object 8 Message Control Register High
CAN_MSGCFGL8 0x200414 Message Object 8 Message Configuration Register Low
CAN_MSGCFGH8 0x200416 Message Object 8 Message Configuration Register High
CAN_MSGFGCRL8 0x200418 Message Object 8 FIFO/Gateway Control Register Low
CAN_MSGFGCRH8 0x20041A Message Object 8 FIFO/Gateway Control Register High
CAN_MSGDRL90 0x200420 Message Object 9 Data Register 0 Low
CAN_MSGDRH90 0x200422 Message Object 9 Data Register 0 High
CAN_MSGDRL94 0x200424 Message Object 9 Data Register 4 Low
CAN_MSGDRH94 0x200426 Message Object 9 Data Register 4 High
CAN_MSGARL9 0x200428 Message Object 9 Arbitration Register Low
CAN_MSGARH9 0x20042A Message Object 9 Arbitration Register High
CAN_MSGAMRL9 0x20042C Message Object 9 Arbitration Mask Register Low
CAN_MSGAMRH9 0x20042E Message Object 9 Arbitration Mask Register High
CAN_MSGCTRL9 0x200430 Message Object 9 Message Control Register Low
CAN_MSGCTRH9 0x200432 Message Object 9 Message Control Register High
CAN_MSGCFGL9 0x200434 Message Object 9 Message Configuration Register Low
CAN_MSGCFGH9 0x200436 Message Object 9 Message Configuration Register High
CAN_MSGFGCRL9 0x200438 Message Object 9 FIFO/Gateway Control Register Low
CAN_MSGFGCRH9 0x20043A Message Object 9 FIFO/Gateway Control Register High
CAN_MSGDRL100 0x200440 Message Object 10 Data Register 0 Low
CAN_MSGDRH100 0x200442 Message Object 10 Data Register 0 High
CAN_MSGDRL104 0x200444 Message Object 10 Data Register 4 Low
CAN_MSGDRH104 0x200446 Message Object 10 Data Register 4 High
CAN_MSGARL10 0x200448 Message Object 10 Arbitration Register Low
CAN_MSGARH10 0x20044A Message Object 10 Arbitration Register High
CAN_MSGAMRL10 0x20044C Message Object 10 Arbitration Mask Register Low
CAN_MSGAMRH10 0x20044E Message Object 10 Arbitration Mask Register High
CAN_MSGCTRL10 0x200450 Message Object 10 Message Control Register Low
CAN_MSGCTRH10 0x200452 Message Object 10 Message Control Register High
CAN_MSGCFGL10 0x200454 Message Object 10 Message Configuration Register Low
CAN_MSGCFGH10 0x200456 Message Object 10 Message Configuration Register High
CAN_MSGFGCRL10 0x200458 Message Object 10 FIFO/Gateway Control Register Low
CAN_MSGFGCRH10 0x20045A Message Object 10 FIFO/Gateway Control Register High
CAN_MSGDRL110 0x200460 Message Object 11 Data Register 0 Low
CAN_MSGDRH110 0x200462 Message Object 11 Data Register 0 High
CAN_MSGDRL114 0x200464 Message Object 11 Data Register 4 Low
CAN_MSGDRH114 0x200466 Message Object 11 Data Register 4 High
CAN_MSGARL11 0x200468 Message Object 11 Arbitration Register Low
CAN_MSGARH11 0x20046A Message Object 11 Arbitration Register High
CAN_MSGAMRL11 0x20046C Message Object 11 Arbitration Mask Register Low
CAN_MSGAMRH11 0x20046E Message Object 11 Arbitration Mask Register High
CAN_MSGCTRL11 0x200470 Message Object 11 Message Control Register Low
CAN_MSGCTRH11 0x200472 Message Object 11 Message Control Register High
CAN_MSGCFGL11 0x200474 Message Object 11 Message Configuration Register Low
CAN_MSGCFGH11 0x200476 Message Object 11 Message Configuration Register High
CAN_MSGFGCRL11 0x200478 Message Object 11 FIFO/Gateway Control Register Low
CAN_MSGFGCRH11 0x20047A Message Object 11 FIFO/Gateway Control Register High
CAN_MSGDRL120 0x200480 Message Object 12 Data Register 0 Low
CAN_MSGDRH120 0x200482 Message Object 12 Data Register 0 High
CAN_MSGDRL124 0x200484 Message Object 12 Data Register 4 Low
CAN_MSGDRH124 0x200486 Message Object 12 Data Register 4 High
CAN_MSGARL12 0x200488 Message Object 12 Arbitration Register Low
CAN_MSGARH12 0x20048A Message Object 12 Arbitration Register High
CAN_MSGAMRL12 0x20048C Message Object 12 Arbitration Mask Register Low
CAN_MSGAMRH12 0x20048E Message Object 12 Arbitration Mask Register High
CAN_MSGCTRL12 0x200490 Message Object 12 Message Control Register Low
CAN_MSGCTRH12 0x200492 Message Object 12 Message Control Register High
CAN_MSGCFGL12 0x200494 Message Object 12 Message Configuration Register Low
CAN_MSGCFGH12 0x200496 Message Object 12 Message Configuration Register High
CAN_MSGFGCRL12 0x200498 Message Object 12 FIFO/Gateway Control Register Low
CAN_MSGFGCRH12 0x20049A Message Object 12 FIFO/Gateway Control Register High
CAN_MSGDRL130 0x2004A0 Message Object 13 Data Register 0 Low
CAN_MSGDRH130 0x2004A2 Message Object 13 Data Register 0 High
CAN_MSGDRL134 0x2004A4 Message Object 13 Data Register 4 Low
CAN_MSGDRH134 0x2004A6 Message Object 13 Data Register 4 High
CAN_MSGARL13 0x2004A8 Message Object 13 Arbitration Register Low
CAN_MSGARH13 0x2004AA Message Object 13 Arbitration Register High
CAN_MSGAMRL13 0x2004AC Message Object 13 Arbitration Mask Register Low
CAN_MSGAMRH13 0x2004AE Message Object 13 Arbitration Mask Register High
CAN_MSGCTRL13 0x2004B0 Message Object 13 Message Control Register Low
CAN_MSGCTRH13 0x2004B2 Message Object 13 Message Control Register High
CAN_MSGCFGL13 0x2004B4 Message Object 13 Message Configuration Register Low
CAN_MSGCFGH13 0x2004B6 Message Object 13 Message Configuration Register High
CAN_MSGFGCRL13 0x2004B8 Message Object 13 FIFO/Gateway Control Register Low
CAN_MSGFGCRH13 0x2004BA Message Object 13 FIFO/Gateway Control Register High
CAN_MSGDRL140 0x2004C0 Message Object 14 Data Register 0 Low
CAN_MSGDRH140 0x2004C2 Message Object 14 Data Register 0 High
CAN_MSGDRL144 0x2004C4 Message Object 14 Data Register 4 Low
CAN_MSGDRH144 0x2004C6 Message Object 14 Data Register 4 High
CAN_MSGARL14 0x2004C8 Message Object 14 Arbitration Register Low
CAN_MSGARH14 0x2004CA Message Object 14 Arbitration Register High
CAN_MSGAMRL14 0x2004CC Message Object 14 Arbitration Mask Register Low
CAN_MSGAMRH14 0x2004CE Message Object 14 Arbitration Mask Register High
CAN_MSGCTRL14 0x2004D0 Message Object 14 Message Control Register Low
CAN_MSGCTRH14 0x2004D2 Message Object 14 Message Control Register High
CAN_MSGCFGL14 0x2004D4 Message Object 14 Message Configuration Reg Low
CAN_MSGCFGH14 0x2004D6 Message Object 14 Message Configuration Register High
CAN_MSGFGCRL14 0x2004D8 Message Object 14 FIFO/Gateway Control Register Low
CAN_MSGFGCRH14 0x2004DA Message Object 14 FIFO/Gateway Control Register High
CAN_MSGDRL150 0x2004E0 Message Object 15 Data Register 0 Low
CAN_MSGDRH150 0x2004E2 Message Object 15 Data Register 0 High
CAN_MSGDRL154 0x2004E4 Message Object 15 Data Register 4 Low
CAN_MSGDRH154 0x2004E6 Message Object 15 Data Register 4 High
CAN_MSGARL15 0x2004E8 Message Object 15 Arbitration Register Low
CAN_MSGARH15 0x2004EA Message Object 15 Arbitration Register High
CAN_MSGAMRL15 0x2004EC Message Object 15 Arbitration Mask Register Low
CAN_MSGAMRH15 0x2004EE Message Object 15 Arbitration Mask Register High
CAN_MSGCTRL15 0x2004F0 Message Object 15 Message Control Register Low
CAN_MSGCTRH15 0x2004F2 Message Object 15 Message Control Register High
CAN_MSGCFGL15 0x2004F4 Message Object 15 Message Configuration Register Low
CAN_MSGCFGH15 0x2004F6 Message Object 15 Message Configuration Register High
CAN_MSGFGCRL15 0x2004F8 Message Object 15 FIFO/Gateway Control Register Low
CAN_MSGFGCRH15 0x2004FA Message Object 15 FIFO/Gateway Control Register High
CAN_MSGDRL160 0x200500 Message Object 16 Data Register 0 Low
CAN_MSGDRH160 0x200502 Message Object 16 Data Register 0 High
CAN_MSGDRL164 0x200504 Message Object 16 Data Register 4 Low
CAN_MSGDRH164 0x200506 Message Object 16 Data Register 4 High
CAN_MSGARL16 0x200508 Message Object 16 Arbitration Register Low
CAN_MSGARH16 0x20050A Message Object 16 Arbitration Register High
CAN_MSGAMRL16 0x20050C Message Object 16 Arbitration Mask Register Low
CAN_MSGAMRH16 0x20050E Message Object 16 Arbitration Mask Register High
CAN_MSGCTRL16 0x200510 Message Object 16 Message Control Register Low
CAN_MSGCTRH16 0x200512 Message Object 16 Message Control Register High
CAN_MSGCFGL16 0x200514 Message Object 16 Message Configuration Register Low
CAN_MSGCFGH16 0x200516 Message Object 16 Message Configuration Register High
CAN_MSGFGCRL16 0x200518 Message Object 16 FIFO/Gateway Control Register Low
CAN_MSGFGCRH16 0x20051A Message Object 16 FIFO/Gateway Control Register High
CAN_MSGDRL170 0x200520 Message Object 17 Data Register 0 Low
CAN_MSGDRH170 0x200522 Message Object 17 Data Register 0 High
CAN_MSGDRL174 0x200524 Message Object 17 Data Register 4 Low
CAN_MSGDRH174 0x200526 Message Object 17 Data Register 4 High
CAN_MSGARL17 0x200528 Message Object 17 Arbitration Register Low
CAN_MSGARH17 0x20052A Message Object 17 Arbitration Register High
CAN_MSGAMRL17 0x20052C Message Object 17 Arbitration Mask Register Low
CAN_MSGAMRH17 0x20052E Message Object 17 Arbitration Mask Register High
CAN_MSGCTRL17 0x200530 Message Object 17 Message Control Register Low
CAN_MSGCTRH17 0x200532 Message Object 17 Message Control Register High
CAN_MSGCFGL17 0x200534 Message Object 17 Message Configuration Register Low
CAN_MSGCFGH17 0x200536 Message Object 17 Message Configuration Register High
CAN_MSGFGCRL17 0x200538 Message Object 17 FIFO/Gateway Control Register Low
CAN_MSGFGCRH17 0x20053A Message Object 17 FIFO/Gateway Control Register High
CAN_MSGDRL180 0x200540 Message Object 18 Data Register 0 Low
CAN_MSGDRH180 0x200542 Message Object 18 Data Register 0 High
CAN_MSGDRL184 0x200544 Message Object 18 Data Register 4 Low
CAN_MSGDRH184 0x200546 Message Object 18 Data Register 4 High
CAN_MSGARL18 0x200548 Message Object 18 Arbitration Register Low
CAN_MSGARH18 0x20054A Message Object 18 Arbitration Register High
CAN_MSGAMRL18 0x20054C Message Object 18 Arbitration Mask Register Low
CAN_MSGAMRH18 0x20054E Message Object 18 Arbitration Mask Register High
CAN_MSGCTRL18 0x200550 Message Object 18 Message Control Register Low
CAN_MSGCTRH18 0x200552 Message Object 18 Message Control Register High
CAN_MSGCFGL18 0x200554 Message Object 18 Message Configuration Register Low
CAN_MSGCFGH18 0x200556 Message Object 18 Message Configuration Register High
CAN_MSGFGCRL18 0x200558 Message Object 18 FIFO/Gateway Control Register Low
CAN_MSGFGCRH18 0x20055A Message Object 18 FIFO/Gateway Control Register High
CAN_MSGDRL190 0x200560 Message Object 19 Data Register 0 Low
CAN_MSGDRH190 0x200562 Message Object 19 Data Register 0 High
CAN_MSGDRL194 0x200564 Message Object 19 Data Register 4 Low
CAN_MSGDRH194 0x200566 Message Object 19 Data Register 4 High
CAN_MSGARL19 0x200568 Message Object 19 Arbitration Register Low
CAN_MSGARH19 0x20056A Message Object 19 Arbitration Register High
CAN_MSGAMRL19 0x20056C Message Object 19 Arbitration Mask Register Low
CAN_MSGAMRH19 0x20056E Message Object 19 Arbitration Mask Register High
CAN_MSGCTRL19 0x200570 Message Object 19 Message Control Register Low
CAN_MSGCTRH19 0x200572 Message Object 19 Message Control Register High
CAN_MSGCFGL19 0x200574 Message Object 19 Message Configuration Register Low
CAN_MSGCFGH19 0x200576 Message Object 19 Message Configuration Register High
CAN_MSGFGCRL19 0x200578 Message Object 19 FIFO/Gateway Control Register Low
CAN_MSGFGCRH19 0x20057A Message Object 19 FIFO/Gateway Control Register High
CAN_MSGDRL200 0x200580 Message Object 20 Data Register 0 Low
CAN_MSGDRH200 0x200582 Message Object 20 Data Register 0 High
CAN_MSGDRL204 0x200584 Message Object 20 Data Register 4 Low
CAN_MSGDRH204 0x200586 Message Object 20 Data Register 4 High
CAN_MSGARL20 0x200588 Message Object 20 Arbitration Register Low
CAN_MSGARH20 0x20058A Message Object 20 Arbitration Register High
CAN_MSGAMRL20 0x20058C Message Object 20 Arbitration Mask Register Low
CAN_MSGAMRH20 0x20058E Message Object 20 Arbitration Mask Register High
CAN_MSGCTRL20 0x200590 Message Object 20 Message Control Register Low
CAN_MSGCTRH20 0x200592 Message Object 20 Message Control Register High
CAN_MSGCFGL20 0x200594 Message Object 20 Message Configuration Register Low
CAN_MSGCFGH20 0x200596 Message Object 20 Message Configuration Register High
CAN_MSGFGCRL20 0x200598 Message Object 20 FIFO/Gateway Control Register Low
CAN_MSGFGCRH20 0x20059A Message Object 20 FIFO/Gateway Control Register High
CAN_MSGDRL210 0x2005A0 Message Object 21 Data Register 0 Low
CAN_MSGDRH210 0x2005A2 Message Object 21 Data Register 0 High
CAN_MSGDRL214 0x2005A4 Message Object 21 Data Register 4 Low
CAN_MSGDRH214 0x2005A6 Message Object 21 Data Register 4 High
CAN_MSGARL21 0x2005A8 Message Object 21 Arbitration Register Low
CAN_MSGARH21 0x2005AA Message Object 21 Arbitration Register High
CAN_MSGAMRL21 0x2005AC Message Object 21 Arbitration Mask Register Low
CAN_MSGAMRH21 0x2005AE Message Object 21 Arbitration Mask Register High
CAN_MSGCTRL21 0x2005B0 Message Object 21 Message Control Register Low
CAN_MSGCTRH21 0x2005B2 Message Object 21 Message Control Register High
CAN_MSGCFGL21 0x2005B4 Message Object 21 Message Configuration Register Low
CAN_MSGCFGH21 0x2005B6 Message Object 21 Message Configuration Register High
CAN_MSGFGCRL21 0x2005B8 Message Object 21 FIFO/Gateway Control Register Low
CAN_MSGFGCRH21 0x2005BA Message Object 21 FIFO/Gateway Control Register High
CAN_MSGDRL220 0x2005C0 Message Object 22 Data Register 0 Low
CAN_MSGDRH220 0x2005C2 Message Object 22 Data Register 0 High
CAN_MSGDRL224 0x2005C4 Message Object 22 Data Register 4 Low
CAN_MSGDRH224 0x2005C6 Message Object 22 Data Register 4 High
CAN_MSGARL22 0x2005C8 Message Object 22 Arbitration Register Low
CAN_MSGARH22 0x2005CA Message Object 22 Arbitration Register High
CAN_MSGAMRL22 0x2005CC Message Object 22 Arbitration Mask Register Low
CAN_MSGAMRH22 0x2005CE Message Object 22 Arbitration Mask Register High
CAN_MSGCTRL22 0x2005D0 Message Object 22 Message Control Register Low
CAN_MSGCTRH22 0x2005D2 Message Object 22 Message Control Register High
CAN_MSGCFGL22 0x2005D4 Message Object 22 Message Configuration Register Low
CAN_MSGCFGH22 0x2005D6 Message Object 22 Message Configuration Register High
CAN_MSGFGCRL22 0x2005D8 Message Object 22 FIFO/Gateway Control Register Low
CAN_MSGFGCRH22 0x2005DA Message Object 22 FIFO/Gateway Control Register High
CAN_MSGDRL230 0x2005E0 Message Object 23 Data Register 0 Low
CAN_MSGDRH230 0x2005E2 Message Object 23 Data Register 0 High
CAN_MSGDRL234 0x2005E4 Message Object 23 Data Register 4 Low
CAN_MSGDRH234 0x2005E6 Message Object 23 Data Register 4 High
CAN_MSGARL23 0x2005E8 Message Object 23 Arbitration Register Low
CAN_MSGARH23 0x2005EA Message Object 23 Arbitration Register High
CAN_MSGAMRL23 0x2005EC Message Object 23 Arbitration Mask Register Low
CAN_MSGAMRH23 0x2005EE Message Object 23 Arbitration Mask Register High
CAN_MSGCTRL23 0x2005F0 Message Object 23 Message Control Register Low
CAN_MSGCTRH23 0x2005F2 Message Object 23 Message Control Register High
CAN_MSGCFGL23 0x2005F4 Message Object 23 Message Configuration Register Low
CAN_MSGCFGH23 0x2005F6 Message Object 23 Message Configuration Register High
CAN_MSGFGCRL23 0x2005F8 Message Object 23 FIFO/Gateway Control Register Low
CAN_MSGFGCRH23 0x2005FA Message Object 23 FIFO/Gateway Control Register High
CAN_MSGDRL240 0x200600 Message Object 24 Data Register 0 Low
CAN_MSGDRH240 0x200602 Message Object 24 Data Register 0 High
CAN_MSGDRL244 0x200604 Message Object 24 Data Register 4 Low
CAN_MSGDRH244 0x200606 Message Object 24 Data Register 4 High
CAN_MSGARL24 0x200608 Message Object 24 Arbitration Register Low
CAN_MSGARH24 0x20060A Message Object 24 Arbitration Register High
CAN_MSGAMRL24 0x20060C Message Object 24 Arbitration Mask Register Low
CAN_MSGAMRH24 0x20060E Message Object 24 Arbitration Mask Register High
CAN_MSGCTRL24 0x200610 Message Object 24 Message Control Register Low
CAN_MSGCTRH24 0x200612 Message Object 24 Message Control Register High
CAN_MSGCFGL24 0x200614 Message Object 24 Message Configuration Register Low
CAN_MSGCFGH24 0x200616 Message Object 24 Message Configuration Register High
CAN_MSGFGCRL24 0x200618 Message Object 24 FIFO/Gateway Control Register Low
CAN_MSGFGCRH24 0x20061A Message Object 24 FIFO/Gateway Control Register High
CAN_MSGDRL250 0x200620 Message Object 25 Data Register 0 Low
CAN_MSGDRH250 0x200622 Message Object 25 Data Register 0 High
CAN_MSGDRL254 0x200624 Message Object 25 Data Register 4 Low
CAN_MSGDRH254 0x200626 Message Object 25 Data Register 4 High
CAN_MSGARL25 0x200628 Message Object 25 Arbitration Register Low
CAN_MSGARH25 0x20062A Message Object 25 Arbitration Register High
CAN_MSGAMRL25 0x20062C Message Object 25 Arbitration Mask Register Low
CAN_MSGAMRH25 0x20062E Message Object 25 Arbitration Mask Register High
CAN_MSGCTRL25 0x200630 Message Object 25 Message Control Register Low
CAN_MSGCTRH25 0x200632 Message Object 25 Message Control Register High
CAN_MSGCFGL25 0x200634 Message Object 25 Message Configuration Register Low
CAN_MSGCFGH25 0x200636 Message Object 25 Message Configuration Register High
CAN_MSGFGCRL25 0x200638 Message Object 25 FIFO/Gateway Control Register Low
CAN_MSGFGCRH25 0x20063A Message Object 25 FIFO/Gateway Control Register High
CAN_MSGDRL260 0x200640 Message Object 26 Data Register 0 Low
CAN_MSGDRH260 0x200642 Message Object 26 Data Register 0 High
CAN_MSGDRL264 0x200644 Message Object 26 Data Register 4 Low
CAN_MSGDRH264 0x200646 Message Object 26 Data Register 4 High
CAN_MSGARL26 0x200648 Message Object 26 Arbitration Register Low
CAN_MSGARH26 0x20064A Message Object 26 Arbitration Register High
CAN_MSGAMRL26 0x20064C Message Object 26 Arbitration Mask Register Low
CAN_MSGAMRH26 0x20064E Message Object 26 Arbitration Mask Register High
CAN_MSGCTRL26 0x200650 Message Object 26 Message Control Register Low
CAN_MSGCTRH26 0x200652 Message Object 26 Message Control Register High
CAN_MSGCFGL26 0x200654 Message Object 26 Message Configuration Register Low
CAN_MSGCFGH26 0x200656 Message Object 26 Message Configuration Register High
CAN_MSGFGCRL26 0x200658 Message Object 26 FIFO/Gateway Control Register Low
CAN_MSGFGCRH26 0x20065A Message Object 26 FIFO/Gateway Control Register High
CAN_MSGDRL270 0x200660 Message Object 27 Data Register 0 Low
CAN_MSGDRH270 0x200662 Message Object 27 Data Register 0 High
CAN_MSGDRL274 0x200664 Message Object 27 Data Register 4 Low
CAN_MSGDRH274 0x200666 Message Object 27 Data Register 4 High
CAN_MSGARL27 0x200668 Message Object 27 Arbitration Register Low
CAN_MSGARH27 0x20066A Message Object 27 Arbitration Register High
CAN_MSGAMRL27 0x20066C Message Object 27 Arbitration Mask Register Low
CAN_MSGAMRH27 0x20066E Message Object 27 Arbitration Mask Register High
CAN_MSGCTRL27 0x200670 Message Object 27 Message Control Register Low
CAN_MSGCTRH27 0x200672 Message Object 27 Message Control Register High
CAN_MSGCFGL27 0x200674 Message Object 27 Message Configuration Register Low
CAN_MSGCFGH27 0x200676 Message Object 27 Message Configuration Register High
CAN_MSGFGCRL27 0x200678 Message Object 27 FIFO/Gateway Control Register Low
CAN_MSGFGCRH27 0x20067A Message Object 27 FIFO/Gateway Control Register High
CAN_MSGDRL280 0x200680 Message Object 28 Data Register 0 Low
CAN_MSGDRH280 0x200682 Message Object 28 Data Register 0 High
CAN_MSGDRL284 0x200684 Message Object 28 Data Register 4 Low
CAN_MSGDRH284 0x200686 Message Object 28 Data Register 4 High
CAN_MSGARL28 0x200688 Message Object 28 Arbitration Register Low
CAN_MSGARH28 0x20068A Message Object 28 Arbitration Register High
CAN_MSGAMRL28 0x20068C Message Object 28 Arbitration Mask Register Low
CAN_MSGAMRH28 0x20068E Message Object 28 Arbitration Mask Register High
CAN_MSGCTRL28 0x200690 Message Object 28 Message Control Register Low
CAN_MSGCTRH28 0x200692 Message Object 28 Message Control Register High
CAN_MSGCFGL28 0x200694 Message Object 28 Message Configuration Register Low
CAN_MSGCFGH28 0x200696 Message Object 28 Message Configuration Register High
CAN_MSGFGCRL28 0x200698 Message Object 28 FIFO/Gateway Control Register Low
CAN_MSGFGCRH28 0x20069A Message Object 28 FIFO/Gateway Control Register High
CAN_MSGDRL290 0x2006A0 Message Object 29 Data Register 0 Low
CAN_MSGDRH290 0x2006A2 Message Object 29 Data Register 0 High
CAN_MSGDRL294 0x2006A4 Message Object 29 Data Register 4 Low
CAN_MSGDRH294 0x2006A6 Message Object 29 Data Register 4 High
CAN_MSGARL29 0x2006A8 Message Object 29 Arbitration Register Low
CAN_MSGARH29 0x2006AA Message Object 29 Arbitration Register High
CAN_MSGAMRL29 0x2006AC Message Object 29 Arbitration Mask Register Low
CAN_MSGAMRH29 0x2006AE Message Object 29 Arbitration Mask Register High
CAN_MSGCTRL29 0x2006B0 Message Object 29 Message Control Register Low
CAN_MSGCTRH29 0x2006B2 Message Object 29 Message Control Register High
CAN_MSGCFGL29 0x2006B4 Message Object 29 Message Configuration Register Low
CAN_MSGCFGH29 0x2006B6 Message Object 29 Message Configuration Register High
CAN_MSGFGCRL29 0x2006B8 Message Object 29 FIFO/Gateway Control Register Low
CAN_MSGFGCRH29 0x2006BA Message Object 29 FIFO/Gateway Control Register High
CAN_MSGDRL300 0x2006C0 Message Object 30 Data Register 0 Low
CAN_MSGDRH300 0x2006C2 Message Object 30 Data Register 0 High
CAN_MSGDRL304 0x2006C4 Message Object 30 Data Register 4 Low
CAN_MSGDRH304 0x2006C6 Message Object 30 Data Register 4 High
CAN_MSGARL30 0x2006C8 Message Object 30 Arbitration Register Low
CAN_MSGARH30 0x2006CA Message Object 30 Arbitration Register High
CAN_MSGAMRL30 0x2006CC Message Object 30 Arbitration Mask Register Low
CAN_MSGAMRH30 0x2006CE Message Object 30 Arbitration Mask Register High
CAN_MSGCTRL30 0x2006D0 Message Object 30 Message Control Register Low
CAN_MSGCTRH30 0x2006D2 Message Object 30 Message Control Register High
CAN_MSGCFGL30 0x2006D4 Message Object 30 Message Configuration Register Low
CAN_MSGCFGH30 0x2006D6 Message Object 30 Message Configuration Register High
CAN_MSGFGCRL30 0x2006D8 Message Object 30 FIFO/Gateway Control Register Low
CAN_MSGFGCRH30 0x2006DA Message Object 30 FIFO/Gateway Control Register High
CAN_MSGDRL310 0x2006E0 Message Object 31 Data Register 0 Low
CAN_MSGDRH310 0x2006E2 Message Object 31 Data Register 0 High
CAN_MSGDRL314 0x2006E4 Message Object 31 Data Register 4 Low
CAN_MSGDRH314 0x2006E6 Message Object 31 Data Register 4 High
CAN_MSGARL31 0x2006E8 Message Object 31 Arbitration Register Low
CAN_MSGARH31 0x2006EA Message Object 31 Arbitration Register High
CAN_MSGAMRL31 0x2006EC Message Object 31 Arbitration Mask Register Low
CAN_MSGAMRH31 0x2006EE Message Object 31 Arbitration Mask Register High
CAN_MSGCTRL31 0x2006F0 Message Object 31 Message Control Register Low
CAN_MSGCTRH31 0x2006F2 Message Object 31 Message Control Register High
CAN_MSGCFGL31 0x2006F4 Message Object 31 Message Configuration Register Low
CAN_MSGCFGH31 0x2006F6 Message Object 31 Message Configuration Register High
CAN_MSGFGCRL31 0x2006F8 Message Object 31 FIFO/Gateway Control Register Low
CAN_MSGFGCRH31 0x2006FA Message Object 31 FIFO/Gateway Control Register High