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Version:
9.1~250226-1.fc41 ▾
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; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; ST7 FAMILY SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:
; area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
; START and END are addresses, the end address is not included
; Interrupt vectors are declared in the following way:
; entry NAME ADDRESS COMMENT
.default
.ST72101
; :ST72101 :ST72101G1 :ST72101G2 :ST72T101G1 :ST72T101G1B6 :ST72T101G1M6 \
; :ST72T101G2 :ST72T101G2B6 :ST72T101G2M6
; http://us.st.com/stonline/books/pdf/docs/5762.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0040
area BSS RESERVED 0x0040:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt EI0_ 0xFFFA External Interrupt Vector EI0
interrupt EI1_ 0xFFF8 External Interrupt Vector EI1
interrupt SPI_ 0xFFF4 SPI Interrupt Vector
interrupt TIMER_A 0xFFF2 TIMER A Interrupt Vector
interrupt TIMER_B 0xFFEE TIMER B Interrupt Vector (ST72212 only)
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR 0x0020 Miscellaneous Register
MISCR.PEI3 7 External Interrupt EI1 Polarity Option 3
MISCR.PEI2 6 External Interrupt EI1 Polarity Option 2
MISCR.MCO 5 Main Clock Out
MISCR.PEI1 4 External Interrupt EI0 Polarity Option 1
MISCR.PEI0 3 External Interrupt EI0 Polarity Option 0
MISCR.SMS 0 Slow Mode Select
SPIDR 0x0021 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 PWM Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture1 High Register
TAIC1LR 0x0035 Timer A Input Capture1 Low Register
TAOC1HR 0x0036 Timer A Output Compare1 High Register
TAOC1LR 0x0037 Timer A Output Compare1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture2 High Register
TAIC2LR 0x003D Timer A Input Capture2 Low Register
TAOC2HR 0x003E Timer A Output Compare2 High Register
TAOC2LR 0x003F Timer A Output Compare2 Low Register
RESERVED0040 0x0040 RESERVED
.ST72104G1
; :ST72104G1 :ST72104G1B1 :ST72104G1B3 :ST72104G1B5 :ST72104G1B6 :ST72104G1B7 \
; :ST72104G1M1 :ST72104G1M3 :ST72104G1M5 :ST72104G1M6 :ST72104G1M7 :ST72C104G1 \
; :ST72C104G1B1 :ST72C104G1B3 :ST72C104G1B5 :ST72C104G1B6 :ST72C104G1B7 \
; :ST72C104G1M1 :ST72C104G1M3 :ST72C104G1M5 :ST72C104G1M6 :ST72C104G1M6/TR \
; :ST72C104G1M7
; http://us.st.com/stonline/books/pdf/docs/6815.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0040
area BSS RESERVED 0x0040:0x0080
area DATA RAM_ 0x0080:0x0180
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt ei0_ 0xFFFA External Interrupt Port A7..0 (C5..0)
interrupt ei1_ 0xFFF8 External Interrupt Port B7..0 (C5..0)
interrupt CSS_ 0xFFF6 Clock Security System Interrupt
interrupt SPI_ 0xFFF4 SPI Peripheral Interrupts
interrupt TIMER_A 0xFFF2 TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFEE TIMER B Peripheral Interrupts
interrupt I_C 0xFFE4 IC Peripheral Interrupt
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei1 sensitivity 1
MISCR1.IS10 6 ei1 sensitivity 0
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei0 sensitivity 1
MISCR1.IS00 3 ei0 sensitivity 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.MOD 3 SPI Master Output Disable
MISCR2.SOD 2 SPI Slave Output Disable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
.ST72104G2
; :ST72104G2 :ST72104G2B1 :ST72104G2B3 :ST72104G2B5 :ST72104G2B6 :ST72104G2B7 \
; :ST72104G2M1 :ST72104G2M3 :ST72104G2M5 :ST72104G2M6 :ST72104G2M7 \
; :ST72C104G2 :ST72C104G2B1 :ST72C104G2B3 :ST72C104G2B5 :ST72C104G2B6 \
; :ST72C104G2B7 :ST72C104G2M1 :ST72C104G2M3 :ST72C104G2M5 :ST72C104G2M6 :ST72C104G2M7
; http://us.st.com/stonline/books/pdf/docs/6815.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0040
area BSS RESERVED 0x0040:0x0080
area DATA RAM_ 0x0080:0x0180
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt ei0_ 0xFFFA External Interrupt Port A7..0 (C5..0)
interrupt ei1_ 0xFFF8 External Interrupt Port B7..0 (C5..0)
interrupt CSS_ 0xFFF6 Clock Security System Interrupt
interrupt SPI_ 0xFFF4 SPI Peripheral Interrupts
interrupt TIMER_A 0xFFF2 TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFEE TIMER B Peripheral Interrupts
interrupt I_C 0xFFE4 IC Peripheral Interrupt
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei1 sensitivity 1
MISCR1.IS10 6 ei1 sensitivity 0
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei0 sensitivity 1
MISCR1.IS00 3 ei0 sensitivity 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.MOD 3 SPI Master Output Disable
MISCR2.SOD 2 SPI Slave Output Disable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
.ST72121
; :ST72121 :ST72121J2 :ST72121J4 :ST72T121J2 :ST72T121J2B6 :ST72T121J2B6S \
; :ST72T121J2T6 :ST72T121J2T6S :ST72T121J4 :ST72T121J4B6 :ST72T121J4B6S \
; :ST72T121J4T6 :ST72T121J4T6S
; http://us.st.com/stonline/books/pdf/docs/5907.pdf
; MEMORY MAP
; ST72T121J2
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0080
area DATA RAM_ 0x0080:0x0200
area BSS RESERVED 0x0200:0xC000
; ST72T121J4
; area DATA FSR_1 0x0000:0x0058
; area BSS RESERVED 0x0058:0x0080
; area DATA RAM_ 0x0080:0x0280
; area BSS RESERVED 0x0280:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP 0xFFFC TRAP (software) Interrupt Vector
interrupt EI0_ 0xFFF6 External Interrupt Vector EI0 (PA3)
interrupt EI1_ 0xFFF4 External Interrupt Vector EI1 (PF0:PF2)
interrupt EI2_ 0xFFF2 External Interrupt Vector EI2 (PB0:PB3)
interrupt EI3_ 0xFFF0 External Interrupt Vector EI3 (PB4)
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt TIMER_A 0xFFEA TIMER A Interrupt Vector
interrupt TIMER_B 0xFFE8 TIMER B Interrupt Vector
interrupt SCI_ 0xFFE6 SCI Interrupt Vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR 0x0020 Miscellaneous Register
MISCR.PEI3 7 External Interrupt EI3 Polarity Option
MISCR.PEI2 6 External Interrupt EI2 Polarity Option
MISCR.MCO 5 Main Clock Out
MISCR.PEI1 4 External Interrupt EI1 Polarity Option
MISCR.PEI0 3 External Interrupt EI0 Polarity Option
MISCR.PSM1 2 Prescaler for Slow Mode 1
MISCR.PSM0 1 Prescaler for Slow Mode 0
MISCR.SMS 0 Slow Mode Select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
RESERVED0040 0x0040 RESERVED
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
.ST72124J
; :ST72124J :ST72124J2 :ST72C124J2 :ST72C124J2B6 :ST72C124J2T6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=384
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0080
area DATA RAM 0x0080:0x0200
area BSS RESERVED 0x0200:0x0C00
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
.ST72141
; :ST72141 :ST72141K2 :ST72141K2B6 :ST72141K2M6 :ST72T141K2 :ST72T141K2B6 \
; :ST72T141K2M6
; http://us.st.com/stonline/books/pdf/docs/6342.pdf
; RAM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0007
area BSS RESERVED 0x0007:0x0020
area DATA FSR_2 0x0020:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) interrupt vector
interrupt EI0_ 0xFFF8 External interrupt vector EI0: port A7..0
interrupt EI1_ 0xFFF6 External interrupt vector EI1: port B7..0
interrupt MCIV_1 0xFFF4 Motor control interrupt vector (events: R, Z)
interrupt MCIV_2 0xFFF2 Motor control interrupt vector (events: C, D)
interrupt MCIV_3 0xFFF0 Motor control interrupt vector (events: E, O)
interrupt SPI_ 0xFFEE SPI interrupt vector
interrupt TIMER_A 0xFFEC TIMER A interrupt vector
interrupt TIMER_B 0xFFEA TIMER B interrupt vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
MISCR 0x0020 Miscellaneous Register
MISCR.XT16 7 MTC and SPI clock selection
MISCR.SSM 6 SS mode selection
MISCR.SSI 5 SS internal mode
MISCR.IS11 4 EI1 sensitivity 1
MISCR.IS10 3 EI1 sensitivity 0
MISCR.IS01 2 EI0 sensitivity 1
MISCR.IS00 1 EI0 sensitivity 0
MISCR.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x0025 Watchdog STATUS REGISTER
WDGSR.WDOGF 0 Watchdog flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
RESERVED0040 0x0040 RESERVED
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
RESERVED0050 0x0050 RESERVED
RESERVED0051 0x0051 RESERVED
RESERVED0052 0x0052 RESERVED
RESERVED0053 0x0053 RESERVED
RESERVED0054 0x0054 RESERVED
RESERVED0055 0x0055 RESERVED
RESERVED0056 0x0056 RESERVED
RESERVED0057 0x0057 RESERVED
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
RESERVED005A 0x005A RESERVED
RESERVED005B 0x005B RESERVED
RESERVED005C 0x005C RESERVED
RESERVED005D 0x005D RESERVED
RESERVED005E 0x005E RESERVED
RESERVED005F 0x005F RESERVED
MTIM 0x0060 MOTOR CONTROLLER Timer Counter Register
MTIM.T7 7 MTIM Counter Value 7
MTIM.T6 6 MTIM Counter Value 6
MTIM.T5 5 MTIM Counter Value 5
MTIM.T4 4 MTIM Counter Value 4
MTIM.T3 3 MTIM Counter Value 3
MTIM.T2 2 MTIM Counter Value 2
MTIM.T1 1 MTIM Counter Value 1
MTIM.T0 0 MTIM Counter Value 0
MZPRV 0x0061 MOTOR CONTROLLER Zn-1 Capture Register
MZPRV.ZP7 7 Previous Z Value 7
MZPRV.ZP6 6 Previous Z Value 6
MZPRV.ZP5 5 Previous Z Value 5
MZPRV.ZP4 4 Previous Z Value 4
MZPRV.ZP3 3 Previous Z Value 3
MZPRV.ZP2 2 Previous Z Value 2
MZPRV.ZP1 1 Previous Z Value 1
MZPRV.ZP0 0 Previous Z Value 0
MZREG 0x0062 MOTOR CONTROLLER Zn Capture Register
MZREG.ZC7 7 Current Z Value 7
MZREG.ZC6 6 Current Z Value 6
MZREG.ZC5 5 Current Z Value 5
MZREG.ZC4 4 Current Z Value 4
MZREG.ZC3 3 Current Z Value 3
MZREG.ZC2 2 Current Z Value 2
MZREG.ZC1 1 Current Z Value 1
MZREG.ZC0 0 Current Z Value 0
MCOMP 0x0063 MOTOR CONTROLLER C n+1 Compare Register
MCOMP.DC7 7 Next Compare Value 7
MCOMP.DC6 6 Next Compare Value 6
MCOMP.DC5 5 Next Compare Value 5
MCOMP.DC4 4 Next Compare Value 4
MCOMP.DC3 3 Next Compare Value 3
MCOMP.DC2 2 Next Compare Value 2
MCOMP.DC1 1 Next Compare Value 1
MCOMP.DC0 0 Next Compare Value 0
MDREG 0x0064 MOTOR CONTROLLER D capture/Compare Register
MDREG.DN7 7 D Value 7
MDREG.DN6 6 D Value 6
MDREG.DN5 5 D Value 5
MDREG.DN4 4 D Value 4
MDREG.DN3 3 D Value 3
MDREG.DN2 2 D Value 2
MDREG.DN1 1 D Value 1
MDREG.DN0 0 D Value 0
MWGHT 0x0065 MOTOR CONTROLLER Weight Register
MWGHT.AN7 7 A Weight Value 7
MWGHT.AN6 6 A Weight Value 6
MWGHT.AN5 5 A Weight Value 5
MWGHT.AN4 4 A Weight Value 4
MWGHT.AN3 3 A Weight Value 3
MWGHT.AN2 2 A Weight Value 2
MWGHT.AN1 1 A Weight Value 1
MWGHT.AN0 0 A Weight Value 0
MPRSR 0x0066 MOTOR CONTROLLER Prescaler and Ratio Register
MPRSR.SA3 7 Sampling Ratio 3
MPRSR.SA2 6 Sampling Ratio 2
MPRSR.SA1 5 Sampling Ratio 1
MPRSR.SA0 4 Sampling Ratio 0
MPRSR.ST3 3 Step Ratio 3
MPRSR.ST2 2 Step Ratio 2
MPRSR.ST1 1 Step Ratio 1
MPRSR.ST0 0 Step Ratio 0
MIMR 0x0067 MOTOR CONTROLLER Interrupt Mask Register
MIMR.HST 7 Hysteresis Comparator Value
MIMR.CL 6 Current Loop Comparator Value
MIMR.RIM 5 Ratio update Interrupt Mask bit
MIMR.OIM 4 Multiplier Overflow Interrupt Mask bit
MIMR.EIM 3 Emergency stop Interrupt Mask bit
MIMR.ZIM 2 Back EMF Zero-crossing Interrupt Mask bit
MIMR.DIM 1 End of Demagnetization Interrupt Mask bit
MIMR.CIM 0 Commutation Interrupt Mask bit
MISR 0x0068 MOTOR CONTROLLER Interrupt Status Register
MISR.RPI 6 Ratio Increment interrupt flag
MISR.RMI 5 Ratio Decrement interrupt flag
MISR.OI 4 Multiplier Overflow interrupt flag
MISR.EI 3 Emergency stop Interrupt flag
MISR.ZI 2 BEMF Zero-crossing interrupt flag
MISR.DI 1 End of Demagnetization interrupt flag
MISR.CI 0 Commutation interrupt flag
MCRA 0x0069 MOTOR CONTROLLER Control Register A
MCRA.MOE 7 Output Enable bit
MCRA.RST 6 Reset MTC registers
MCRA.SR 5 Sensor ON/OFF
MCRA.DAC 4 Direct Access to phase state register
MCRA.V0C1 3 Voltage/Current Mode
MCRA.SWA 2 Switched/Autoswitched Mode
MCRA.CFF 1 Current Feedback Filter
MCRA.DCB 0 Data Capture bit
MCRB 0x006A MOTOR CONTROLLER Control Register B
MCRB.VR1 7 BEMF/demagnetization Reference threshold 1
MCRB.VR0 6 BEMF/demagnetization Reference threshold 0
MCRB.CPB 5 Compare Bit for Zero-crossing detection
MCRB.HDM 4 Hardware Demagnetization event Mask bit
MCRB.SDM 3 Software Demagnetization event Mask bit
MCRB.OS2 2 Operating output mode Selection bit 2
MCRB.OS1 1 Operating output mode Selection bit 1
MCRB.OS0 0 Operating output mode Selection bit 0
MPHST 0x006B MOTOR CONTROLLER Phase State Register
MPHST.IS1 7 Input Selection bit 1
MPHST.IS0 6 Input Selection bit 0
MPHST.OO5 5 Channel On/Off bit 5
MPHST.OO4 4 Channel On/Off bit 4
MPHST.OO3 3 Channel On/Off bit 3
MPHST.OO2 2 Channel On/Off bit 2
MPHST.OO1 1 Channel On/Off bit 1
MPHST.OO0 0 Channel On/Off bit 0
MPAR 0x006C MOTOR CONTROLLER Output Parity Register
MPAR.ZVD 7 Z vs D edge polarity
MPAR.REO 6 Read on Even or Odd channel bit
MPAR.OE5 5 Output Parity Mode 5
MPAR.OE4 4 Output Parity Mode 4
MPAR.OE3 3 Output Parity Mode 3
MPAR.OE2 2 Output Parity Mode 2
MPAR.OE1 1 Output Parity Mode 1
MPAR.OE0 0 Output Parity Mode 0
MPOL 0x006D MOTOR CONTROLLER Output Polarity Register
MPOL.OT1 7 Off Time selection 1
MPOL.OT0 6 Off Time selection 0
MPOL.OP5 5 Output channel polarity 5
MPOL.OP4 4 Output channel polarity 4
MPOL.OP3 3 Output channel polarity 3
MPOL.OP2 2 Output channel polarity 2
MPOL.OP1 1 Output channel polarity 1
MPOL.OP0 0 Output channel polarity 0
RESERVED006E 0x006E RESERVED
RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.AD7 7 Analog Converted Value 7
ADCDR.AD6 6 Analog Converted Value 6
ADCDR.AD5 5 Analog Converted Value 5
ADCDR.AD4 4 Analog Converted Value 4
ADCDR.AD3 3 Analog Converted Value 3
ADCDR.AD2 2 Analog Converted Value 2
ADCDR.AD1 1 Analog Converted Value 1
ADCDR.AD0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
RESERVED0072 0x0072 RESERVED
RESERVED0073 0x0073 RESERVED
RESERVED0074 0x0074 RESERVED
RESERVED0075 0x0075 RESERVED
RESERVED0076 0x0076 RESERVED
RESERVED0077 0x0077 RESERVED
RESERVED0078 0x0078 RESERVED
RESERVED0079 0x0079 RESERVED
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72212
; :ST72212 :ST72212G2 :ST72T212G2 :ST72T212G2B3 :ST72T212G2B6 :ST72T212G2M3 \
; :ST72T212G2M3/TR :ST72T212G2M6
; http://us.st.com/stonline/books/pdf/docs/5762.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0050
area BSS RESERVED 0x0050:0x0070
area DATA FSR_3 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt EI0_ 0xFFFA External Interrupt Vector EI0
interrupt EI1_ 0xFFF8 External Interrupt Vector EI1
interrupt SPI_ 0xFFF4 SPI Interrupt Vector
interrupt TIMER_A 0xFFF2 TIMER A Interrupt Vector
interrupt TIMER_B 0xFFEE TIMER B Interrupt Vector (ST72212 only)
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR 0x0020 Miscellaneous Register
MISCR.PEI3 7 External Interrupt EI1 Polarity Option 3
MISCR.PEI2 6 External Interrupt EI1 Polarity Option 2
MISCR.MCO 5 Main Clock Out
MISCR.PEI1 4 External Interrupt EI0 Polarity Option 1
MISCR.PEI0 3 External Interrupt EI0 Polarity Option 0
MISCR.SMS 0 Slow Mode Select
SPIDR 0x0021 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 PWM Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture1 High Register
TAIC1LR 0x0035 Timer A Input Capture1 Low Register
TAOC1HR 0x0036 Timer A Output Compare1 High Register
TAOC1LR 0x0037 Timer A Output Compare1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture2 High Register
TAIC2LR 0x003D Timer A Input Capture2 Low Register
TAOC2HR 0x003E Timer A Output Compare2 High Register
TAOC2LR 0x003F Timer A Output Compare2 Low Register
RESERVED0040 0x0040 RESERVED
TBCR2 0x0041 Timer B Control Register2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 PWM Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture1 High Register
TBIC1LR 0x0045 Timer B Input Capture1 Low Register
TBOC1HR 0x0046 Timer B Output Compare1 High Register
TBOC1LR 0x0047 Timer B Output Compare1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture2 High Register
TBIC2LR 0x004D Timer B Input Capture2 Low Register
TBOC2HR 0x004E Timer B Output Compare2 High Register
TBOC2LR 0x004F Timer B Output Compare2 Low Register
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.AD7 7 Analog Converted Value 7
ADCDR.AD6 6 Analog Converted Value 6
ADCDR.AD5 5 Analog Converted Value 5
ADCDR.AD4 4 Analog Converted Value 4
ADCDR.AD3 3 Analog Converted Value 3
ADCDR.AD2 2 Analog Converted Value 2
ADCDR.AD1 1 Analog Converted Value 1
ADCDR.AD0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72213
; :ST72213 :ST72213G1 :ST72T213G1 :ST72T213G1B6 :ST72T213G1M6
; http://us.st.com/stonline/books/pdf/docs/5762.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0040
area BSS RESERVED 0x0040:0x0070
area DATA FSR_3 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt EI0_ 0xFFFA External Interrupt Vector EI0
interrupt EI1_ 0xFFF8 External Interrupt Vector EI1
interrupt SPI_ 0xFFF4 SPI Interrupt Vector
interrupt TIMER_A 0xFFF2 TIMER A Interrupt Vector
interrupt TIMER_B 0xFFEE TIMER B Interrupt Vector (ST72212 only)
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR 0x0020 Miscellaneous Register
MISCR.PEI3 7 External Interrupt EI1 Polarity Option 3
MISCR.PEI2 6 External Interrupt EI1 Polarity Option 2
MISCR.MCO 5 Main Clock Out
MISCR.PEI1 4 External Interrupt EI0 Polarity Option 1
MISCR.PEI0 3 External Interrupt EI0 Polarity Option 0
MISCR.SMS 0 Slow Mode Select
SPIDR 0x0021 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 PWM Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture1 High Register
TAIC1LR 0x0035 Timer A Input Capture1 Low Register
TAOC1HR 0x0036 Timer A Output Compare1 High Register
TAOC1LR 0x0037 Timer A Output Compare1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture2 High Register
TAIC2LR 0x003D Timer A Input Capture2 Low Register
TAOC2HR 0x003E Timer A Output Compare2 High Register
TAOC2LR 0x003F Timer A Output Compare2 Low Register
RESERVED0040 0x0040 RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.AD7 7 Analog Converted Value 7
ADCDR.AD6 6 Analog Converted Value 6
ADCDR.AD5 5 Analog Converted Value 5
ADCDR.AD4 4 Analog Converted Value 4
ADCDR.AD3 3 Analog Converted Value 3
ADCDR.AD2 2 Analog Converted Value 2
ADCDR.AD1 1 Analog Converted Value 1
ADCDR.AD0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72215G2
; :ST72215G2 :ST72215G2B1 :ST72215G2B3 :ST72215G2B5 :ST72215G2B6 :ST72215G2B7 \
; :ST72215G2M1 :ST72215G2M1/TR :ST72215G2M3 :ST72215G2M5 :ST72215G2M6 :ST72215G2M7
; :ST72C215G2 :ST72C215G2B1 :ST72C215G2B3 :ST72C215G2B5 :ST72C215G2B6 \
; :ST72C215G2B7 :ST72C215G2M1 :ST72C215G2M3 :ST72C215G2M5 :ST72C215G2M6 \
; :ST72C215G2M6/TR :ST72C215G2M7
; http://us.st.com/stonline/books/pdf/docs/6815.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0050
area BSS RESERVED 0x0050:0x0070
area DATA FSR_2 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt ei0_ 0xFFFA External Interrupt Port A7..0 (C5..0)
interrupt ei1_ 0xFFF8 External Interrupt Port B7..0 (C5..0)
interrupt CSS_ 0xFFF6 Clock Security System Interrupt
interrupt SPI_ 0xFFF4 SPI Peripheral Interrupts
interrupt TIMER_A 0xFFF2 TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFEE TIMER B Peripheral Interrupts
interrupt I_C 0xFFE4 IC Peripheral Interrupt
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei1 sensitivity 1
MISCR1.IS10 6 ei1 sensitivity 0
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei0 sensitivity 1
MISCR1.IS00 3 ei0 sensitivity 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.MOD 3 SPI Master Output Disable
MISCR2.SOD 2 SPI Slave Output Disable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72216G1
; :ST72216G1 :ST72216G1B1 :ST72216G1B3 :ST72216G1B5 :ST72216G1B6 :ST72216G1B7 \
; :ST72216G1M1 :ST72216G1M3 :ST72216G1M5 :ST72216G1M6 :ST72216G1M7 \
; :ST72C216G1 :ST72C216G1B1 :ST72C216G1B3 :ST72C216G1B5 :ST72C216G1B6 \
; :ST72C216G1B7 :ST72C216G1M1 :ST72C216G1M3 :ST72C216G1M5 :ST72C216G1M6 \
; :ST72C216G1M7
; http://us.st.com/stonline/books/pdf/docs/6815.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0040
area BSS RESERVED 0x0040:0x0070
area DATA FSR_2 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt ei0_ 0xFFFA External Interrupt Port A7..0 (C5..0)
interrupt ei1_ 0xFFF8 External Interrupt Port B7..0 (C5..0)
interrupt CSS_ 0xFFF6 Clock Security System Interrupt
interrupt SPI_ 0xFFF4 SPI Peripheral Interrupts
interrupt TIMER_A 0xFFF2 TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFEE TIMER B Peripheral Interrupts
interrupt I_C 0xFFE4 IC Peripheral Interrupt
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei1 sensitivity 1
MISCR1.IS10 6 ei1 sensitivity 0
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei0 sensitivity 1
MISCR1.IS00 3 ei0 sensitivity 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.MOD 3 SPI Master Output Disable
MISCR2.SOD 2 SPI Slave Output Disable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72251
; :ST72251 :ST72251G1 :ST72251G1B1 :ST72251G1B3 :ST72251G1B6 :ST72251G1M1 \
; :ST72251G1M3 :ST72251G1M6 :ST72251G2 :ST72251G2B1 :ST72251G2B3 :ST72251G2B6 \
; :ST72251G2M1 :ST72251G2M3 :ST72251G2M6 :ST72T251G1 :ST72T251G1B3 :ST72T251G1B6 \
; :ST72T251G1M3 :ST72T251G1M6 :ST72T251G2 :ST72T251G2B3 :ST72T251G2B6 \
; :ST72T251G2M3 :ST72T251G2M6
; http://us.st.com/stonline/books/pdf/docs/5277.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0050
area BSS RESERVED 0x0050:0x0070
area DATA FSR_3 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt EI0_ 0xFFFA External Interrupt Vector EI0
interrupt EI1_ 0xFFF8 External Interrupt Vector EI1
interrupt SPI_ 0xFFF4 SPI Interrupt Vector
interrupt TIMER_A 0xFFF2 TIMER A Interrupt Vector
interrupt TIMER_B 0xFFEE TIMER B Interrupt Vector
interrupt I2C_ 0xFFE4 I2C Interrupt Vector
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR 0x0020 Miscellaneous Register
MISCR.PEI3 7 External Interrupt EI1 Polarity Option 3
MISCR.PEI2 6 External Interrupt EI1 Polarity Option 2
MISCR.MCO 5 Main Clock Out
MISCR.PEI1 4 External Interrupt EI0 Polarity Option 1
MISCR.PEI0 3 External Interrupt EI0 Polarity Option 0
MISCR.SMS 0 Slow Mode Select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
I2CCR 0x0028 I2C Control Register
I2CCR.PE 5 Peripheral enable
I2CCR.ENGC 4 Enable General Call
I2CCR.START 3 Generation of a Start condition
I2CCR.ACK 2 Acknowledge enable
I2CCR.STOP 1 Generation of a Stop condition
I2CCR.ITE 0 Interrupt enable
I2CSR1 0x0029 I2C Status Register 1
I2CSR1.EVF 7 Event flag
I2CSR1.ADD10 6 10-bit addressing in Master mode
I2CSR1.TRA 5 Transmitter/Receiver
I2CSR1.BUSY 4 Bus busy
I2CSR1.BTF 3 Byte transfer finished
I2CSR1.ADSL 2 Address matched (Slave mode)
I2CSR1.M_SL 1 Master/Slave
I2CSR1.SB 0 Start bit (Master mode)
I2CSR2 0x002A I2C Status Register 2
I2CSR2.AF 4 Acknowledge failure
I2CSR2.STOPF 3 Stop detection (Slave mode)
I2CSR2.ARLO 2 Arbitration lost
I2CSR2.BERR 1 Bus error
I2CSR2.GCAL 0 General Call (Slave mode)
I2CCCR 0x002B I2C Clock Control Register
I2CCCR.FM_SM 7 Fast/Standard I2C mode
I2CCCR.CC6 6 clock divider bit 6
I2CCCR.CC5 5 clock divider bit 5
I2CCCR.CC4 4 clock divider bit 4
I2CCCR.CC3 3 clock divider bit 3
I2CCCR.CC2 2 clock divider bit 2
I2CCCR.CC1 1 clock divider bit 1
I2CCCR.CC0 0 clock divider bit 0
I2COAR1 0x002C I2C Own Address Register 1
I2COAR1.ADD7 7 Interface addres 7
I2COAR1.ADD6 6 Interface addres 6
I2COAR1.ADD5 5 Interface addres 5
I2COAR1.ADD4 4 Interface addres 4
I2COAR1.ADD3 3 Interface addres 3
I2COAR1.ADD2 2 Interface addres 2
I2COAR1.ADD1 1 Interface addres 1
I2COAR1.ADD0 0 Interface addres 0
I2COAR2 0x002D I2C Own Address Register 2
I2COAR2.FR1 7 Frequency bit 1
I2COAR2.FR0 6 Frequency bit 0
I2COAR2.ADD9 2 Interface addres 9
I2COAR2.ADD8 1 Interface addres 8
I2CDR 0x002E I2C Data Register
I2CDR.D7 7 I2C Data Register bit 7
I2CDR.D6 6 I2C Data Register bit 6
I2CDR.D5 5 I2C Data Register bit 5
I2CDR.D4 4 I2C Data Register bit 4
I2CDR.D3 3 I2C Data Register bit 3
I2CDR.D2 2 I2C Data Register bit 2
I2CDR.D1 1 I2C Data Register bit 1
I2CDR.D0 0 I2C Data Register bit 0
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
RESERVED0040 0x0040 RESERVED
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.AD7 7 Analog Converted Value 7
ADCDR.AD6 6 Analog Converted Value 6
ADCDR.AD5 5 Analog Converted Value 5
ADCDR.AD4 4 Analog Converted Value 4
ADCDR.AD3 3 Analog Converted Value 3
ADCDR.AD2 2 Analog Converted Value 2
ADCDR.AD1 1 Analog Converted Value 1
ADCDR.AD0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72254G1
; :ST72254G1 :ST72254G1B1 :ST72254G1B3 :ST72254G1B5 :ST72254G1B6 :ST72254G1B7 \
; :ST72254G1M1 :ST72254G1M3 :ST72254G1M5 :ST72254G1M6 :ST72254G1M7
; :T72C254G1 :ST72C254G1B1 :ST72C254G1B3 :ST72C254G1B5 :ST72C254G1B6 \
; :ST72C254G1B7 :ST72C254G1M1 :ST72C254G1M3 :ST72C254G1M5 :ST72C254G1M6 \
; :ST72C254G1M7
; http://us.st.com/stonline/books/pdf/docs/6815.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0050
area BSS RESERVED 0x0050:0x0070
area DATA FSR_3 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt ei0_ 0xFFFA External Interrupt Port A7..0 (C5..0)
interrupt ei1_ 0xFFF8 External Interrupt Port B7..0 (C5..0)
interrupt CSS_ 0xFFF6 Clock Security System Interrupt
interrupt SPI_ 0xFFF4 SPI Peripheral Interrupts
interrupt TIMER_A 0xFFF2 TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFEE TIMER B Peripheral Interrupts
interrupt I_C 0xFFE4 IC Peripheral Interrupt
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei1 sensitivity 1
MISCR1.IS10 6 ei1 sensitivity 0
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei0 sensitivity 1
MISCR1.IS00 3 ei0 sensitivity 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
I2CCR 0x0028 I2C Control Register
I2CCR.PE 5 Peripheral enable
I2CCR.ENGC 4 Enable General Call
I2CCR.START 3 Generation of a Start condition
I2CCR.ACK 2 Acknowledge enable
I2CCR.STOP 1 Generation of a Stop condition
I2CCR.ITE 0 Interrupt enable
I2CSR1 0x0029 I2C Status Register 1
I2CSR1.EVF 7 Event flag
I2CSR1.ADD10 6 10-bit addressing in Master mode
I2CSR1.TRA 5 Transmitter/Receiver
I2CSR1.BUSY 4 Bus busy
I2CSR1.BTF 3 Byte transfer finished
I2CSR1.ADSL 2 Address matched (Slave mode)
I2CSR1.M_SL 1 Master/Slave
I2CSR1.SB 0 Start bit (Master mode)
I2CSR2 0x002A I2C Status Register 2
I2CSR2.AF 4 Acknowledge failure
I2CSR2.STOPF 3 Stop detection (Slave mode)
I2CSR2.ARLO 2 Arbitration lost
I2CSR2.BERR 1 Bus error
I2CSR2.GCAL 0 General Call (Slave mode)
I2CCCR 0x002B I2C Clock Control Register
I2CCCR.FM_SM 7 Fast/Standard I2C mode
I2CCCR.CC6 6 clock divider bit 6
I2CCCR.CC5 5 clock divider bit 5
I2CCCR.CC4 4 clock divider bit 4
I2CCCR.CC3 3 clock divider bit 3
I2CCCR.CC2 2 clock divider bit 2
I2CCCR.CC1 1 clock divider bit 1
I2CCCR.CC0 0 clock divider bit 0
I2COAR1 0x002C I2C Own Address Register 1
I2COAR1.ADD7 7 Interface addres 7
I2COAR1.ADD6 6 Interface addres 6
I2COAR1.ADD5 5 Interface addres 5
I2COAR1.ADD4 4 Interface addres 4
I2COAR1.ADD3 3 Interface addres 3
I2COAR1.ADD2 2 Interface addres 2
I2COAR1.ADD1 1 Interface addres 1
I2COAR1.ADD0 0 Interface addres 0
I2COAR2 0x002D I2C Own Address Register 2
I2COAR2.FR1 7 Frequency bit 1
I2COAR2.FR0 6 Frequency bit 0
I2COAR2.ADD9 2 Interface addres 9
I2COAR2.ADD8 1 Interface addres 8
I2CDR 0x002E I2C Data Register
I2CDR.D7 7 I2C Data Register bit 7
I2CDR.D6 6 I2C Data Register bit 6
I2CDR.D5 5 I2C Data Register bit 5
I2CDR.D4 4 I2C Data Register bit 4
I2CDR.D3 3 I2C Data Register bit 3
I2CDR.D2 2 I2C Data Register bit 2
I2CDR.D1 1 I2C Data Register bit 1
I2CDR.D0 0 I2C Data Register bit 0
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.MOD 3 SPI Master Output Disable
MISCR2.SOD 2 SPI Slave Output Disable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72254G2
; :ST72254G2 :ST72254G2B1 :ST72254G2B3 :ST72254G2B5 :ST72254G2B6 :ST72254G2B7 \
; :ST72254G2M1 :ST72254G2M3 :ST72254G2M5 :ST72254G2M6 :ST72254G2M7 \
; :ST72C254G2 :ST72C254G2B1 :ST72C254G2B3 :ST72C254G2B5 :ST72C254G2B6 \
; :ST72C254G2B7 :ST72C254G2D0 :ST72C254G2E0 :ST72C254G2M1 :ST72C254G2M3 \
; :ST72C254G2M5 :ST72C254G2M6 :ST72C254G2M6/TR :ST72C254G2M7
; http://us.st.com/stonline/books/pdf/docs/6815.pdf
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0050
area BSS RESERVED 0x0050:0x0070
area DATA FSR_2 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0180
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt ei0_ 0xFFFA External Interrupt Port A7..0 (C5..0)
interrupt ei1_ 0xFFF8 External Interrupt Port B7..0 (C5..0)
interrupt CSS_ 0xFFF6 Clock Security System Interrupt
interrupt SPI_ 0xFFF4 SPI Peripheral Interrupts
interrupt TIMER_A 0xFFF2 TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFEE TIMER B Peripheral Interrupts
interrupt I_C 0xFFE4 IC Peripheral Interrupt
; INPUT/OUTPUT PORTS
PCDR 0x0000 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0001 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0002 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PADR 0x0008 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0009 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x000A Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei1 sensitivity 1
MISCR1.IS10 6 ei1 sensitivity 0
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei0 sensitivity 1
MISCR1.IS00 3 ei0 sensitivity 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
I2CCR 0x0028 I2C Control Register
I2CCR.PE 5 Peripheral enable
I2CCR.ENGC 4 Enable General Call
I2CCR.START 3 Generation of a Start condition
I2CCR.ACK 2 Acknowledge enable
I2CCR.STOP 1 Generation of a Stop condition
I2CCR.ITE 0 Interrupt enable
I2CSR1 0x0029 I2C Status Register 1
I2CSR1.EVF 7 Event flag
I2CSR1.ADD10 6 10-bit addressing in Master mode
I2CSR1.TRA 5 Transmitter/Receiver
I2CSR1.BUSY 4 Bus busy
I2CSR1.BTF 3 Byte transfer finished
I2CSR1.ADSL 2 Address matched (Slave mode)
I2CSR1.M_SL 1 Master/Slave
I2CSR1.SB 0 Start bit (Master mode)
I2CSR2 0x002A I2C Status Register 2
I2CSR2.AF 4 Acknowledge failure
I2CSR2.STOPF 3 Stop detection (Slave mode)
I2CSR2.ARLO 2 Arbitration lost
I2CSR2.BERR 1 Bus error
I2CSR2.GCAL 0 General Call (Slave mode)
I2CCCR 0x002B I2C Clock Control Register
I2CCCR.FM_SM 7 Fast/Standard I2C mode
I2CCCR.CC6 6 clock divider bit 6
I2CCCR.CC5 5 clock divider bit 5
I2CCCR.CC4 4 clock divider bit 4
I2CCCR.CC3 3 clock divider bit 3
I2CCCR.CC2 2 clock divider bit 2
I2CCCR.CC1 1 clock divider bit 1
I2CCCR.CC0 0 clock divider bit 0
I2COAR1 0x002C I2C Own Address Register 1
I2COAR1.ADD7 7 Interface addres 7
I2COAR1.ADD6 6 Interface addres 6
I2COAR1.ADD5 5 Interface addres 5
I2COAR1.ADD4 4 Interface addres 4
I2COAR1.ADD3 3 Interface addres 3
I2COAR1.ADD2 2 Interface addres 2
I2COAR1.ADD1 1 Interface addres 1
I2COAR1.ADD0 0 Interface addres 0
I2COAR2 0x002D I2C Own Address Register 2
I2COAR2.FR1 7 Frequency bit 1
I2COAR2.FR0 6 Frequency bit 0
I2COAR2.ADD9 2 Interface addres 9
I2COAR2.ADD8 1 Interface addres 8
I2CDR 0x002E I2C Data Register
I2CDR.D7 7 I2C Data Register bit 7
I2CDR.D6 6 I2C Data Register bit 6
I2CDR.D5 5 I2C Data Register bit 5
I2CDR.D4 4 I2C Data Register bit 4
I2CDR.D3 3 I2C Data Register bit 3
I2CDR.D2 2 I2C Data Register bit 2
I2CDR.D1 1 I2C Data Register bit 1
I2CDR.D0 0 I2C Data Register bit 0
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.MOD 3 SPI Master Output Disable
MISCR2.SOD 2 SPI Slave Output Disable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72260G1
; :ST72260G1
; http://us.st.com/stonline/books/pdf/docs/8347.pdf
.ST72262G1
; :ST72262G1
; http://us.st.com/stonline/books/pdf/docs/8347.pdf
.ST72262G2
; :ST72262G2
; http://us.st.com/stonline/books/pdf/docs/8347.pdf
.ST72264G1
; :ST72264G1
; http://us.st.com/stonline/books/pdf/docs/8347.pdf
; MEMORY MAP
; Interrupt and reset vector assignments
; INPUT/OUTPUT PORTS
.ST72264G2
; :ST72264G2 :ST72264G2B6 :ST72264G2M6 :ST72F264G2B6 :ST72F264G2M6
; http://us.st.com/stonline/books/pdf/docs/8347.pdf
.ST72311
; :ST72311 :ST72311J2 :ST72311J4 :ST72311N2 :ST72311N4 :ST72T311J2B6 \
; :ST72T311J2B6S :ST72T311J2T6 :ST72T311J2T6S :ST72T311J4B3 :ST72T311J4B3S \
; :ST72T311J4B6 :ST72T311J4B6S :ST72T311J4T3 :ST72T311J4T3S :ST72T311J4T6 \
; :ST72T311J4T6S :ST72T311N2B6 :ST72T311N2B6S :ST72T311N2T6 :ST72T311N2T6S \
; :ST72T311N4 :ST72T311N4B6 :ST72T311N4B6S :ST72T311N4T3 :ST72T311N4T3S \
; :ST72T311N4T6 :ST72T311N4T6S
; http://us.st.com/stonline/books/pdf/docs/5834.pdf
; MEMORY MAP
; ST72T311J4, ST72T311N4
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_2 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0280
area BSS RESERVED 0x0280:0xC000
; ST72T311J2, ST72T311N2
; area DATA FSR_1 0x0000:0x0058
; area BSS RESERVED 0x0058:0x0070
; area DATA FSR_2 0x0070:0x0072
; area BSS RESERVED 0x0072:0x0080
; area DATA RAM_ 0x0080:0x0200
; area BSS RESERVED 0x0200:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt EI0_ 0xFFF6 External Interrupt Vector EI0
interrupt EI1_ 0xFFF4 External Interrupt Vector EI1
interrupt EI2_ 0xFFF2 External Interrupt Vector EI2
interrupt EI3_ 0xFFF0 External Interrupt Vector EI3
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt TIMER_A 0xFFEA TIMER A Interrupt Vector
interrupt TIMER_B 0xFFE8 TIMER B Interrupt Vector
interrupt SCI_ 0xFFE6 SCI Interrupt Vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR 0x0020 Miscellaneous Register
MISCR.PEI3 7 External Interrupt EI3 Polarity Option
MISCR.PEI2 6 External Interrupt EI2 Polarity Option
MISCR.MCO 5 Main Clock Out
MISCR.PEI1 4 External Interrupt EI1 Polarity Option
MISCR.PEI0 3 External Interrupt EI0 Polarity Option
MISCR.PSM1 2 Prescaler for Slow Mode 1
MISCR.PSM0 1 Prescaler for Slow Mode 0
MISCR.SMS 0 Slow Mode Select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
RESERVED0040 0x0040 RESERVED
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72311R6
; :ST72311R6 :ST72T311R6 :ST72T311R6T6 :ST72T311R6T6S :ST72T311R6T7
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=1024
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0480
area BSS RESERVED 0x0480:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
RESERVED0060 0x0060 RESERVED
RESERVED0061 0x0061 RESERVED
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
RESERVED006D 0x006D RESERVED
RESERVED006E 0x006E RESERVED
RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
PWMDCR3 0x0072 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0073 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0074 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72311R7
; :ST72311R7 :ST72T311R6T7 :ST72T311R7 :ST72T311R7T6S
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=1536
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0680
area BSS RESERVED 0x0680:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
RESERVED0060 0x0060 RESERVED
RESERVED0061 0x0061 RESERVED
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
RESERVED006D 0x006D RESERVED
RESERVED006E 0x006E RESERVED
RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
PWMDCR3 0x0072 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0073 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0074 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72311R9
; :ST72311R9 :ST72311R9T6 :ST72T311R9 :ST72T311R9Q6 :ST72T311R9T6 :ST72T311R9T6S
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=2048
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0880
area BSS RESERVED 0x0880:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
RESERVED0060 0x0060 RESERVED
RESERVED0061 0x0061 RESERVED
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
RESERVED006D 0x006D RESERVED
RESERVED006E 0x006E RESERVED
RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
PWMDCR3 0x0072 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0073 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0074 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72314J2
; :ST72314J2 :ST72C314J2 :ST72C314J2B6 :ST72C314J2T6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=384
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0200
area BSS RESERVED 0x0200:0x0C00
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72314J4
; :ST72314J4 :ST72C314J4 :ST72C314J4B6 :ST72C314J4T6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=512
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0280
area BSS RESERVED 0x0280:0x0C00
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72314N2
; :ST72314N2 :ST72C314N2
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=384
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0200
area BSS RESERVED 0x0200:0x0C00
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72314N4
; :ST72314N4 :ST72C314N4 :ST72C314N4B6 :ST72C314N4T6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=512
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0280
area BSS RESERVED 0x0280:0x0C00
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72321AR6
; :ST72321AR6 :ST72F321AR6
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321AR7
; :ST72321AR7 :ST72F321AR7
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321AR9
; :ST72321AR9 :ST72F321AR9
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321J7
; :ST72321J7 :ST72321J7T6 :ST72F321J7
; http://us.st.com/stonline/books/pdf/docs/7600.pdf
.ST72321J9
; :ST72321J9 :ST72F321J9 :ST72F321J9T3
; http://us.st.com/stonline/books/pdf/docs/7600.pdf
.ST72321M7
; :ST72321M7 :ST72F321M7
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321M9
; :ST72321M9 :ST72F321M9
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321R6
; :ST72321R6 :ST72F321R6
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321R7
; :ST72321R7 :ST72F321R7
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72321R9
; :ST72321R9 :ST72F321R9
; http://us.st.com/stonline/books/pdf/docs/7599.pdf
.ST72324J2
; :ST72324J2 :ST72324J2B6 :ST72324J2T3 :ST72F324J2
; http://us.st.com/stonline/books/pdf/docs/8336.pdf
.ST72324J4
; :ST72324J4 :ST72324J4B6 :ST72F324J4
; http://us.st.com/stonline/books/pdf/docs/8336.pdf
.ST72324J6
; :ST72324J6 :ST72F324J6 :ST72F324J6T6
; http://us.st.com/stonline/books/pdf/docs/8336.pdf
.ST72324K2
; :ST72324K2 :ST72324K2B3 :ST72324K2T3 :ST72F324K2
; http://us.st.com/stonline/books/pdf/docs/8336.pdf
.ST72324K4
; :ST72324K4 :ST72324K4B6 :ST72F324K4
; http://us.st.com/stonline/books/pdf/docs/8336.pdf
.ST72324K6
; :ST72324K6 :ST72F324K6 :ST72F324K6T6
; http://us.st.com/stonline/books/pdf/docs/8336.pdf
.ST72331
; :ST72331 :ST72331J2 :ST72331J4 :ST72331N2 :ST72331N4 :ST72T331J2 :ST72T331J2B6 \
; :ST72T331J2B6S :ST72T331J2T6 :ST72T331J2T6S :ST72T331J4 :ST72T331J4B6 \
; :ST72T331J4B6S :ST72T331J4T3 :ST72T331J4T3S :ST72T331J4T6 :ST72T331J4T6S \
; :ST72T331N2 :ST72T331N2B6 :ST72T331N2B6S :ST72T331N2T6 :ST72T331N2T6S \
; :ST72T331N4 :ST72T331N4B6 :ST72T331N4B6S :ST72T331N4T3 :ST72T331N4T3S \
; :ST72T331N4T6 :ST72T331N4T6S
; http://us.st.com/stonline/books/pdf/docs/5841.pdf
.ST72334J2
; :ST72334J2 :ST72334J2T6 :ST72C334J2 :ST72C334J2B6 :ST72C334J2T6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=384
; EEPROM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0200
area BSS RESERVED 0x0200:0x0C00
area DATA EEPROM_ 0x0C00:0x0D00
area BSS RESERVED 0x0D00:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72334J4
; :ST72334J4 :ST72334J4B6 :ST72C334J4 :ST72C334J4B6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=512
; EEPROM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0280
area BSS RESERVED 0x0280:0x0C00
area DATA EEPROM_ 0x0C00:0x0D00
area BSS RESERVED 0x0D00:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72334N2
; :ST72334N2 :ST72C334N2
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=384
; EEPROM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0200
area BSS RESERVED 0x0200:0x0C00
area DATA EEPROM_ 0x0C00:0x0D00
area BSS RESERVED 0x0D00:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72334N4
; :ST72334N4 :ST72C334N4 :ST72C334N4B6 :ST72C334N4T6
; http://us.st.com/stonline/books/pdf/docs/6816.pdf
; RAM=512
; EEPROM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0058
area BSS RESERVED 0x0058:0x0070
area DATA FSR_1 0x0070:0x0072
area BSS RESERVED 0x0072:0x0080
area DATA RAM_ 0x0080:0x0280
area BSS RESERVED 0x0280:0x0C00
area DATA EEPROM_ 0x0C00:0x0D00
area BSS RESERVED 0x0D00:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt MCC_RTC_CSS 0xFFF8 Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 Data EEPROM Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei3 sensitivity
MISCR1.IS10 6 ei2 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS01 4 ei1 sensitivity
MISCR1.IS00 3 ei0 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
RESERVED0024 0x0024 RESERVED
RESERVED0025 0x0025 RESERVED
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x002B Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
EECSR 0x002C Data-EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer A Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer A Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer A Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer A Input Capture 1 High Register
TBIC1LR 0x0045 Timer A Input Capture 1 Low Register
TBOC1HR 0x0046 Timer A Output Compare 1 High Register
TBOC1LR 0x0047 Timer A Output Compare 1 Low Register
TBCHR 0x0048 Timer A Counter High Register
TBCLR 0x0049 Timer A Counter Low Register
TBACHR 0x004A Timer A Alternate Counter High Register
TBACLR 0x004B Timer A Alternate Counter Low Register
TBIC2HR 0x004C Timer A Input Capture 2 High Register
TBIC2LR 0x004D Timer A Input Capture 2 Low Register
TBOC2HR 0x004E Timer A Output Compare 2 High Register
TBOC2LR 0x004F Timer A Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler DIVISION Register
SCIERPR.ERPR7 7 Extended Receive Prescaler DIVISION Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler DIVISION Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler DIVISION Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler DIVISION Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler DIVISION Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler DIVISION Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler DIVISION Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler DIVISION Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler DIVISION Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler DIVISION Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler DIVISION Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler DIVISION Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler DIVISION Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler DIVISION Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler DIVISION Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler DIVISION Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler DIVISION Register bit 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72389BW
; :ST72389BW :ST72389BW4
; http://us.st.com/stonline/books/pdf/docs/7517.pdf
; RAM=512
; MEMORY MAP
area DATA FSR_1 0x0000:0x000F
area BSS RESERVED 0x000F:0x001C
area DATA FSR_2 0x001C:0x0059
area BSS RESERVED 0x0059:0x0080
area DATA RAM_ 0x0080:0x0280
area DATA LCD_RAM 0x0280:0x04BC
area BSS RESERVED 0x04BC:0xA000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) interrupt vector
interrupt NMI_ 0xFFFA Non maskable external interrupt vector
interrupt EI1_ 0xFFF8 External interrupt vector (port A3..0)
interrupt EI2_ 0xFFF6 External interrupt vector (port A7..4)
interrupt EI3_ 0xFFF4 External interrupt vector (port B)
interrupt EI4_ 0xFFF2 External interrupt vector (port C)
interrupt EI5_ 0xFFF0 External interrupt vector (port D)
interrupt MCC_ 0xFFEE MCC interrupt vector
interrupt ACC_ 0xFFEC ACC interrupt vector
interrupt SPI_ 0xFFE8 SPI interrupt vector
interrupt TIMER_A 0xFFE6 TIMER A interrupt vector
interrupt TIMER_B 0xFFE4 TIMER B interrupt vector
interrupt SCI_ 0xFFE2 SCI interrupt vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PCDR 0x0008 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0009 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x000A Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED000B 0x000B RESERVED
PDDR 0x000C Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x000D Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
PDOR 0x000E Port D Option Register
PDOR.O7 7 Port C Option Register bit 7
PDOR.O6 6 Port C Option Register bit 6
PDOR.O5 5 Port C Option Register bit 5
PDOR.O4 4 Port C Option Register bit 4
PDOR.O3 3 Port C Option Register bit 3
PDOR.O2 2 Port C Option Register bit 2
PDOR.O1 1 Port C Option Register bit 1
PDOR.O0 0 Port C Option Register bit 0
ISPR0 0x001C Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR0.I1_0 1
ISPR0.I0_0 0
ISPR1 0x001D Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x001E Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x001F Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7
MISCR1.IS10 6
MISCR1.IS21 5
MISCR1.IS20 4
MISCR1.NMIS 1 NMI Sensitivity
MISCR1.NMIE 0 NMI Enable
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED0025 0x0025 RESERVED
MCCSR 0x0026 Main Clock Control / Status Register
MCCSR.SMS 7 Slow mode select
MCCSR.CP1 6 CPU clock prescaler
MCCSR.CP0 5 CPU clock prescaler
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
ACCSR 0x0027 Auxiliary Clock Control / Status Register
ACCSR.OE 2 Oscillator enable
ACCSR.OIE 1 Oscillator interrupt enable
ACCSR.OIF 0 Oscillator interrupt flag
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.ACO 7 Auxiliary clock-out control
MISCR2.MCO 6 Main clock-out control
MISCR2.BC1 5 Beep Control 1
MISCR2.BC0 4 Beep Control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
LCDCR 0x0058 LCD Control Register
LCDCR.DCS 7 Duty cycle selection
LCDCR.CD1 5 Clock divider 1
LCDCR.CD0 4 Clock divider 0
LCDCR.LCDE 3 LCD enable
LCDCR.CLKS 2 Clock selection
LCDCR.FS1 1 Frame Frequency selection 1
LCDCR.FS0 0 Frame Frequency selection 0
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
.ST72511R6
; :ST72511R6 :ST72T511R6 :ST72T511R6T6 :ST72T511R6T6S
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=1024
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0480
area BSS RESERVED 0x0480:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
CANISR 0x005A CAN Interrupt Status Register
CANISR.RXIF3 7 Receive Interrupt Flag for Buffer 3
CANISR.RXIF2 6 Receive Interrupt Flag for Buffer 2
CANISR.RXIF1 5 Receive Interrupt Flag for Buffer 1
CANISR.TXIF 4 Transmit Interrupt Flag
CANISR.SCIF 3 Status Change Interrupt Flag
CANISR.ORIF 2 Overrun Interrupt Flag
CANISR.TEIF 1 Transmit Error Interrupt Flag
CANISR.EPND 0 Error Interrupt Pending
CANICR 0x005B CAN Interrupt Control Register
CANICR.ESCI 6 Extended Status Change Interrupt
CANICR.RXIE 5 Receive Interrupt Enable
CANICR.TXIE 4 Transmit Interrupt Enable
CANICR.SCIE 3 Status Change Interrupt Enable
CANICR.ORIE 2 Overrun Interrupt Enable
CANICR.TEIE 1 Transmit Error Interrupt Enable
CANICR.ETX 0 Early Transmit Interrupt
CANCSR 0x005C CAN Control / Status Register
CANCSR.BOFF 6 Bus-Off State
CANCSR.EPSV 5 Error Passive State
CANCSR.SRTE 4 Simultaneous Receive/Transmit Enable
CANCSR.NRTX 3 No Retransmission
CANCSR.FSYN 2 Fast Synchronization
CANCSR.WKPS 1 Wake-up Pulse
CANCSR.RUN 0 CAN Enable
CANBRPR 0x005D CAN Baud Rate Prescaler Register
CANBRPR.RJW1 7
CANBRPR.RJW0 6
CANBRPR.BRP5 5
CANBRPR.BRP4 4
CANBRPR.BRP3 3
CANBRPR.BRP2 2
CANBRPR.BRP1 1
CANBRPR.BRP0 0
CANBTR 0x005E CAN Bit Timing Register
CANBTR.BS22 6
CANBTR.BS21 5
CANBTR.BS20 4
CANBTR.BS13 3
CANBTR.BS12 2
CANBTR.BS11 1
CANBTR.BS10 0
CANPSR 0x005F CAN Page Selection Register
CANPSR.PAGE2 2
CANPSR.PAGE1 1
CANPSR.PAGE0 0
; CAN PAGE 0
CANLIDHR 0x0060 CAN LAST IDENTIFIER HIGH REGISTER
CANLIDHR.LID10 7
CANLIDHR.LID9 6
CANLIDHR.LID8 5
CANLIDHR.LID7 4
CANLIDHR.LID6 3
CANLIDHR.LID5 2
CANLIDHR.LID4 1
CANLIDHR.LID3 0
CANLIDLR 0x0061 CAN LAST IDENTIFIER LOW REGISTER
CANLIDLR.LID2 7
CANLIDLR.LID1 6
CANLIDLR.LID0 5
CANLIDLR.LRTR 4
CANLIDLR.LDLC3 3
CANLIDLR.LDLC2 2
CANLIDLR.LDLC1 1
CANLIDLR.LDLC0 0
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
CANTSTR 0x006D CAN TSTR
CANTECR 0x006E CAN TRANSMIT ERROR COUNTER REGISTER
CANTECR.TEC7 7
CANTECR.TEC6 6
CANTECR.TEC5 5
CANTECR.TEC4 4
CANTECR.TEC3 3
CANTECR.TEC2 2
CANTECR.TEC1 1
CANTECR.TEC0 0
CANRECR 0x006F CAN RECEIVE ERROR COUNTER REGISTER
CANRECR.REC7 7
CANRECR.REC6 6
CANRECR.REC5 5
CANRECR.REC4 4
CANRECR.REC3 3
CANRECR.REC2 2
CANRECR.REC1 1
CANRECR.REC0 0
; CAN PAGE 1
; CANIDHR1 0x0060 CAN IDENTIFIER HIGH REGISTER 1
; CANIDHR1.ID10 7
; CANIDHR1.ID9 6
; CANIDHR1.ID8 5
; CANIDHR1.ID7 4
; CANIDHR1.ID6 3
; CANIDHR1.ID5 2
; CANIDHR1.ID4 1
; CANIDHR1.ID3 0
; CANIDLR1 0x0061 CAN IDENTIFIER LOW REGISTER 1
; CANIDLR1.ID2 7
; CANIDLR1.ID1 6
; CANIDLR1.ID0 5
; CANIDLR1.RTR 4
; CANIDLR1.DLC3 3
; CANIDLR1.DLC2 2
; CANIDLR1.DLC1 1
; CANIDLR1.DLC0 0
; CANDATA01 0x0062 CAN DATA REGISTER 01
; CANDATA01.DATA7 7
; CANDATA01.DATA6 6
; CANDATA01.DATA5 5
; CANDATA01.DATA4 4
; CANDATA01.DATA3 3
; CANDATA01.DATA2 2
; CANDATA01.DATA1 1
; CANDATA01.DATA0 0
; CANDATA11 0x0063 CAN DATA REGISTER 11
; CANDATA11.DATA7 7
; CANDATA11.DATA6 6
; CANDATA11.DATA5 5
; CANDATA11.DATA4 4
; CANDATA11.DATA3 3
; CANDATA11.DATA2 2
; CANDATA11.DATA1 1
; CANDATA11.DATA0 0
; CANDATA21 0x0064 CAN DATA REGISTER 21
; CANDATA21.DATA7 7
; CANDATA21.DATA6 6
; CANDATA21.DATA5 5
; CANDATA21.DATA4 4
; CANDATA21.DATA3 3
; CANDATA21.DATA2 2
; CANDATA21.DATA1 1
; CANDATA21.DATA0 0
; CANDATA31 0x0065 CAN DATA REGISTER 31
; CANDATA31.DATA7 7
; CANDATA31.DATA6 6
; CANDATA31.DATA5 5
; CANDATA31.DATA4 4
; CANDATA31.DATA3 3
; CANDATA31.DATA2 2
; CANDATA31.DATA1 1
; CANDATA31.DATA0 0
; CANDATA41 0x0066 CAN DATA REGISTER 41
; CANDATA41.DATA7 7
; CANDATA41.DATA6 6
; CANDATA41.DATA5 5
; CANDATA41.DATA4 4
; CANDATA41.DATA3 3
; CANDATA41.DATA2 2
; CANDATA41.DATA1 1
; CANDATA41.DATA0 0
; CANDATA51 0x0067 CAN DATA REGISTER 51
; CANDATA51.DATA7 7
; CANDATA51.DATA6 6
; CANDATA51.DATA5 5
; CANDATA51.DATA4 4
; CANDATA51.DATA3 3
; CANDATA51.DATA2 2
; CANDATA51.DATA1 1
; CANDATA51.DATA0 0
; CANDATA61 0x0068 CAN DATA REGISTER 61
; CANDATA61.DATA7 7
; CANDATA61.DATA6 6
; CANDATA61.DATA5 5
; CANDATA61.DATA4 4
; CANDATA61.DATA3 3
; CANDATA61.DATA2 2
; CANDATA61.DATA1 1
; CANDATA61.DATA0 0
; CANDATA71 0x0069 CAN DATA REGISTER 71
; CANDATA71.DATA7 7
; CANDATA71.DATA6 6
; CANDATA71.DATA5 5
; CANDATA71.DATA4 4
; CANDATA71.DATA3 3
; CANDATA71.DATA2 2
; CANDATA71.DATA1 1
; CANDATA71.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR1 0x006F CAN BUFFER CONTROL/STATUS REGISTER 1
; CANBCSR1.ACC 3 Acceptance Code
; CANBCSR1.RDY 2 Message Ready
; CANBCSR1.BUSY 1 Busy Buffer
; CANBCSR1.LOCK 0 Lock Buffer
; CAN PAGE 2
; CANIDHR2 0x0060 CAN IDENTIFIER HIGH REGISTER 2
; CANIDHR2.ID10 7
; CANIDHR2.ID9 6
; CANIDHR2.ID8 5
; CANIDHR2.ID7 4
; CANIDHR2.ID6 3
; CANIDHR2.ID5 2
; CANIDHR2.ID4 1
; CANIDHR2.ID3 0
; CANIDLR2 0x0061 CAN IDENTIFIER LOW REGISTER 2
; CANIDLR2.ID2 7
; CANIDLR2.ID1 6
; CANIDLR2.ID0 5
; CANIDLR2.RTR 4
; CANIDLR2.DLC3 3
; CANIDLR2.DLC2 2
; CANIDLR2.DLC1 1
; CANIDLR2.DLC0 0
; CANDATA02 0x0062 CAN DATA REGISTER 02
; CANDATA02.DATA7 7
; CANDATA02.DATA6 6
; CANDATA02.DATA5 5
; CANDATA02.DATA4 4
; CANDATA02.DATA3 3
; CANDATA02.DATA2 2
; CANDATA02.DATA1 1
; CANDATA02.DATA0 0
; CANDATA12 0x0063 CAN DATA REGISTER 12
; CANDATA12.DATA7 7
; CANDATA12.DATA6 6
; CANDATA12.DATA5 5
; CANDATA12.DATA4 4
; CANDATA12.DATA3 3
; CANDATA12.DATA2 2
; CANDATA12.DATA1 1
; CANDATA12.DATA0 0
; CANDATA22 0x0064 CAN DATA REGISTER 22
; CANDATA22.DATA7 7
; CANDATA22.DATA6 6
; CANDATA22.DATA5 5
; CANDATA22.DATA4 4
; CANDATA22.DATA3 3
; CANDATA22.DATA2 2
; CANDATA22.DATA1 1
; CANDATA22.DATA0 0
; CANDATA32 0x0065 CAN DATA REGISTER 32
; CANDATA32.DATA7 7
; CANDATA32.DATA6 6
; CANDATA32.DATA5 5
; CANDATA32.DATA4 4
; CANDATA32.DATA3 3
; CANDATA32.DATA2 2
; CANDATA32.DATA1 1
; CANDATA32.DATA0 0
; CANDATA42 0x0066 CAN DATA REGISTER 42
; CANDATA42.DATA7 7
; CANDATA42.DATA6 6
; CANDATA42.DATA5 5
; CANDATA42.DATA4 4
; CANDATA42.DATA3 3
; CANDATA42.DATA2 2
; CANDATA42.DATA1 1
; CANDATA42.DATA0 0
; CANDATA52 0x0067 CAN DATA REGISTER 52
; CANDATA52.DATA7 7
; CANDATA52.DATA6 6
; CANDATA52.DATA5 5
; CANDATA52.DATA4 4
; CANDATA52.DATA3 3
; CANDATA52.DATA2 2
; CANDATA52.DATA1 1
; CANDATA52.DATA0 0
; CANDATA62 0x0068 CAN DATA REGISTER 62
; CANDATA62.DATA7 7
; CANDATA62.DATA6 6
; CANDATA62.DATA5 5
; CANDATA62.DATA4 4
; CANDATA62.DATA3 3
; CANDATA62.DATA2 2
; CANDATA62.DATA1 1
; CANDATA62.DATA0 0
; CANDATA72 0x0069 CAN DATA REGISTER 72
; CANDATA72.DATA7 7
; CANDATA72.DATA6 6
; CANDATA72.DATA5 5
; CANDATA72.DATA4 4
; CANDATA72.DATA3 3
; CANDATA72.DATA2 2
; CANDATA72.DATA1 1
; CANDATA72.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR2 0x006F CAN BUFFER CONTROL/STATUS REGISTER 2
; CANBCSR2.ACC 3 Acceptance Code
; CANBCSR2.RDY 2 Message Ready
; CANBCSR2.BUSY 1 Busy Buffer
; CANBCSR2.LOCK 0 Lock Buffer
; CAN PAGE 3
; CANIDHR3 0x0060 CAN IDENTIFIER HIGH REGISTER 3
; CANIDHR3.ID10 7
; CANIDHR3.ID9 6
; CANIDHR3.ID8 5
; CANIDHR3.ID7 4
; CANIDHR3.ID6 3
; CANIDHR3.ID5 2
; CANIDHR3.ID4 1
; CANIDHR3.ID3 0
; CANIDLR3 0x0061 CAN IDENTIFIER LOW REGISTER 3
; CANIDLR3.ID2 7
; CANIDLR3.ID1 6
; CANIDLR3.ID0 5
; CANIDLR3.RTR 4
; CANIDLR3.DLC3 3
; CANIDLR3.DLC2 2
; CANIDLR3.DLC1 1
; CANIDLR3.DLC0 0
; CANDATA03 0x0062 CAN DATA REGISTER 03
; CANDATA03.DATA7 7
; CANDATA03.DATA6 6
; CANDATA03.DATA5 5
; CANDATA03.DATA4 4
; CANDATA03.DATA3 3
; CANDATA03.DATA2 2
; CANDATA03.DATA1 1
; CANDATA03.DATA0 0
; CANDATA13 0x0063 CAN DATA REGISTER 13
; CANDATA13.DATA7 7
; CANDATA13.DATA6 6
; CANDATA13.DATA5 5
; CANDATA13.DATA4 4
; CANDATA13.DATA3 3
; CANDATA13.DATA2 2
; CANDATA13.DATA1 1
; CANDATA13.DATA0 0
; CANDATA23 0x0064 CAN DATA REGISTER 23
; CANDATA23.DATA7 7
; CANDATA23.DATA6 6
; CANDATA23.DATA5 5
; CANDATA23.DATA4 4
; CANDATA23.DATA3 3
; CANDATA23.DATA2 2
; CANDATA23.DATA1 1
; CANDATA23.DATA0 0
; CANDATA33 0x0065 CAN DATA REGISTER 33
; CANDATA33.DATA7 7
; CANDATA33.DATA6 6
; CANDATA33.DATA5 5
; CANDATA33.DATA4 4
; CANDATA33.DATA3 3
; CANDATA33.DATA2 2
; CANDATA33.DATA1 1
; CANDATA33.DATA0 0
; CANDATA43 0x0066 CAN DATA REGISTER 43
; CANDATA43.DATA7 7
; CANDATA43.DATA6 6
; CANDATA43.DATA5 5
; CANDATA43.DATA4 4
; CANDATA43.DATA3 3
; CANDATA43.DATA2 2
; CANDATA43.DATA1 1
; CANDATA43.DATA0 0
; CANDATA53 0x0067 CAN DATA REGISTER 53
; CANDATA53.DATA7 7
; CANDATA53.DATA6 6
; CANDATA53.DATA5 5
; CANDATA53.DATA4 4
; CANDATA53.DATA3 3
; CANDATA53.DATA2 2
; CANDATA53.DATA1 1
; CANDATA53.DATA0 0
; CANDATA63 0x0068 CAN DATA REGISTER 63
; CANDATA63.DATA7 7
; CANDATA63.DATA6 6
; CANDATA63.DATA5 5
; CANDATA63.DATA4 4
; CANDATA63.DATA3 3
; CANDATA63.DATA2 2
; CANDATA63.DATA1 1
; CANDATA63.DATA0 0
; CANDATA73 0x0069 CAN DATA REGISTER 73
; CANDATA73.DATA7 7
; CANDATA73.DATA6 6
; CANDATA73.DATA5 5
; CANDATA73.DATA4 4
; CANDATA73.DATA3 3
; CANDATA73.DATA2 2
; CANDATA73.DATA1 1
; CANDATA73.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR3 0x006F CAN BUFFER CONTROL/STATUS REGISTER 3
; CANBCSR3.ACC 3 Acceptance Code
; CANBCSR3.RDY 2 Message Ready
; CANBCSR3.BUSY 1 Busy Buffer
; CANBCSR3.LOCK 0 Lock Buffer
; CAN PAGE 4
; CANFHR0 0x0060 CAN FILTER HIGH REGISTER 0
; CANFHR0.FIL11 7
; CANFHR0.FIL10 6
; CANFHR0.FIL9 5
; CANFHR0.FIL8 4
; CANFHR0.FIL7 3
; CANFHR0.FIL6 2
; CANFHR0.FIL5 1
; CANFHR0.FlL4 0
; CANFLR0 0x0061 CAN FILTER LOW REGISTER 0
; CANFLR0.FIL3 3
; CANFLR0.FIL2 2
; CANFLR0.FIL1 1
; CANFLR0.FIL0 0
; CANMHR0 0x0062 CAN MASK HIGH REGISTER 0
; CANMHR0.MSK11 7
; CANMHR0.MSK10 6
; CANMHR0.MSK9 5
; CANMHR0.MSK8 4
; CANMHR0.MSK7 3
; CANMHR0.MSK6 2
; CANMHR0.MSK5 1
; CANMHR0.MSK4 0
; CANMLR0 0x0063 CAN MASK LOW REGISTER 0
; CANMLR0.MSK3 7
; CANMLR0.MSK2 6
; CANMLR0.MSK1 5
; CANMLR0.MSK0 4
; CANFHR1 0x0064 CAN FILTER HIGH REGISTER 1
; CANFHR1.FIL11 7
; CANFHR1.FIL10 6
; CANFHR1.FIL9 5
; CANFHR1.FIL8 4
; CANFHR1.FIL7 3
; CANFHR1.FIL6 2
; CANFHR1.FIL5 1
; CANFHR1.FlL4 0
; CANFLR1 0x0065 CAN FILTER LOW REGISTER 1
; CANFLR1.FIL3 3
; CANFLR1.FIL2 2
; CANFLR1.FIL1 1
; CANFLR1.FIL0 0
; CANMHR1 0x0066 CAN MASK HIGH REGISTER 1
; CANMHR1.MSK11 7
; CANMHR1.MSK10 6
; CANMHR1.MSK9 5
; CANMHR1.MSK8 4
; CANMHR1.MSK7 3
; CANMHR1.MSK6 2
; CANMHR1.MSK5 1
; CANMHR1.MSK4 0
; CANMLR1 0x0067 CAN MASK LOW REGISTER 1
; CANMLR1.MSK3 7
; CANMLR1.MSK2 6
; CANMLR1.MSK1 5
; CANMLR1.MSK0 4
; RESERVED0068 0x0068 RESERVED
; RESERVED0069 0x0069 RESERVED
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
PWMDCR3 0x0072 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0073 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0074 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72511R7
; :ST72511R7 :ST72T511R7
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=1536
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0680
area BSS RESERVED 0x0680:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
CANISR 0x005A CAN Interrupt Status Register
CANISR.RXIF3 7 Receive Interrupt Flag for Buffer 3
CANISR.RXIF2 6 Receive Interrupt Flag for Buffer 2
CANISR.RXIF1 5 Receive Interrupt Flag for Buffer 1
CANISR.TXIF 4 Transmit Interrupt Flag
CANISR.SCIF 3 Status Change Interrupt Flag
CANISR.ORIF 2 Overrun Interrupt Flag
CANISR.TEIF 1 Transmit Error Interrupt Flag
CANISR.EPND 0 Error Interrupt Pending
CANICR 0x005B CAN Interrupt Control Register
CANICR.ESCI 6 Extended Status Change Interrupt
CANICR.RXIE 5 Receive Interrupt Enable
CANICR.TXIE 4 Transmit Interrupt Enable
CANICR.SCIE 3 Status Change Interrupt Enable
CANICR.ORIE 2 Overrun Interrupt Enable
CANICR.TEIE 1 Transmit Error Interrupt Enable
CANICR.ETX 0 Early Transmit Interrupt
CANCSR 0x005C CAN Control / Status Register
CANCSR.BOFF 6 Bus-Off State
CANCSR.EPSV 5 Error Passive State
CANCSR.SRTE 4 Simultaneous Receive/Transmit Enable
CANCSR.NRTX 3 No Retransmission
CANCSR.FSYN 2 Fast Synchronization
CANCSR.WKPS 1 Wake-up Pulse
CANCSR.RUN 0 CAN Enable
CANBRPR 0x005D CAN Baud Rate Prescaler Register
CANBRPR.RJW1 7
CANBRPR.RJW0 6
CANBRPR.BRP5 5
CANBRPR.BRP4 4
CANBRPR.BRP3 3
CANBRPR.BRP2 2
CANBRPR.BRP1 1
CANBRPR.BRP0 0
CANBTR 0x005E CAN Bit Timing Register
CANBTR.BS22 6
CANBTR.BS21 5
CANBTR.BS20 4
CANBTR.BS13 3
CANBTR.BS12 2
CANBTR.BS11 1
CANBTR.BS10 0
CANPSR 0x005F CAN Page Selection Register
CANPSR.PAGE2 2
CANPSR.PAGE1 1
CANPSR.PAGE0 0
; CAN PAGE 0
CANLIDHR 0x0060 CAN LAST IDENTIFIER HIGH REGISTER
CANLIDHR.LID10 7
CANLIDHR.LID9 6
CANLIDHR.LID8 5
CANLIDHR.LID7 4
CANLIDHR.LID6 3
CANLIDHR.LID5 2
CANLIDHR.LID4 1
CANLIDHR.LID3 0
CANLIDLR 0x0061 CAN LAST IDENTIFIER LOW REGISTER
CANLIDLR.LID2 7
CANLIDLR.LID1 6
CANLIDLR.LID0 5
CANLIDLR.LRTR 4
CANLIDLR.LDLC3 3
CANLIDLR.LDLC2 2
CANLIDLR.LDLC1 1
CANLIDLR.LDLC0 0
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
CANTSTR 0x006D CAN TSTR
CANTECR 0x006E CAN TRANSMIT ERROR COUNTER REGISTER
CANTECR.TEC7 7
CANTECR.TEC6 6
CANTECR.TEC5 5
CANTECR.TEC4 4
CANTECR.TEC3 3
CANTECR.TEC2 2
CANTECR.TEC1 1
CANTECR.TEC0 0
CANRECR 0x006F CAN RECEIVE ERROR COUNTER REGISTER
CANRECR.REC7 7
CANRECR.REC6 6
CANRECR.REC5 5
CANRECR.REC4 4
CANRECR.REC3 3
CANRECR.REC2 2
CANRECR.REC1 1
CANRECR.REC0 0
; CAN PAGE 1
; CANIDHR1 0x0060 CAN IDENTIFIER HIGH REGISTER 1
; CANIDHR1.ID10 7
; CANIDHR1.ID9 6
; CANIDHR1.ID8 5
; CANIDHR1.ID7 4
; CANIDHR1.ID6 3
; CANIDHR1.ID5 2
; CANIDHR1.ID4 1
; CANIDHR1.ID3 0
; CANIDLR1 0x0061 CAN IDENTIFIER LOW REGISTER 1
; CANIDLR1.ID2 7
; CANIDLR1.ID1 6
; CANIDLR1.ID0 5
; CANIDLR1.RTR 4
; CANIDLR1.DLC3 3
; CANIDLR1.DLC2 2
; CANIDLR1.DLC1 1
; CANIDLR1.DLC0 0
; CANDATA01 0x0062 CAN DATA REGISTER 01
; CANDATA01.DATA7 7
; CANDATA01.DATA6 6
; CANDATA01.DATA5 5
; CANDATA01.DATA4 4
; CANDATA01.DATA3 3
; CANDATA01.DATA2 2
; CANDATA01.DATA1 1
; CANDATA01.DATA0 0
; CANDATA11 0x0063 CAN DATA REGISTER 11
; CANDATA11.DATA7 7
; CANDATA11.DATA6 6
; CANDATA11.DATA5 5
; CANDATA11.DATA4 4
; CANDATA11.DATA3 3
; CANDATA11.DATA2 2
; CANDATA11.DATA1 1
; CANDATA11.DATA0 0
; CANDATA21 0x0064 CAN DATA REGISTER 21
; CANDATA21.DATA7 7
; CANDATA21.DATA6 6
; CANDATA21.DATA5 5
; CANDATA21.DATA4 4
; CANDATA21.DATA3 3
; CANDATA21.DATA2 2
; CANDATA21.DATA1 1
; CANDATA21.DATA0 0
; CANDATA31 0x0065 CAN DATA REGISTER 31
; CANDATA31.DATA7 7
; CANDATA31.DATA6 6
; CANDATA31.DATA5 5
; CANDATA31.DATA4 4
; CANDATA31.DATA3 3
; CANDATA31.DATA2 2
; CANDATA31.DATA1 1
; CANDATA31.DATA0 0
; CANDATA41 0x0066 CAN DATA REGISTER 41
; CANDATA41.DATA7 7
; CANDATA41.DATA6 6
; CANDATA41.DATA5 5
; CANDATA41.DATA4 4
; CANDATA41.DATA3 3
; CANDATA41.DATA2 2
; CANDATA41.DATA1 1
; CANDATA41.DATA0 0
; CANDATA51 0x0067 CAN DATA REGISTER 51
; CANDATA51.DATA7 7
; CANDATA51.DATA6 6
; CANDATA51.DATA5 5
; CANDATA51.DATA4 4
; CANDATA51.DATA3 3
; CANDATA51.DATA2 2
; CANDATA51.DATA1 1
; CANDATA51.DATA0 0
; CANDATA61 0x0068 CAN DATA REGISTER 61
; CANDATA61.DATA7 7
; CANDATA61.DATA6 6
; CANDATA61.DATA5 5
; CANDATA61.DATA4 4
; CANDATA61.DATA3 3
; CANDATA61.DATA2 2
; CANDATA61.DATA1 1
; CANDATA61.DATA0 0
; CANDATA71 0x0069 CAN DATA REGISTER 71
; CANDATA71.DATA7 7
; CANDATA71.DATA6 6
; CANDATA71.DATA5 5
; CANDATA71.DATA4 4
; CANDATA71.DATA3 3
; CANDATA71.DATA2 2
; CANDATA71.DATA1 1
; CANDATA71.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR1 0x006F CAN BUFFER CONTROL/STATUS REGISTER 1
; CANBCSR1.ACC 3 Acceptance Code
; CANBCSR1.RDY 2 Message Ready
; CANBCSR1.BUSY 1 Busy Buffer
; CANBCSR1.LOCK 0 Lock Buffer
; CAN PAGE 2
; CANIDHR2 0x0060 CAN IDENTIFIER HIGH REGISTER 2
; CANIDHR2.ID10 7
; CANIDHR2.ID9 6
; CANIDHR2.ID8 5
; CANIDHR2.ID7 4
; CANIDHR2.ID6 3
; CANIDHR2.ID5 2
; CANIDHR2.ID4 1
; CANIDHR2.ID3 0
; CANIDLR2 0x0061 CAN IDENTIFIER LOW REGISTER 2
; CANIDLR2.ID2 7
; CANIDLR2.ID1 6
; CANIDLR2.ID0 5
; CANIDLR2.RTR 4
; CANIDLR2.DLC3 3
; CANIDLR2.DLC2 2
; CANIDLR2.DLC1 1
; CANIDLR2.DLC0 0
; CANDATA02 0x0062 CAN DATA REGISTER 02
; CANDATA02.DATA7 7
; CANDATA02.DATA6 6
; CANDATA02.DATA5 5
; CANDATA02.DATA4 4
; CANDATA02.DATA3 3
; CANDATA02.DATA2 2
; CANDATA02.DATA1 1
; CANDATA02.DATA0 0
; CANDATA12 0x0063 CAN DATA REGISTER 12
; CANDATA12.DATA7 7
; CANDATA12.DATA6 6
; CANDATA12.DATA5 5
; CANDATA12.DATA4 4
; CANDATA12.DATA3 3
; CANDATA12.DATA2 2
; CANDATA12.DATA1 1
; CANDATA12.DATA0 0
; CANDATA22 0x0064 CAN DATA REGISTER 22
; CANDATA22.DATA7 7
; CANDATA22.DATA6 6
; CANDATA22.DATA5 5
; CANDATA22.DATA4 4
; CANDATA22.DATA3 3
; CANDATA22.DATA2 2
; CANDATA22.DATA1 1
; CANDATA22.DATA0 0
; CANDATA32 0x0065 CAN DATA REGISTER 32
; CANDATA32.DATA7 7
; CANDATA32.DATA6 6
; CANDATA32.DATA5 5
; CANDATA32.DATA4 4
; CANDATA32.DATA3 3
; CANDATA32.DATA2 2
; CANDATA32.DATA1 1
; CANDATA32.DATA0 0
; CANDATA42 0x0066 CAN DATA REGISTER 42
; CANDATA42.DATA7 7
; CANDATA42.DATA6 6
; CANDATA42.DATA5 5
; CANDATA42.DATA4 4
; CANDATA42.DATA3 3
; CANDATA42.DATA2 2
; CANDATA42.DATA1 1
; CANDATA42.DATA0 0
; CANDATA52 0x0067 CAN DATA REGISTER 52
; CANDATA52.DATA7 7
; CANDATA52.DATA6 6
; CANDATA52.DATA5 5
; CANDATA52.DATA4 4
; CANDATA52.DATA3 3
; CANDATA52.DATA2 2
; CANDATA52.DATA1 1
; CANDATA52.DATA0 0
; CANDATA62 0x0068 CAN DATA REGISTER 62
; CANDATA62.DATA7 7
; CANDATA62.DATA6 6
; CANDATA62.DATA5 5
; CANDATA62.DATA4 4
; CANDATA62.DATA3 3
; CANDATA62.DATA2 2
; CANDATA62.DATA1 1
; CANDATA62.DATA0 0
; CANDATA72 0x0069 CAN DATA REGISTER 72
; CANDATA72.DATA7 7
; CANDATA72.DATA6 6
; CANDATA72.DATA5 5
; CANDATA72.DATA4 4
; CANDATA72.DATA3 3
; CANDATA72.DATA2 2
; CANDATA72.DATA1 1
; CANDATA72.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR2 0x006F CAN BUFFER CONTROL/STATUS REGISTER 2
; CANBCSR2.ACC 3 Acceptance Code
; CANBCSR2.RDY 2 Message Ready
; CANBCSR2.BUSY 1 Busy Buffer
; CANBCSR2.LOCK 0 Lock Buffer
; CAN PAGE 3
; CANIDHR3 0x0060 CAN IDENTIFIER HIGH REGISTER 3
; CANIDHR3.ID10 7
; CANIDHR3.ID9 6
; CANIDHR3.ID8 5
; CANIDHR3.ID7 4
; CANIDHR3.ID6 3
; CANIDHR3.ID5 2
; CANIDHR3.ID4 1
; CANIDHR3.ID3 0
; CANIDLR3 0x0061 CAN IDENTIFIER LOW REGISTER 3
; CANIDLR3.ID2 7
; CANIDLR3.ID1 6
; CANIDLR3.ID0 5
; CANIDLR3.RTR 4
; CANIDLR3.DLC3 3
; CANIDLR3.DLC2 2
; CANIDLR3.DLC1 1
; CANIDLR3.DLC0 0
; CANDATA03 0x0062 CAN DATA REGISTER 03
; CANDATA03.DATA7 7
; CANDATA03.DATA6 6
; CANDATA03.DATA5 5
; CANDATA03.DATA4 4
; CANDATA03.DATA3 3
; CANDATA03.DATA2 2
; CANDATA03.DATA1 1
; CANDATA03.DATA0 0
; CANDATA13 0x0063 CAN DATA REGISTER 13
; CANDATA13.DATA7 7
; CANDATA13.DATA6 6
; CANDATA13.DATA5 5
; CANDATA13.DATA4 4
; CANDATA13.DATA3 3
; CANDATA13.DATA2 2
; CANDATA13.DATA1 1
; CANDATA13.DATA0 0
; CANDATA23 0x0064 CAN DATA REGISTER 23
; CANDATA23.DATA7 7
; CANDATA23.DATA6 6
; CANDATA23.DATA5 5
; CANDATA23.DATA4 4
; CANDATA23.DATA3 3
; CANDATA23.DATA2 2
; CANDATA23.DATA1 1
; CANDATA23.DATA0 0
; CANDATA33 0x0065 CAN DATA REGISTER 33
; CANDATA33.DATA7 7
; CANDATA33.DATA6 6
; CANDATA33.DATA5 5
; CANDATA33.DATA4 4
; CANDATA33.DATA3 3
; CANDATA33.DATA2 2
; CANDATA33.DATA1 1
; CANDATA33.DATA0 0
; CANDATA43 0x0066 CAN DATA REGISTER 43
; CANDATA43.DATA7 7
; CANDATA43.DATA6 6
; CANDATA43.DATA5 5
; CANDATA43.DATA4 4
; CANDATA43.DATA3 3
; CANDATA43.DATA2 2
; CANDATA43.DATA1 1
; CANDATA43.DATA0 0
; CANDATA53 0x0067 CAN DATA REGISTER 53
; CANDATA53.DATA7 7
; CANDATA53.DATA6 6
; CANDATA53.DATA5 5
; CANDATA53.DATA4 4
; CANDATA53.DATA3 3
; CANDATA53.DATA2 2
; CANDATA53.DATA1 1
; CANDATA53.DATA0 0
; CANDATA63 0x0068 CAN DATA REGISTER 63
; CANDATA63.DATA7 7
; CANDATA63.DATA6 6
; CANDATA63.DATA5 5
; CANDATA63.DATA4 4
; CANDATA63.DATA3 3
; CANDATA63.DATA2 2
; CANDATA63.DATA1 1
; CANDATA63.DATA0 0
; CANDATA73 0x0069 CAN DATA REGISTER 73
; CANDATA73.DATA7 7
; CANDATA73.DATA6 6
; CANDATA73.DATA5 5
; CANDATA73.DATA4 4
; CANDATA73.DATA3 3
; CANDATA73.DATA2 2
; CANDATA73.DATA1 1
; CANDATA73.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR3 0x006F CAN BUFFER CONTROL/STATUS REGISTER 3
; CANBCSR3.ACC 3 Acceptance Code
; CANBCSR3.RDY 2 Message Ready
; CANBCSR3.BUSY 1 Busy Buffer
; CANBCSR3.LOCK 0 Lock Buffer
; CAN PAGE 4
; CANFHR0 0x0060 CAN FILTER HIGH REGISTER 0
; CANFHR0.FIL11 7
; CANFHR0.FIL10 6
; CANFHR0.FIL9 5
; CANFHR0.FIL8 4
; CANFHR0.FIL7 3
; CANFHR0.FIL6 2
; CANFHR0.FIL5 1
; CANFHR0.FlL4 0
; CANFLR0 0x0061 CAN FILTER LOW REGISTER 0
; CANFLR0.FIL3 3
; CANFLR0.FIL2 2
; CANFLR0.FIL1 1
; CANFLR0.FIL0 0
; CANMHR0 0x0062 CAN MASK HIGH REGISTER 0
; CANMHR0.MSK11 7
; CANMHR0.MSK10 6
; CANMHR0.MSK9 5
; CANMHR0.MSK8 4
; CANMHR0.MSK7 3
; CANMHR0.MSK6 2
; CANMHR0.MSK5 1
; CANMHR0.MSK4 0
; CANMLR0 0x0063 CAN MASK LOW REGISTER 0
; CANMLR0.MSK3 7
; CANMLR0.MSK2 6
; CANMLR0.MSK1 5
; CANMLR0.MSK0 4
; CANFHR1 0x0064 CAN FILTER HIGH REGISTER 1
; CANFHR1.FIL11 7
; CANFHR1.FIL10 6
; CANFHR1.FIL9 5
; CANFHR1.FIL8 4
; CANFHR1.FIL7 3
; CANFHR1.FIL6 2
; CANFHR1.FIL5 1
; CANFHR1.FlL4 0
; CANFLR1 0x0065 CAN FILTER LOW REGISTER 1
; CANFLR1.FIL3 3
; CANFLR1.FIL2 2
; CANFLR1.FIL1 1
; CANFLR1.FIL0 0
; CANMHR1 0x0066 CAN MASK HIGH REGISTER 1
; CANMHR1.MSK11 7
; CANMHR1.MSK10 6
; CANMHR1.MSK9 5
; CANMHR1.MSK8 4
; CANMHR1.MSK7 3
; CANMHR1.MSK6 2
; CANMHR1.MSK5 1
; CANMHR1.MSK4 0
; CANMLR1 0x0067 CAN MASK LOW REGISTER 1
; CANMLR1.MSK3 7
; CANMLR1.MSK2 6
; CANMLR1.MSK1 5
; CANMLR1.MSK0 4
; RESERVED0068 0x0068 RESERVED
; RESERVED0069 0x0069 RESERVED
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
PWMDCR3 0x0072 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0073 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0074 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72511R9
; :ST72511R9 :ST72T511R9 :ST72T511R9T6 :ST72T511R9T6S :ST72T511R9T7 :ST72T511R9T7S
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=2048
; EEPROM=0
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0880
area BSS RESERVED 0x0880:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
CANISR 0x005A CAN Interrupt Status Register
CANISR.RXIF3 7 Receive Interrupt Flag for Buffer 3
CANISR.RXIF2 6 Receive Interrupt Flag for Buffer 2
CANISR.RXIF1 5 Receive Interrupt Flag for Buffer 1
CANISR.TXIF 4 Transmit Interrupt Flag
CANISR.SCIF 3 Status Change Interrupt Flag
CANISR.ORIF 2 Overrun Interrupt Flag
CANISR.TEIF 1 Transmit Error Interrupt Flag
CANISR.EPND 0 Error Interrupt Pending
CANICR 0x005B CAN Interrupt Control Register
CANICR.ESCI 6 Extended Status Change Interrupt
CANICR.RXIE 5 Receive Interrupt Enable
CANICR.TXIE 4 Transmit Interrupt Enable
CANICR.SCIE 3 Status Change Interrupt Enable
CANICR.ORIE 2 Overrun Interrupt Enable
CANICR.TEIE 1 Transmit Error Interrupt Enable
CANICR.ETX 0 Early Transmit Interrupt
CANCSR 0x005C CAN Control / Status Register
CANCSR.BOFF 6 Bus-Off State
CANCSR.EPSV 5 Error Passive State
CANCSR.SRTE 4 Simultaneous Receive/Transmit Enable
CANCSR.NRTX 3 No Retransmission
CANCSR.FSYN 2 Fast Synchronization
CANCSR.WKPS 1 Wake-up Pulse
CANCSR.RUN 0 CAN Enable
CANBRPR 0x005D CAN Baud Rate Prescaler Register
CANBRPR.RJW1 7
CANBRPR.RJW0 6
CANBRPR.BRP5 5
CANBRPR.BRP4 4
CANBRPR.BRP3 3
CANBRPR.BRP2 2
CANBRPR.BRP1 1
CANBRPR.BRP0 0
CANBTR 0x005E CAN Bit Timing Register
CANBTR.BS22 6
CANBTR.BS21 5
CANBTR.BS20 4
CANBTR.BS13 3
CANBTR.BS12 2
CANBTR.BS11 1
CANBTR.BS10 0
CANPSR 0x005F CAN Page Selection Register
CANPSR.PAGE2 2
CANPSR.PAGE1 1
CANPSR.PAGE0 0
; CAN PAGE 0
CANLIDHR 0x0060 CAN LAST IDENTIFIER HIGH REGISTER
CANLIDHR.LID10 7
CANLIDHR.LID9 6
CANLIDHR.LID8 5
CANLIDHR.LID7 4
CANLIDHR.LID6 3
CANLIDHR.LID5 2
CANLIDHR.LID4 1
CANLIDHR.LID3 0
CANLIDLR 0x0061 CAN LAST IDENTIFIER LOW REGISTER
CANLIDLR.LID2 7
CANLIDLR.LID1 6
CANLIDLR.LID0 5
CANLIDLR.LRTR 4
CANLIDLR.LDLC3 3
CANLIDLR.LDLC2 2
CANLIDLR.LDLC1 1
CANLIDLR.LDLC0 0
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
CANTSTR 0x006D CAN TSTR
CANTECR 0x006E CAN TRANSMIT ERROR COUNTER REGISTER
CANTECR.TEC7 7
CANTECR.TEC6 6
CANTECR.TEC5 5
CANTECR.TEC4 4
CANTECR.TEC3 3
CANTECR.TEC2 2
CANTECR.TEC1 1
CANTECR.TEC0 0
CANRECR 0x006F CAN RECEIVE ERROR COUNTER REGISTER
CANRECR.REC7 7
CANRECR.REC6 6
CANRECR.REC5 5
CANRECR.REC4 4
CANRECR.REC3 3
CANRECR.REC2 2
CANRECR.REC1 1
CANRECR.REC0 0
; CAN PAGE 1
; CANIDHR1 0x0060 CAN IDENTIFIER HIGH REGISTER 1
; CANIDHR1.ID10 7
; CANIDHR1.ID9 6
; CANIDHR1.ID8 5
; CANIDHR1.ID7 4
; CANIDHR1.ID6 3
; CANIDHR1.ID5 2
; CANIDHR1.ID4 1
; CANIDHR1.ID3 0
; CANIDLR1 0x0061 CAN IDENTIFIER LOW REGISTER 1
; CANIDLR1.ID2 7
; CANIDLR1.ID1 6
; CANIDLR1.ID0 5
; CANIDLR1.RTR 4
; CANIDLR1.DLC3 3
; CANIDLR1.DLC2 2
; CANIDLR1.DLC1 1
; CANIDLR1.DLC0 0
; CANDATA01 0x0062 CAN DATA REGISTER 01
; CANDATA01.DATA7 7
; CANDATA01.DATA6 6
; CANDATA01.DATA5 5
; CANDATA01.DATA4 4
; CANDATA01.DATA3 3
; CANDATA01.DATA2 2
; CANDATA01.DATA1 1
; CANDATA01.DATA0 0
; CANDATA11 0x0063 CAN DATA REGISTER 11
; CANDATA11.DATA7 7
; CANDATA11.DATA6 6
; CANDATA11.DATA5 5
; CANDATA11.DATA4 4
; CANDATA11.DATA3 3
; CANDATA11.DATA2 2
; CANDATA11.DATA1 1
; CANDATA11.DATA0 0
; CANDATA21 0x0064 CAN DATA REGISTER 21
; CANDATA21.DATA7 7
; CANDATA21.DATA6 6
; CANDATA21.DATA5 5
; CANDATA21.DATA4 4
; CANDATA21.DATA3 3
; CANDATA21.DATA2 2
; CANDATA21.DATA1 1
; CANDATA21.DATA0 0
; CANDATA31 0x0065 CAN DATA REGISTER 31
; CANDATA31.DATA7 7
; CANDATA31.DATA6 6
; CANDATA31.DATA5 5
; CANDATA31.DATA4 4
; CANDATA31.DATA3 3
; CANDATA31.DATA2 2
; CANDATA31.DATA1 1
; CANDATA31.DATA0 0
; CANDATA41 0x0066 CAN DATA REGISTER 41
; CANDATA41.DATA7 7
; CANDATA41.DATA6 6
; CANDATA41.DATA5 5
; CANDATA41.DATA4 4
; CANDATA41.DATA3 3
; CANDATA41.DATA2 2
; CANDATA41.DATA1 1
; CANDATA41.DATA0 0
; CANDATA51 0x0067 CAN DATA REGISTER 51
; CANDATA51.DATA7 7
; CANDATA51.DATA6 6
; CANDATA51.DATA5 5
; CANDATA51.DATA4 4
; CANDATA51.DATA3 3
; CANDATA51.DATA2 2
; CANDATA51.DATA1 1
; CANDATA51.DATA0 0
; CANDATA61 0x0068 CAN DATA REGISTER 61
; CANDATA61.DATA7 7
; CANDATA61.DATA6 6
; CANDATA61.DATA5 5
; CANDATA61.DATA4 4
; CANDATA61.DATA3 3
; CANDATA61.DATA2 2
; CANDATA61.DATA1 1
; CANDATA61.DATA0 0
; CANDATA71 0x0069 CAN DATA REGISTER 71
; CANDATA71.DATA7 7
; CANDATA71.DATA6 6
; CANDATA71.DATA5 5
; CANDATA71.DATA4 4
; CANDATA71.DATA3 3
; CANDATA71.DATA2 2
; CANDATA71.DATA1 1
; CANDATA71.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR1 0x006F CAN BUFFER CONTROL/STATUS REGISTER 1
; CANBCSR1.ACC 3 Acceptance Code
; CANBCSR1.RDY 2 Message Ready
; CANBCSR1.BUSY 1 Busy Buffer
; CANBCSR1.LOCK 0 Lock Buffer
; CAN PAGE 2
; CANIDHR2 0x0060 CAN IDENTIFIER HIGH REGISTER 2
; CANIDHR2.ID10 7
; CANIDHR2.ID9 6
; CANIDHR2.ID8 5
; CANIDHR2.ID7 4
; CANIDHR2.ID6 3
; CANIDHR2.ID5 2
; CANIDHR2.ID4 1
; CANIDHR2.ID3 0
; CANIDLR2 0x0061 CAN IDENTIFIER LOW REGISTER 2
; CANIDLR2.ID2 7
; CANIDLR2.ID1 6
; CANIDLR2.ID0 5
; CANIDLR2.RTR 4
; CANIDLR2.DLC3 3
; CANIDLR2.DLC2 2
; CANIDLR2.DLC1 1
; CANIDLR2.DLC0 0
; CANDATA02 0x0062 CAN DATA REGISTER 02
; CANDATA02.DATA7 7
; CANDATA02.DATA6 6
; CANDATA02.DATA5 5
; CANDATA02.DATA4 4
; CANDATA02.DATA3 3
; CANDATA02.DATA2 2
; CANDATA02.DATA1 1
; CANDATA02.DATA0 0
; CANDATA12 0x0063 CAN DATA REGISTER 12
; CANDATA12.DATA7 7
; CANDATA12.DATA6 6
; CANDATA12.DATA5 5
; CANDATA12.DATA4 4
; CANDATA12.DATA3 3
; CANDATA12.DATA2 2
; CANDATA12.DATA1 1
; CANDATA12.DATA0 0
; CANDATA22 0x0064 CAN DATA REGISTER 22
; CANDATA22.DATA7 7
; CANDATA22.DATA6 6
; CANDATA22.DATA5 5
; CANDATA22.DATA4 4
; CANDATA22.DATA3 3
; CANDATA22.DATA2 2
; CANDATA22.DATA1 1
; CANDATA22.DATA0 0
; CANDATA32 0x0065 CAN DATA REGISTER 32
; CANDATA32.DATA7 7
; CANDATA32.DATA6 6
; CANDATA32.DATA5 5
; CANDATA32.DATA4 4
; CANDATA32.DATA3 3
; CANDATA32.DATA2 2
; CANDATA32.DATA1 1
; CANDATA32.DATA0 0
; CANDATA42 0x0066 CAN DATA REGISTER 42
; CANDATA42.DATA7 7
; CANDATA42.DATA6 6
; CANDATA42.DATA5 5
; CANDATA42.DATA4 4
; CANDATA42.DATA3 3
; CANDATA42.DATA2 2
; CANDATA42.DATA1 1
; CANDATA42.DATA0 0
; CANDATA52 0x0067 CAN DATA REGISTER 52
; CANDATA52.DATA7 7
; CANDATA52.DATA6 6
; CANDATA52.DATA5 5
; CANDATA52.DATA4 4
; CANDATA52.DATA3 3
; CANDATA52.DATA2 2
; CANDATA52.DATA1 1
; CANDATA52.DATA0 0
; CANDATA62 0x0068 CAN DATA REGISTER 62
; CANDATA62.DATA7 7
; CANDATA62.DATA6 6
; CANDATA62.DATA5 5
; CANDATA62.DATA4 4
; CANDATA62.DATA3 3
; CANDATA62.DATA2 2
; CANDATA62.DATA1 1
; CANDATA62.DATA0 0
; CANDATA72 0x0069 CAN DATA REGISTER 72
; CANDATA72.DATA7 7
; CANDATA72.DATA6 6
; CANDATA72.DATA5 5
; CANDATA72.DATA4 4
; CANDATA72.DATA3 3
; CANDATA72.DATA2 2
; CANDATA72.DATA1 1
; CANDATA72.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR2 0x006F CAN BUFFER CONTROL/STATUS REGISTER 2
; CANBCSR2.ACC 3 Acceptance Code
; CANBCSR2.RDY 2 Message Ready
; CANBCSR2.BUSY 1 Busy Buffer
; CANBCSR2.LOCK 0 Lock Buffer
; CAN PAGE 3
; CANIDHR3 0x0060 CAN IDENTIFIER HIGH REGISTER 3
; CANIDHR3.ID10 7
; CANIDHR3.ID9 6
; CANIDHR3.ID8 5
; CANIDHR3.ID7 4
; CANIDHR3.ID6 3
; CANIDHR3.ID5 2
; CANIDHR3.ID4 1
; CANIDHR3.ID3 0
; CANIDLR3 0x0061 CAN IDENTIFIER LOW REGISTER 3
; CANIDLR3.ID2 7
; CANIDLR3.ID1 6
; CANIDLR3.ID0 5
; CANIDLR3.RTR 4
; CANIDLR3.DLC3 3
; CANIDLR3.DLC2 2
; CANIDLR3.DLC1 1
; CANIDLR3.DLC0 0
; CANDATA03 0x0062 CAN DATA REGISTER 03
; CANDATA03.DATA7 7
; CANDATA03.DATA6 6
; CANDATA03.DATA5 5
; CANDATA03.DATA4 4
; CANDATA03.DATA3 3
; CANDATA03.DATA2 2
; CANDATA03.DATA1 1
; CANDATA03.DATA0 0
; CANDATA13 0x0063 CAN DATA REGISTER 13
; CANDATA13.DATA7 7
; CANDATA13.DATA6 6
; CANDATA13.DATA5 5
; CANDATA13.DATA4 4
; CANDATA13.DATA3 3
; CANDATA13.DATA2 2
; CANDATA13.DATA1 1
; CANDATA13.DATA0 0
; CANDATA23 0x0064 CAN DATA REGISTER 23
; CANDATA23.DATA7 7
; CANDATA23.DATA6 6
; CANDATA23.DATA5 5
; CANDATA23.DATA4 4
; CANDATA23.DATA3 3
; CANDATA23.DATA2 2
; CANDATA23.DATA1 1
; CANDATA23.DATA0 0
; CANDATA33 0x0065 CAN DATA REGISTER 33
; CANDATA33.DATA7 7
; CANDATA33.DATA6 6
; CANDATA33.DATA5 5
; CANDATA33.DATA4 4
; CANDATA33.DATA3 3
; CANDATA33.DATA2 2
; CANDATA33.DATA1 1
; CANDATA33.DATA0 0
; CANDATA43 0x0066 CAN DATA REGISTER 43
; CANDATA43.DATA7 7
; CANDATA43.DATA6 6
; CANDATA43.DATA5 5
; CANDATA43.DATA4 4
; CANDATA43.DATA3 3
; CANDATA43.DATA2 2
; CANDATA43.DATA1 1
; CANDATA43.DATA0 0
; CANDATA53 0x0067 CAN DATA REGISTER 53
; CANDATA53.DATA7 7
; CANDATA53.DATA6 6
; CANDATA53.DATA5 5
; CANDATA53.DATA4 4
; CANDATA53.DATA3 3
; CANDATA53.DATA2 2
; CANDATA53.DATA1 1
; CANDATA53.DATA0 0
; CANDATA63 0x0068 CAN DATA REGISTER 63
; CANDATA63.DATA7 7
; CANDATA63.DATA6 6
; CANDATA63.DATA5 5
; CANDATA63.DATA4 4
; CANDATA63.DATA3 3
; CANDATA63.DATA2 2
; CANDATA63.DATA1 1
; CANDATA63.DATA0 0
; CANDATA73 0x0069 CAN DATA REGISTER 73
; CANDATA73.DATA7 7
; CANDATA73.DATA6 6
; CANDATA73.DATA5 5
; CANDATA73.DATA4 4
; CANDATA73.DATA3 3
; CANDATA73.DATA2 2
; CANDATA73.DATA1 1
; CANDATA73.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR3 0x006F CAN BUFFER CONTROL/STATUS REGISTER 3
; CANBCSR3.ACC 3 Acceptance Code
; CANBCSR3.RDY 2 Message Ready
; CANBCSR3.BUSY 1 Busy Buffer
; CANBCSR3.LOCK 0 Lock Buffer
; CAN PAGE 4
; CANFHR0 0x0060 CAN FILTER HIGH REGISTER 0
; CANFHR0.FIL11 7
; CANFHR0.FIL10 6
; CANFHR0.FIL9 5
; CANFHR0.FIL8 4
; CANFHR0.FIL7 3
; CANFHR0.FIL6 2
; CANFHR0.FIL5 1
; CANFHR0.FlL4 0
; CANFLR0 0x0061 CAN FILTER LOW REGISTER 0
; CANFLR0.FIL3 3
; CANFLR0.FIL2 2
; CANFLR0.FIL1 1
; CANFLR0.FIL0 0
; CANMHR0 0x0062 CAN MASK HIGH REGISTER 0
; CANMHR0.MSK11 7
; CANMHR0.MSK10 6
; CANMHR0.MSK9 5
; CANMHR0.MSK8 4
; CANMHR0.MSK7 3
; CANMHR0.MSK6 2
; CANMHR0.MSK5 1
; CANMHR0.MSK4 0
; CANMLR0 0x0063 CAN MASK LOW REGISTER 0
; CANMLR0.MSK3 7
; CANMLR0.MSK2 6
; CANMLR0.MSK1 5
; CANMLR0.MSK0 4
; CANFHR1 0x0064 CAN FILTER HIGH REGISTER 1
; CANFHR1.FIL11 7
; CANFHR1.FIL10 6
; CANFHR1.FIL9 5
; CANFHR1.FIL8 4
; CANFHR1.FIL7 3
; CANFHR1.FIL6 2
; CANFHR1.FIL5 1
; CANFHR1.FlL4 0
; CANFLR1 0x0065 CAN FILTER LOW REGISTER 1
; CANFLR1.FIL3 3
; CANFLR1.FIL2 2
; CANFLR1.FIL1 1
; CANFLR1.FIL0 0
; CANMHR1 0x0066 CAN MASK HIGH REGISTER 1
; CANMHR1.MSK11 7
; CANMHR1.MSK10 6
; CANMHR1.MSK9 5
; CANMHR1.MSK8 4
; CANMHR1.MSK7 3
; CANMHR1.MSK6 2
; CANMHR1.MSK5 1
; CANMHR1.MSK4 0
; CANMLR1 0x0067 CAN MASK LOW REGISTER 1
; CANMLR1.MSK3 7
; CANMLR1.MSK2 6
; CANMLR1.MSK1 5
; CANMLR1.MSK0 4
; RESERVED0068 0x0068 RESERVED
; RESERVED0069 0x0069 RESERVED
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
PWMDCR3 0x0072 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0073 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0074 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72521AR6
; :ST72521AR6 :ST72F521AR6
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521AR7
; :ST72521AR7 :ST72F521AR7
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521AR9
; :ST72521AR9 :ST72F521AR9
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521M7
; :ST72521M7 :ST72F521M7
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521M9
; :ST72521M9 :ST72521M9T6 :ST72F521M9
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521R6
; :ST72521R6 :ST72F521R6
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521R7
; :ST72521R7 :ST72F521R7
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72521R9
; :ST72521R9 :ST72F521R9
; http://us.st.com/stonline/books/pdf/docs/7601.pdf
.ST72532R
; :ST72532R :ST72T532R4
; http://us.st.com/stonline/books/pdf/docs/6810.pdf
; RAM=1024
; EEPROM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0080
area DATA RAM_ 0x0080:0x0480
area BSS RESERVED 0x0480:0x0C00
area DATA EEPROM_ 0x0C00:0x0D00
area BSS RESERVED 0x0D00:0x1000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software Interrupt
interrupt TLI_ 0xFFFA External Top Level Interrupt
interrupt MCC_RTC 0xFFF8 Main Clock Controller Time Base Interrupt
interrupt ei0_ 0xFFF6 External Interrupt Port A3..0
interrupt ei1_ 0xFFF4 External Interrupt Port F2..0
interrupt ei2_ 0xFFF2 External Interrupt Port B3..0
interrupt ei3_ 0xFFF0 External Interrupt Port B7..4
interrupt CAN_ 0xFFEE CAN Peripheral Interrupts
interrupt SPI_ 0xFFEC SPI Peripheral Interrupts
interrupt TIMER_A 0xFFEA TIMER A Peripheral Interrupts
interrupt TIMER_B 0xFFE8 TIMER B Peripheral Interrupts
interrupt SCI_ 0xFFE6 SCI Peripheral Interrupts
interrupt EEPROM_ 0xFFE4 EEPROM Interrupt
interrupt PWM_ART 0xFFE0 PWM ART Overflow Interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0006 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED0007 0x0007 RESERVED
PBDR 0x0008 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0009 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x000A Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED000B 0x000B RESERVED
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
RESERVED000F 0x000F RESERVED
PDDR 0x0010 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x0011 Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x0012 Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
RESERVED0013 0x0013 RESERVED
PFDR 0x0014 Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0015 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0016 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
RESERVED0017 0x0017 RESERVED
RESERVED0018 0x0018 RESERVED
RESERVED0019 0x0019 RESERVED
RESERVED001A 0x001A RESERVED
RESERVED001B 0x001B RESERVED
RESERVED001C 0x001C RESERVED
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7 ei2 sensitivity
MISCR1.IS10 6 ei3 sensitivity
MISCR1.MCO 5 Main clock out selection
MISCR1.IS21 4 ei0 sensitivity
MISCR1.IS20 3 ei1 sensitivity
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow mode select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
ISPR0 0x0024 Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR1 0x0025 Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x0026 Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x0027 Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
RESERVED0028 0x0028 RESERVED
MCCSR 0x0029 Main Clock Control / Status Register
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
WDGCR 0x002A Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGSR 0x002B Watchdog Status Register
WDGSR.WDOGF 0 Watchdog flag
EECSR 0x002C Data EEPROM Control/Status Register
EECSR.IE 2 Interrupt enable
EECSR.LAT 1 Latch Access Transfer
EECSR.PGM 0 Programming control and status
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.IPA 7 Interrupt polarity for port A
MISCR2.IPB 6 Interrupt polarity for port B
MISCR2.BC1 5 Beep control 1
MISCR2.BC0 4 Beep control 0
MISCR2.TLIS 3 TLI sensitivity
MISCR2.TLIE 2 TLI enable
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
RESERVED0058 0x0058 RESERVED
RESERVED0059 0x0059 RESERVED
CANISR 0x005A CAN Interrupt Status Register
CANISR.RXIF3 7 Receive Interrupt Flag for Buffer 3
CANISR.RXIF2 6 Receive Interrupt Flag for Buffer 2
CANISR.RXIF1 5 Receive Interrupt Flag for Buffer 1
CANISR.TXIF 4 Transmit Interrupt Flag
CANISR.SCIF 3 Status Change Interrupt Flag
CANISR.ORIF 2 Overrun Interrupt Flag
CANISR.TEIF 1 Transmit Error Interrupt Flag
CANISR.EPND 0 Error Interrupt Pending
CANICR 0x005B CAN Interrupt Control Register
CANICR.ESCI 6 Extended Status Change Interrupt
CANICR.RXIE 5 Receive Interrupt Enable
CANICR.TXIE 4 Transmit Interrupt Enable
CANICR.SCIE 3 Status Change Interrupt Enable
CANICR.ORIE 2 Overrun Interrupt Enable
CANICR.TEIE 1 Transmit Error Interrupt Enable
CANICR.ETX 0 Early Transmit Interrupt
CANCSR 0x005C CAN Control / Status Register
CANCSR.BOFF 6 Bus-Off State
CANCSR.EPSV 5 Error Passive State
CANCSR.SRTE 4 Simultaneous Receive/Transmit Enable
CANCSR.NRTX 3 No Retransmission
CANCSR.FSYN 2 Fast Synchronization
CANCSR.WKPS 1 Wake-up Pulse
CANCSR.RUN 0 CAN Enable
CANBRPR 0x005D CAN Baud Rate Prescaler Register
CANBRPR.RJW1 7
CANBRPR.RJW0 6
CANBRPR.BRP5 5
CANBRPR.BRP4 4
CANBRPR.BRP3 3
CANBRPR.BRP2 2
CANBRPR.BRP1 1
CANBRPR.BRP0 0
CANBTR 0x005E CAN Bit Timing Register
CANBTR.BS22 6
CANBTR.BS21 5
CANBTR.BS20 4
CANBTR.BS13 3
CANBTR.BS12 2
CANBTR.BS11 1
CANBTR.BS10 0
CANPSR 0x005F CAN Page Selection Register
CANPSR.PAGE2 2
CANPSR.PAGE1 1
CANPSR.PAGE0 0
; CAN PAGE 0
CANLIDHR 0x0060 CAN LAST IDENTIFIER HIGH REGISTER
CANLIDHR.LID10 7
CANLIDHR.LID9 6
CANLIDHR.LID8 5
CANLIDHR.LID7 4
CANLIDHR.LID6 3
CANLIDHR.LID5 2
CANLIDHR.LID4 1
CANLIDHR.LID3 0
CANLIDLR 0x0061 CAN LAST IDENTIFIER LOW REGISTER
CANLIDLR.LID2 7
CANLIDLR.LID1 6
CANLIDLR.LID0 5
CANLIDLR.LRTR 4
CANLIDLR.LDLC3 3
CANLIDLR.LDLC2 2
CANLIDLR.LDLC1 1
CANLIDLR.LDLC0 0
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
CANTSTR 0x006D CAN TSTR
CANTECR 0x006E CAN TRANSMIT ERROR COUNTER REGISTER
CANTECR.TEC7 7
CANTECR.TEC6 6
CANTECR.TEC5 5
CANTECR.TEC4 4
CANTECR.TEC3 3
CANTECR.TEC2 2
CANTECR.TEC1 1
CANTECR.TEC0 0
CANRECR 0x006F CAN RECEIVE ERROR COUNTER REGISTER
CANRECR.REC7 7
CANRECR.REC6 6
CANRECR.REC5 5
CANRECR.REC4 4
CANRECR.REC3 3
CANRECR.REC2 2
CANRECR.REC1 1
CANRECR.REC0 0
; CAN PAGE 1
; CANIDHR1 0x0060 CAN IDENTIFIER HIGH REGISTER 1
; CANIDHR1.ID10 7
; CANIDHR1.ID9 6
; CANIDHR1.ID8 5
; CANIDHR1.ID7 4
; CANIDHR1.ID6 3
; CANIDHR1.ID5 2
; CANIDHR1.ID4 1
; CANIDHR1.ID3 0
; CANIDLR1 0x0061 CAN IDENTIFIER LOW REGISTER 1
; CANIDLR1.ID2 7
; CANIDLR1.ID1 6
; CANIDLR1.ID0 5
; CANIDLR1.RTR 4
; CANIDLR1.DLC3 3
; CANIDLR1.DLC2 2
; CANIDLR1.DLC1 1
; CANIDLR1.DLC0 0
; CANDATA01 0x0062 CAN DATA REGISTER 01
; CANDATA01.DATA7 7
; CANDATA01.DATA6 6
; CANDATA01.DATA5 5
; CANDATA01.DATA4 4
; CANDATA01.DATA3 3
; CANDATA01.DATA2 2
; CANDATA01.DATA1 1
; CANDATA01.DATA0 0
; CANDATA11 0x0063 CAN DATA REGISTER 11
; CANDATA11.DATA7 7
; CANDATA11.DATA6 6
; CANDATA11.DATA5 5
; CANDATA11.DATA4 4
; CANDATA11.DATA3 3
; CANDATA11.DATA2 2
; CANDATA11.DATA1 1
; CANDATA11.DATA0 0
; CANDATA21 0x0064 CAN DATA REGISTER 21
; CANDATA21.DATA7 7
; CANDATA21.DATA6 6
; CANDATA21.DATA5 5
; CANDATA21.DATA4 4
; CANDATA21.DATA3 3
; CANDATA21.DATA2 2
; CANDATA21.DATA1 1
; CANDATA21.DATA0 0
; CANDATA31 0x0065 CAN DATA REGISTER 31
; CANDATA31.DATA7 7
; CANDATA31.DATA6 6
; CANDATA31.DATA5 5
; CANDATA31.DATA4 4
; CANDATA31.DATA3 3
; CANDATA31.DATA2 2
; CANDATA31.DATA1 1
; CANDATA31.DATA0 0
; CANDATA41 0x0066 CAN DATA REGISTER 41
; CANDATA41.DATA7 7
; CANDATA41.DATA6 6
; CANDATA41.DATA5 5
; CANDATA41.DATA4 4
; CANDATA41.DATA3 3
; CANDATA41.DATA2 2
; CANDATA41.DATA1 1
; CANDATA41.DATA0 0
; CANDATA51 0x0067 CAN DATA REGISTER 51
; CANDATA51.DATA7 7
; CANDATA51.DATA6 6
; CANDATA51.DATA5 5
; CANDATA51.DATA4 4
; CANDATA51.DATA3 3
; CANDATA51.DATA2 2
; CANDATA51.DATA1 1
; CANDATA51.DATA0 0
; CANDATA61 0x0068 CAN DATA REGISTER 61
; CANDATA61.DATA7 7
; CANDATA61.DATA6 6
; CANDATA61.DATA5 5
; CANDATA61.DATA4 4
; CANDATA61.DATA3 3
; CANDATA61.DATA2 2
; CANDATA61.DATA1 1
; CANDATA61.DATA0 0
; CANDATA71 0x0069 CAN DATA REGISTER 71
; CANDATA71.DATA7 7
; CANDATA71.DATA6 6
; CANDATA71.DATA5 5
; CANDATA71.DATA4 4
; CANDATA71.DATA3 3
; CANDATA71.DATA2 2
; CANDATA71.DATA1 1
; CANDATA71.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR1 0x006F CAN BUFFER CONTROL/STATUS REGISTER 1
; CANBCSR1.ACC 3 Acceptance Code
; CANBCSR1.RDY 2 Message Ready
; CANBCSR1.BUSY 1 Busy Buffer
; CANBCSR1.LOCK 0 Lock Buffer
; CAN PAGE 2
; CANIDHR2 0x0060 CAN IDENTIFIER HIGH REGISTER 2
; CANIDHR2.ID10 7
; CANIDHR2.ID9 6
; CANIDHR2.ID8 5
; CANIDHR2.ID7 4
; CANIDHR2.ID6 3
; CANIDHR2.ID5 2
; CANIDHR2.ID4 1
; CANIDHR2.ID3 0
; CANIDLR2 0x0061 CAN IDENTIFIER LOW REGISTER 2
; CANIDLR2.ID2 7
; CANIDLR2.ID1 6
; CANIDLR2.ID0 5
; CANIDLR2.RTR 4
; CANIDLR2.DLC3 3
; CANIDLR2.DLC2 2
; CANIDLR2.DLC1 1
; CANIDLR2.DLC0 0
; CANDATA02 0x0062 CAN DATA REGISTER 02
; CANDATA02.DATA7 7
; CANDATA02.DATA6 6
; CANDATA02.DATA5 5
; CANDATA02.DATA4 4
; CANDATA02.DATA3 3
; CANDATA02.DATA2 2
; CANDATA02.DATA1 1
; CANDATA02.DATA0 0
; CANDATA12 0x0063 CAN DATA REGISTER 12
; CANDATA12.DATA7 7
; CANDATA12.DATA6 6
; CANDATA12.DATA5 5
; CANDATA12.DATA4 4
; CANDATA12.DATA3 3
; CANDATA12.DATA2 2
; CANDATA12.DATA1 1
; CANDATA12.DATA0 0
; CANDATA22 0x0064 CAN DATA REGISTER 22
; CANDATA22.DATA7 7
; CANDATA22.DATA6 6
; CANDATA22.DATA5 5
; CANDATA22.DATA4 4
; CANDATA22.DATA3 3
; CANDATA22.DATA2 2
; CANDATA22.DATA1 1
; CANDATA22.DATA0 0
; CANDATA32 0x0065 CAN DATA REGISTER 32
; CANDATA32.DATA7 7
; CANDATA32.DATA6 6
; CANDATA32.DATA5 5
; CANDATA32.DATA4 4
; CANDATA32.DATA3 3
; CANDATA32.DATA2 2
; CANDATA32.DATA1 1
; CANDATA32.DATA0 0
; CANDATA42 0x0066 CAN DATA REGISTER 42
; CANDATA42.DATA7 7
; CANDATA42.DATA6 6
; CANDATA42.DATA5 5
; CANDATA42.DATA4 4
; CANDATA42.DATA3 3
; CANDATA42.DATA2 2
; CANDATA42.DATA1 1
; CANDATA42.DATA0 0
; CANDATA52 0x0067 CAN DATA REGISTER 52
; CANDATA52.DATA7 7
; CANDATA52.DATA6 6
; CANDATA52.DATA5 5
; CANDATA52.DATA4 4
; CANDATA52.DATA3 3
; CANDATA52.DATA2 2
; CANDATA52.DATA1 1
; CANDATA52.DATA0 0
; CANDATA62 0x0068 CAN DATA REGISTER 62
; CANDATA62.DATA7 7
; CANDATA62.DATA6 6
; CANDATA62.DATA5 5
; CANDATA62.DATA4 4
; CANDATA62.DATA3 3
; CANDATA62.DATA2 2
; CANDATA62.DATA1 1
; CANDATA62.DATA0 0
; CANDATA72 0x0069 CAN DATA REGISTER 72
; CANDATA72.DATA7 7
; CANDATA72.DATA6 6
; CANDATA72.DATA5 5
; CANDATA72.DATA4 4
; CANDATA72.DATA3 3
; CANDATA72.DATA2 2
; CANDATA72.DATA1 1
; CANDATA72.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR2 0x006F CAN BUFFER CONTROL/STATUS REGISTER 2
; CANBCSR2.ACC 3 Acceptance Code
; CANBCSR2.RDY 2 Message Ready
; CANBCSR2.BUSY 1 Busy Buffer
; CANBCSR2.LOCK 0 Lock Buffer
; CAN PAGE 3
; CANIDHR3 0x0060 CAN IDENTIFIER HIGH REGISTER 3
; CANIDHR3.ID10 7
; CANIDHR3.ID9 6
; CANIDHR3.ID8 5
; CANIDHR3.ID7 4
; CANIDHR3.ID6 3
; CANIDHR3.ID5 2
; CANIDHR3.ID4 1
; CANIDHR3.ID3 0
; CANIDLR3 0x0061 CAN IDENTIFIER LOW REGISTER 3
; CANIDLR3.ID2 7
; CANIDLR3.ID1 6
; CANIDLR3.ID0 5
; CANIDLR3.RTR 4
; CANIDLR3.DLC3 3
; CANIDLR3.DLC2 2
; CANIDLR3.DLC1 1
; CANIDLR3.DLC0 0
; CANDATA03 0x0062 CAN DATA REGISTER 03
; CANDATA03.DATA7 7
; CANDATA03.DATA6 6
; CANDATA03.DATA5 5
; CANDATA03.DATA4 4
; CANDATA03.DATA3 3
; CANDATA03.DATA2 2
; CANDATA03.DATA1 1
; CANDATA03.DATA0 0
; CANDATA13 0x0063 CAN DATA REGISTER 13
; CANDATA13.DATA7 7
; CANDATA13.DATA6 6
; CANDATA13.DATA5 5
; CANDATA13.DATA4 4
; CANDATA13.DATA3 3
; CANDATA13.DATA2 2
; CANDATA13.DATA1 1
; CANDATA13.DATA0 0
; CANDATA23 0x0064 CAN DATA REGISTER 23
; CANDATA23.DATA7 7
; CANDATA23.DATA6 6
; CANDATA23.DATA5 5
; CANDATA23.DATA4 4
; CANDATA23.DATA3 3
; CANDATA23.DATA2 2
; CANDATA23.DATA1 1
; CANDATA23.DATA0 0
; CANDATA33 0x0065 CAN DATA REGISTER 33
; CANDATA33.DATA7 7
; CANDATA33.DATA6 6
; CANDATA33.DATA5 5
; CANDATA33.DATA4 4
; CANDATA33.DATA3 3
; CANDATA33.DATA2 2
; CANDATA33.DATA1 1
; CANDATA33.DATA0 0
; CANDATA43 0x0066 CAN DATA REGISTER 43
; CANDATA43.DATA7 7
; CANDATA43.DATA6 6
; CANDATA43.DATA5 5
; CANDATA43.DATA4 4
; CANDATA43.DATA3 3
; CANDATA43.DATA2 2
; CANDATA43.DATA1 1
; CANDATA43.DATA0 0
; CANDATA53 0x0067 CAN DATA REGISTER 53
; CANDATA53.DATA7 7
; CANDATA53.DATA6 6
; CANDATA53.DATA5 5
; CANDATA53.DATA4 4
; CANDATA53.DATA3 3
; CANDATA53.DATA2 2
; CANDATA53.DATA1 1
; CANDATA53.DATA0 0
; CANDATA63 0x0068 CAN DATA REGISTER 63
; CANDATA63.DATA7 7
; CANDATA63.DATA6 6
; CANDATA63.DATA5 5
; CANDATA63.DATA4 4
; CANDATA63.DATA3 3
; CANDATA63.DATA2 2
; CANDATA63.DATA1 1
; CANDATA63.DATA0 0
; CANDATA73 0x0069 CAN DATA REGISTER 73
; CANDATA73.DATA7 7
; CANDATA73.DATA6 6
; CANDATA73.DATA5 5
; CANDATA73.DATA4 4
; CANDATA73.DATA3 3
; CANDATA73.DATA2 2
; CANDATA73.DATA1 1
; CANDATA73.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR3 0x006F CAN BUFFER CONTROL/STATUS REGISTER 3
; CANBCSR3.ACC 3 Acceptance Code
; CANBCSR3.RDY 2 Message Ready
; CANBCSR3.BUSY 1 Busy Buffer
; CANBCSR3.LOCK 0 Lock Buffer
; CAN PAGE 4
; CANFHR0 0x0060 CAN FILTER HIGH REGISTER 0
; CANFHR0.FIL11 7
; CANFHR0.FIL10 6
; CANFHR0.FIL9 5
; CANFHR0.FIL8 4
; CANFHR0.FIL7 3
; CANFHR0.FIL6 2
; CANFHR0.FIL5 1
; CANFHR0.FlL4 0
; CANFLR0 0x0061 CAN FILTER LOW REGISTER 0
; CANFLR0.FIL3 3
; CANFLR0.FIL2 2
; CANFLR0.FIL1 1
; CANFLR0.FIL0 0
; CANMHR0 0x0062 CAN MASK HIGH REGISTER 0
; CANMHR0.MSK11 7
; CANMHR0.MSK10 6
; CANMHR0.MSK9 5
; CANMHR0.MSK8 4
; CANMHR0.MSK7 3
; CANMHR0.MSK6 2
; CANMHR0.MSK5 1
; CANMHR0.MSK4 0
; CANMLR0 0x0063 CAN MASK LOW REGISTER 0
; CANMLR0.MSK3 7
; CANMLR0.MSK2 6
; CANMLR0.MSK1 5
; CANMLR0.MSK0 4
; CANFHR1 0x0064 CAN FILTER HIGH REGISTER 1
; CANFHR1.FIL11 7
; CANFHR1.FIL10 6
; CANFHR1.FIL9 5
; CANFHR1.FIL8 4
; CANFHR1.FIL7 3
; CANFHR1.FIL6 2
; CANFHR1.FIL5 1
; CANFHR1.FlL4 0
; CANFLR1 0x0065 CAN FILTER LOW REGISTER 1
; CANFLR1.FIL3 3
; CANFLR1.FIL2 2
; CANFLR1.FIL1 1
; CANFLR1.FIL0 0
; CANMHR1 0x0066 CAN MASK HIGH REGISTER 1
; CANMHR1.MSK11 7
; CANMHR1.MSK10 6
; CANMHR1.MSK9 5
; CANMHR1.MSK8 4
; CANMHR1.MSK7 3
; CANMHR1.MSK6 2
; CANMHR1.MSK5 1
; CANMHR1.MSK4 0
; CANMLR1 0x0067 CAN MASK LOW REGISTER 1
; CANMLR1.MSK3 7
; CANMLR1.MSK2 6
; CANMLR1.MSK1 5
; CANMLR1.MSK0 4
; RESERVED0068 0x0068 RESERVED
; RESERVED0069 0x0069 RESERVED
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
RESERVED0072 0x0072 RESERVED
RESERVED0073 0x0073 RESERVED
RESERVED0074 0x0074 RESERVED
RESERVED0075 0x0075 RESERVED
RESERVED0076 0x0076 RESERVED
RESERVED0077 0x0077 RESERVED
RESERVED0078 0x0078 RESERVED
RESERVED0079 0x0079 RESERVED
RESERVED007A 0x007A RESERVED
RESERVED007B 0x007B RESERVED
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72589BW
; :ST72589BW :ST72589BW5 :ST72P589BW5 :ST72T589BW5
; http://us.st.com/stonline/books/pdf/docs/7517.pdf
; RAM=1024
; MEMORY MAP
area DATA FSR_1 0x0000:0x000F
area BSS RESERVED 0x000F:0x001C
area DATA FSR_2 0x001C:0x007A
area BSS RESERVED 0x007A:0x0080
area DATA RAM 0x0080:0x0480
area DATA LCD_RAM 0x0480:0x04BC
area BSS RESERVED 0x04BC:0xA000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) interrupt vector
interrupt NMI_ 0xFFFA Non maskable external interrupt vector
interrupt EI1_ 0xFFF8 External interrupt vector (port A3..0)
interrupt EI2_ 0xFFF6 External interrupt vector (port A7..4)
interrupt EI3_ 0xFFF4 External interrupt vector (port B)
interrupt EI4_ 0xFFF2 External interrupt vector (port C)
interrupt EI5_ 0xFFF0 External interrupt vector (port D)
interrupt MCC_ 0xFFEE MCC interrupt vector
interrupt ACC_ 0xFFEC ACC interrupt vector
interrupt CAN_ 0xFFEA CAN interrupt vector
interrupt SPI_ 0xFFE8 SPI interrupt vector
interrupt TIMER_A 0xFFE6 TIMER A interrupt vector
interrupt TIMER_B 0xFFE4 TIMER B interrupt vector
interrupt SCI_ 0xFFE2 SCI interrupt vector
interrupt I2C_ 0xFFE0 I2C interrupt vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PCDR 0x0008 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0009 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x000A Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
RESERVED000B 0x000B RESERVED
PDDR 0x000C Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x000D Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
PDOR 0x000E Port D Option Register
PDOR.O7 7 Port C Option Register bit 7
PDOR.O6 6 Port C Option Register bit 6
PDOR.O5 5 Port C Option Register bit 5
PDOR.O4 4 Port C Option Register bit 4
PDOR.O3 3 Port C Option Register bit 3
PDOR.O2 2 Port C Option Register bit 2
PDOR.O1 1 Port C Option Register bit 1
PDOR.O0 0 Port C Option Register bit 0
ISPR0 0x001C Interrupt Software Priority Register 0
ISPR0.I1_3 7
ISPR0.I0_3 6
ISPR0.I1_2 5
ISPR0.I0_2 4
ISPR0.I1_1 3
ISPR0.I0_1 2
ISPR0.I1_0 1
ISPR0.I0_0 0
ISPR1 0x001D Interrupt Software Priority Register 1
ISPR1.I1_7 7
ISPR1.I0_7 6
ISPR1.I1_6 5
ISPR1.I0_6 4
ISPR1.I1_5 3
ISPR1.I0_5 2
ISPR1.I1_4 1
ISPR1.I0_4 0
ISPR2 0x001E Interrupt Software Priority Register 2
ISPR2.I1_11 7
ISPR2.I0_11 6
ISPR2.I1_10 5
ISPR2.I0_10 4
ISPR2.I1_9 3
ISPR2.I0_9 2
ISPR2.I1_8 1
ISPR2.I0_8 0
ISPR3 0x001F Interrupt Software Priority Register 3
ISPR3.I1_13 3
ISPR3.I0_13 2
ISPR3.I1_12 1
ISPR3.I0_12 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.IS11 7
MISCR1.IS10 6
MISCR1.IS21 5
MISCR1.IS20 4
MISCR1.NMIS 1 NMI Sensitivity
MISCR1.NMIE 0 NMI Enable
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED0025 0x0025 RESERVED
MCCSR 0x0026 Main Clock Control / Status Register
MCCSR.SMS 7 Slow mode select
MCCSR.CP1 6 CPU clock prescaler
MCCSR.CP0 5 CPU clock prescaler
MCCSR.TB1 3 Time base control 1
MCCSR.TB0 2 Time base control 0
MCCSR.OIE 1 Oscillator interrupt enable
MCCSR.OIF 0 Oscillator interrupt flag
ACCSR 0x0027 Auxiliary Clock Control / Status Register
ACCSR.OE 2 Oscillator enable
ACCSR.OIE 1 Oscillator interrupt enable
ACCSR.OIF 0 Oscillator interrupt flag
I2CCR 0x0028 I2C Control Register
I2CCR.PE 5 Peripheral enable
I2CCR.ENGC 4 Enable General Call
I2CCR.START 3 Generation of a Start condition
I2CCR.ACK 2 Acknowledge enable
I2CCR.STOP 1 Generation of a Stop condition
I2CCR.ITE 0 Interrupt enable
I2CSR1 0x0029 I2C Status Register 1
I2CSR1.EVF 7 Event flag
I2CSR1.ADD10 6 10-bit addressing in Master mode
I2CSR1.TRA 5 Transmitter/Receiver
I2CSR1.BUSY 4 Bus busy
I2CSR1.BTF 3 Byte transfer finished
I2CSR1.ADSL 2 Address matched (Slave mode)
I2CSR1.M_SL 1 Master/Slave
I2CSR1.SB 0 Start bit (Master mode)
I2CSR2 0x002A I2C Status Register 2
I2CSR2.AF 4 Acknowledge failure
I2CSR2.STOPF 3 Stop detection (Slave mode)
I2CSR2.ARLO 2 Arbitration lost
I2CSR2.BERR 1 Bus error
I2CSR2.GCAL 0 General Call (Slave mode)
I2CCCR 0x002B I2C Clock Control Register
I2CCCR.FM_SM 7 Fast/Standard I2C mode
I2CCCR.CC6 6 clock divider bit 6
I2CCCR.CC5 5 clock divider bit 5
I2CCCR.CC4 4 clock divider bit 4
I2CCCR.CC3 3 clock divider bit 3
I2CCCR.CC2 2 clock divider bit 2
I2CCCR.CC1 1 clock divider bit 1
I2CCCR.CC0 0 clock divider bit 0
I2COAR1 0x002C I2C Own Address Register 1
I2COAR1.ADD7 7 Interface addres 7
I2COAR1.ADD6 6 Interface addres 6
I2COAR1.ADD5 5 Interface addres 5
I2COAR1.ADD4 4 Interface addres 4
I2COAR1.ADD3 3 Interface addres 3
I2COAR1.ADD2 2 Interface addres 2
I2COAR1.ADD1 1 Interface addres 1
I2COAR1.ADD0 0 Interface addres 0
I2COAR2 0x002D I2C Own Address Register 2
I2COAR2.FR1 7 Frequency bit 1
I2COAR2.FR0 6 Frequency bit 0
I2COAR2.ADD9 2 Interface addres 9
I2COAR2.ADD8 1 Interface addres 8
I2CDR 0x002E I2C Data Register
I2CDR.D7 7 I2C Data Register bit 7
I2CDR.D6 6 I2C Data Register bit 6
I2CDR.D5 5 I2C Data Register bit 5
I2CDR.D4 4 I2C Data Register bit 4
I2CDR.D3 3 I2C Data Register bit 3
I2CDR.D2 2 I2C Data Register bit 2
I2CDR.D1 1 I2C Data Register bit 1
I2CDR.D0 0 I2C Data Register bit 0
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.ACO 7 Auxiliary clock-out control
MISCR2.MCO 6 Main clock-out control
MISCR2.BC1 5 Beep Control 1
MISCR2.BC0 4 Beep Control 0
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
TBCR2 0x0041 Timer B Control Register 2
TBCR2.OC1E 7 Output Compare 1 Pin Enable
TBCR2.OC2E 6 Output Compare 2 Pin Enable
TBCR2.OPM 5 One Pulse mode
TBCR2.PWM 4 Pulse Width Modulation
TBCR2.CC1 3 Clock Control 1
TBCR2.CC0 2 Clock Control 0
TBCR2.IEDG2 1 Input Edge 2
TBCR2.EXEDG 0 External Clock Edge
TBCR1 0x0042 Timer B Control Register 1
TBCR1.ICIE 7 Input Capture Interrupt Enable
TBCR1.OCIE 6 Output Compare Interrupt Enable
TBCR1.TOIE 5 Timer Overflow Interrupt Enable
TBCR1.FOLV2 4 Forced Output Compare 2
TBCR1.FOLV1 3 Forced Output Compare 1
TBCR1.OLVL2 2 Output Level 2
TBCR1.IEDG1 1 Input Edge 1
TBCR1.OLVL1 0 Output Level 1
TBSR 0x0043 Timer B Status Register
TBSR.ICF1 7 Input Capture Flag 1
TBSR.OCF1 6 Output Compare Flag 1
TBSR.TOF 5 Timer Overflow Flag
TBSR.ICF2 4 Input Capture Flag 2
TBSR.OCF2 3 Output Compare Flag 2
TBIC1HR 0x0044 Timer B Input Capture 1 High Register
TBIC1LR 0x0045 Timer B Input Capture 1 Low Register
TBOC1HR 0x0046 Timer B Output Compare 1 High Register
TBOC1LR 0x0047 Timer B Output Compare 1 Low Register
TBCHR 0x0048 Timer B Counter High Register
TBCLR 0x0049 Timer B Counter Low Register
TBACHR 0x004A Timer B Alternate Counter High Register
TBACLR 0x004B Timer B Alternate Counter Low Register
TBIC2HR 0x004C Timer B Input Capture 2 High Register
TBIC2LR 0x004D Timer B Input Capture 2 Low Register
TBOC2HR 0x004E Timer B Output Compare 2 High Register
TBOC2LR 0x004F Timer B Output Compare 2 Low Register
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCIERPR 0x0055 SCI Extended Receive Prescaler Register
SCIERPR.ERPR7 7 Extended Receive Prescaler Register bit 7
SCIERPR.ERPR6 6 Extended Receive Prescaler Register bit 6
SCIERPR.ERPR5 5 Extended Receive Prescaler Register bit 5
SCIERPR.ERPR4 4 Extended Receive Prescaler Register bit 4
SCIERPR.ERPR3 3 Extended Receive Prescaler Register bit 3
SCIERPR.ERPR2 2 Extended Receive Prescaler Register bit 2
SCIERPR.ERPR1 1 Extended Receive Prescaler Register bit 1
SCIERPR.ERPR0 0 Extended Receive Prescaler Register bit 0
RESERVED0056 0x0056 RESERVED
SCIETPR 0x0057 SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 Extended Transmit Prescaler Register bit 0
LCDCR 0x0058 LCD Control Register
LCDCR.DCS 7 Duty cycle selection
LCDCR.CD1 5 Clock divider 1
LCDCR.CD0 4 Clock divider 0
LCDCR.LCDE 3 LCD enable
LCDCR.CLKS 2 Clock selection
LCDCR.FS1 1 Frame Frequency selection 1
LCDCR.FS0 0 Frame Frequency selection 0
RESERVED0059 0x0059 RESERVED
CANISR 0x005A CAN Interrupt Status Register
CANISR.RXIF3 7 Receive Interrupt Flag for Buffer 3
CANISR.RXIF2 6 Receive Interrupt Flag for Buffer 2
CANISR.RXIF1 5 Receive Interrupt Flag for Buffer 1
CANISR.TXIF 4 Transmit Interrupt Flag
CANISR.SCIF 3 Status Change Interrupt Flag
CANISR.ORIF 2 Overrun Interrupt Flag
CANISR.TEIF 1 Transmit Error Interrupt Flag
CANISR.EPND 0 Error Interrupt Pending
CANICR 0x005B CAN Interrupt Control Register
CANICR.ESCI 6 Extended Status Change Interrupt
CANICR.RXIE 5 Receive Interrupt Enable
CANICR.TXIE 4 Transmit Interrupt Enable
CANICR.SCIE 3 Status Change Interrupt Enable
CANICR.ORIE 2 Overrun Interrupt Enable
CANICR.TEIE 1 Transmit Error Interrupt Enable
CANICR.ETX 0 Early Transmit Interrupt
CANCSR 0x005C CAN Control / Status Register
CANCSR.BOFF 6 Bus-Off State
CANCSR.EPSV 5 Error Passive State
CANCSR.SRTE 4 Simultaneous Receive/Transmit Enable
CANCSR.NRTX 3 No Retransmission
CANCSR.FSYN 2 Fast Synchronization
CANCSR.WKPS 1 Wake-up Pulse
CANCSR.RUN 0 CAN Enable
CANBRPR 0x005D CAN Baud Rate Prescaler Register
CANBRPR.RJW1 7
CANBRPR.RJW0 6
CANBRPR.BRP5 5
CANBRPR.BRP4 4
CANBRPR.BRP3 3
CANBRPR.BRP2 2
CANBRPR.BRP1 1
CANBRPR.BRP0 0
CANBTR 0x005E CAN Bit Timing Register
CANBTR.BS22 6
CANBTR.BS21 5
CANBTR.BS20 4
CANBTR.BS13 3
CANBTR.BS12 2
CANBTR.BS11 1
CANBTR.BS10 0
CANPSR 0x005F CAN Page Selection Register
CANPSR.PAGE2 2
CANPSR.PAGE1 1
CANPSR.PAGE0 0
; CAN PAGE 0
CANLIDHR 0x0060 CAN LAST IDENTIFIER HIGH REGISTER
CANLIDHR.LID10 7
CANLIDHR.LID9 6
CANLIDHR.LID8 5
CANLIDHR.LID7 4
CANLIDHR.LID6 3
CANLIDHR.LID5 2
CANLIDHR.LID4 1
CANLIDHR.LID3 0
CANLIDLR 0x0061 CAN LAST IDENTIFIER LOW REGISTER
CANLIDLR.LID2 7
CANLIDLR.LID1 6
CANLIDLR.LID0 5
CANLIDLR.LRTR 4
CANLIDLR.LDLC3 3
CANLIDLR.LDLC2 2
CANLIDLR.LDLC1 1
CANLIDLR.LDLC0 0
RESERVED0062 0x0062 RESERVED
RESERVED0063 0x0063 RESERVED
RESERVED0064 0x0064 RESERVED
RESERVED0065 0x0065 RESERVED
RESERVED0066 0x0066 RESERVED
RESERVED0067 0x0067 RESERVED
RESERVED0068 0x0068 RESERVED
RESERVED0069 0x0069 RESERVED
RESERVED006A 0x006A RESERVED
RESERVED006B 0x006B RESERVED
RESERVED006C 0x006C RESERVED
CANTSTR 0x006D CAN TSTR
CANTECR 0x006E CAN TRANSMIT ERROR COUNTER REGISTER
CANTECR.TEC7 7
CANTECR.TEC6 6
CANTECR.TEC5 5
CANTECR.TEC4 4
CANTECR.TEC3 3
CANTECR.TEC2 2
CANTECR.TEC1 1
CANTECR.TEC0 0
CANRECR 0x006F CAN RECEIVE ERROR COUNTER REGISTER
CANRECR.REC7 7
CANRECR.REC6 6
CANRECR.REC5 5
CANRECR.REC4 4
CANRECR.REC3 3
CANRECR.REC2 2
CANRECR.REC1 1
CANRECR.REC0 0
; CAN PAGE 1
; CANIDHR1 0x0060 CAN IDENTIFIER HIGH REGISTER 1
; CANIDHR1.ID10 7
; CANIDHR1.ID9 6
; CANIDHR1.ID8 5
; CANIDHR1.ID7 4
; CANIDHR1.ID6 3
; CANIDHR1.ID5 2
; CANIDHR1.ID4 1
; CANIDHR1.ID3 0
; CANIDLR1 0x0061 CAN IDENTIFIER LOW REGISTER 1
; CANIDLR1.ID2 7
; CANIDLR1.ID1 6
; CANIDLR1.ID0 5
; CANIDLR1.RTR 4
; CANIDLR1.DLC3 3
; CANIDLR1.DLC2 2
; CANIDLR1.DLC1 1
; CANIDLR1.DLC0 0
; CANDATA01 0x0062 CAN DATA REGISTER 01
; CANDATA01.DATA7 7
; CANDATA01.DATA6 6
; CANDATA01.DATA5 5
; CANDATA01.DATA4 4
; CANDATA01.DATA3 3
; CANDATA01.DATA2 2
; CANDATA01.DATA1 1
; CANDATA01.DATA0 0
; CANDATA11 0x0063 CAN DATA REGISTER 11
; CANDATA11.DATA7 7
; CANDATA11.DATA6 6
; CANDATA11.DATA5 5
; CANDATA11.DATA4 4
; CANDATA11.DATA3 3
; CANDATA11.DATA2 2
; CANDATA11.DATA1 1
; CANDATA11.DATA0 0
; CANDATA21 0x0064 CAN DATA REGISTER 21
; CANDATA21.DATA7 7
; CANDATA21.DATA6 6
; CANDATA21.DATA5 5
; CANDATA21.DATA4 4
; CANDATA21.DATA3 3
; CANDATA21.DATA2 2
; CANDATA21.DATA1 1
; CANDATA21.DATA0 0
; CANDATA31 0x0065 CAN DATA REGISTER 31
; CANDATA31.DATA7 7
; CANDATA31.DATA6 6
; CANDATA31.DATA5 5
; CANDATA31.DATA4 4
; CANDATA31.DATA3 3
; CANDATA31.DATA2 2
; CANDATA31.DATA1 1
; CANDATA31.DATA0 0
; CANDATA41 0x0066 CAN DATA REGISTER 41
; CANDATA41.DATA7 7
; CANDATA41.DATA6 6
; CANDATA41.DATA5 5
; CANDATA41.DATA4 4
; CANDATA41.DATA3 3
; CANDATA41.DATA2 2
; CANDATA41.DATA1 1
; CANDATA41.DATA0 0
; CANDATA51 0x0067 CAN DATA REGISTER 51
; CANDATA51.DATA7 7
; CANDATA51.DATA6 6
; CANDATA51.DATA5 5
; CANDATA51.DATA4 4
; CANDATA51.DATA3 3
; CANDATA51.DATA2 2
; CANDATA51.DATA1 1
; CANDATA51.DATA0 0
; CANDATA61 0x0068 CAN DATA REGISTER 61
; CANDATA61.DATA7 7
; CANDATA61.DATA6 6
; CANDATA61.DATA5 5
; CANDATA61.DATA4 4
; CANDATA61.DATA3 3
; CANDATA61.DATA2 2
; CANDATA61.DATA1 1
; CANDATA61.DATA0 0
; CANDATA71 0x0069 CAN DATA REGISTER 71
; CANDATA71.DATA7 7
; CANDATA71.DATA6 6
; CANDATA71.DATA5 5
; CANDATA71.DATA4 4
; CANDATA71.DATA3 3
; CANDATA71.DATA2 2
; CANDATA71.DATA1 1
; CANDATA71.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR1 0x006F CAN BUFFER CONTROL/STATUS REGISTER 1
; CANBCSR1.ACC 3 Acceptance Code
; CANBCSR1.RDY 2 Message Ready
; CANBCSR1.BUSY 1 Busy Buffer
; CANBCSR1.LOCK 0 Lock Buffer
; CAN PAGE 2
; CANIDHR2 0x0060 CAN IDENTIFIER HIGH REGISTER 2
; CANIDHR2.ID10 7
; CANIDHR2.ID9 6
; CANIDHR2.ID8 5
; CANIDHR2.ID7 4
; CANIDHR2.ID6 3
; CANIDHR2.ID5 2
; CANIDHR2.ID4 1
; CANIDHR2.ID3 0
; CANIDLR2 0x0061 CAN IDENTIFIER LOW REGISTER 2
; CANIDLR2.ID2 7
; CANIDLR2.ID1 6
; CANIDLR2.ID0 5
; CANIDLR2.RTR 4
; CANIDLR2.DLC3 3
; CANIDLR2.DLC2 2
; CANIDLR2.DLC1 1
; CANIDLR2.DLC0 0
; CANDATA02 0x0062 CAN DATA REGISTER 02
; CANDATA02.DATA7 7
; CANDATA02.DATA6 6
; CANDATA02.DATA5 5
; CANDATA02.DATA4 4
; CANDATA02.DATA3 3
; CANDATA02.DATA2 2
; CANDATA02.DATA1 1
; CANDATA02.DATA0 0
; CANDATA12 0x0063 CAN DATA REGISTER 12
; CANDATA12.DATA7 7
; CANDATA12.DATA6 6
; CANDATA12.DATA5 5
; CANDATA12.DATA4 4
; CANDATA12.DATA3 3
; CANDATA12.DATA2 2
; CANDATA12.DATA1 1
; CANDATA12.DATA0 0
; CANDATA22 0x0064 CAN DATA REGISTER 22
; CANDATA22.DATA7 7
; CANDATA22.DATA6 6
; CANDATA22.DATA5 5
; CANDATA22.DATA4 4
; CANDATA22.DATA3 3
; CANDATA22.DATA2 2
; CANDATA22.DATA1 1
; CANDATA22.DATA0 0
; CANDATA32 0x0065 CAN DATA REGISTER 32
; CANDATA32.DATA7 7
; CANDATA32.DATA6 6
; CANDATA32.DATA5 5
; CANDATA32.DATA4 4
; CANDATA32.DATA3 3
; CANDATA32.DATA2 2
; CANDATA32.DATA1 1
; CANDATA32.DATA0 0
; CANDATA42 0x0066 CAN DATA REGISTER 42
; CANDATA42.DATA7 7
; CANDATA42.DATA6 6
; CANDATA42.DATA5 5
; CANDATA42.DATA4 4
; CANDATA42.DATA3 3
; CANDATA42.DATA2 2
; CANDATA42.DATA1 1
; CANDATA42.DATA0 0
; CANDATA52 0x0067 CAN DATA REGISTER 52
; CANDATA52.DATA7 7
; CANDATA52.DATA6 6
; CANDATA52.DATA5 5
; CANDATA52.DATA4 4
; CANDATA52.DATA3 3
; CANDATA52.DATA2 2
; CANDATA52.DATA1 1
; CANDATA52.DATA0 0
; CANDATA62 0x0068 CAN DATA REGISTER 62
; CANDATA62.DATA7 7
; CANDATA62.DATA6 6
; CANDATA62.DATA5 5
; CANDATA62.DATA4 4
; CANDATA62.DATA3 3
; CANDATA62.DATA2 2
; CANDATA62.DATA1 1
; CANDATA62.DATA0 0
; CANDATA72 0x0069 CAN DATA REGISTER 72
; CANDATA72.DATA7 7
; CANDATA72.DATA6 6
; CANDATA72.DATA5 5
; CANDATA72.DATA4 4
; CANDATA72.DATA3 3
; CANDATA72.DATA2 2
; CANDATA72.DATA1 1
; CANDATA72.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR2 0x006F CAN BUFFER CONTROL/STATUS REGISTER 2
; CANBCSR2.ACC 3 Acceptance Code
; CANBCSR2.RDY 2 Message Ready
; CANBCSR2.BUSY 1 Busy Buffer
; CANBCSR2.LOCK 0 Lock Buffer
; CAN PAGE 3
; CANIDHR3 0x0060 CAN IDENTIFIER HIGH REGISTER 3
; CANIDHR3.ID10 7
; CANIDHR3.ID9 6
; CANIDHR3.ID8 5
; CANIDHR3.ID7 4
; CANIDHR3.ID6 3
; CANIDHR3.ID5 2
; CANIDHR3.ID4 1
; CANIDHR3.ID3 0
; CANIDLR3 0x0061 CAN IDENTIFIER LOW REGISTER 3
; CANIDLR3.ID2 7
; CANIDLR3.ID1 6
; CANIDLR3.ID0 5
; CANIDLR3.RTR 4
; CANIDLR3.DLC3 3
; CANIDLR3.DLC2 2
; CANIDLR3.DLC1 1
; CANIDLR3.DLC0 0
; CANDATA03 0x0062 CAN DATA REGISTER 03
; CANDATA03.DATA7 7
; CANDATA03.DATA6 6
; CANDATA03.DATA5 5
; CANDATA03.DATA4 4
; CANDATA03.DATA3 3
; CANDATA03.DATA2 2
; CANDATA03.DATA1 1
; CANDATA03.DATA0 0
; CANDATA13 0x0063 CAN DATA REGISTER 13
; CANDATA13.DATA7 7
; CANDATA13.DATA6 6
; CANDATA13.DATA5 5
; CANDATA13.DATA4 4
; CANDATA13.DATA3 3
; CANDATA13.DATA2 2
; CANDATA13.DATA1 1
; CANDATA13.DATA0 0
; CANDATA23 0x0064 CAN DATA REGISTER 23
; CANDATA23.DATA7 7
; CANDATA23.DATA6 6
; CANDATA23.DATA5 5
; CANDATA23.DATA4 4
; CANDATA23.DATA3 3
; CANDATA23.DATA2 2
; CANDATA23.DATA1 1
; CANDATA23.DATA0 0
; CANDATA33 0x0065 CAN DATA REGISTER 33
; CANDATA33.DATA7 7
; CANDATA33.DATA6 6
; CANDATA33.DATA5 5
; CANDATA33.DATA4 4
; CANDATA33.DATA3 3
; CANDATA33.DATA2 2
; CANDATA33.DATA1 1
; CANDATA33.DATA0 0
; CANDATA43 0x0066 CAN DATA REGISTER 43
; CANDATA43.DATA7 7
; CANDATA43.DATA6 6
; CANDATA43.DATA5 5
; CANDATA43.DATA4 4
; CANDATA43.DATA3 3
; CANDATA43.DATA2 2
; CANDATA43.DATA1 1
; CANDATA43.DATA0 0
; CANDATA53 0x0067 CAN DATA REGISTER 53
; CANDATA53.DATA7 7
; CANDATA53.DATA6 6
; CANDATA53.DATA5 5
; CANDATA53.DATA4 4
; CANDATA53.DATA3 3
; CANDATA53.DATA2 2
; CANDATA53.DATA1 1
; CANDATA53.DATA0 0
; CANDATA63 0x0068 CAN DATA REGISTER 63
; CANDATA63.DATA7 7
; CANDATA63.DATA6 6
; CANDATA63.DATA5 5
; CANDATA63.DATA4 4
; CANDATA63.DATA3 3
; CANDATA63.DATA2 2
; CANDATA63.DATA1 1
; CANDATA63.DATA0 0
; CANDATA73 0x0069 CAN DATA REGISTER 73
; CANDATA73.DATA7 7
; CANDATA73.DATA6 6
; CANDATA73.DATA5 5
; CANDATA73.DATA4 4
; CANDATA73.DATA3 3
; CANDATA73.DATA2 2
; CANDATA73.DATA1 1
; CANDATA73.DATA0 0
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; CANBCSR3 0x006F CAN BUFFER CONTROL/STATUS REGISTER 3
; CANBCSR3.ACC 3 Acceptance Code
; CANBCSR3.RDY 2 Message Ready
; CANBCSR3.BUSY 1 Busy Buffer
; CANBCSR3.LOCK 0 Lock Buffer
; CAN PAGE 4
; CANFHR0 0x0060 CAN FILTER HIGH REGISTER 0
; CANFHR0.FIL11 7
; CANFHR0.FIL10 6
; CANFHR0.FIL9 5
; CANFHR0.FIL8 4
; CANFHR0.FIL7 3
; CANFHR0.FIL6 2
; CANFHR0.FIL5 1
; CANFHR0.FlL4 0
; CANFLR0 0x0061 CAN FILTER LOW REGISTER 0
; CANFLR0.FIL3 3
; CANFLR0.FIL2 2
; CANFLR0.FIL1 1
; CANFLR0.FIL0 0
; CANMHR0 0x0062 CAN MASK HIGH REGISTER 0
; CANMHR0.MSK11 7
; CANMHR0.MSK10 6
; CANMHR0.MSK9 5
; CANMHR0.MSK8 4
; CANMHR0.MSK7 3
; CANMHR0.MSK6 2
; CANMHR0.MSK5 1
; CANMHR0.MSK4 0
; CANMLR0 0x0063 CAN MASK LOW REGISTER 0
; CANMLR0.MSK3 7
; CANMLR0.MSK2 6
; CANMLR0.MSK1 5
; CANMLR0.MSK0 4
; CANFHR1 0x0064 CAN FILTER HIGH REGISTER 1
; CANFHR1.FIL11 7
; CANFHR1.FIL10 6
; CANFHR1.FIL9 5
; CANFHR1.FIL8 4
; CANFHR1.FIL7 3
; CANFHR1.FIL6 2
; CANFHR1.FIL5 1
; CANFHR1.FlL4 0
; CANFLR1 0x0065 CAN FILTER LOW REGISTER 1
; CANFLR1.FIL3 3
; CANFLR1.FIL2 2
; CANFLR1.FIL1 1
; CANFLR1.FIL0 0
; CANMHR1 0x0066 CAN MASK HIGH REGISTER 1
; CANMHR1.MSK11 7
; CANMHR1.MSK10 6
; CANMHR1.MSK9 5
; CANMHR1.MSK8 4
; CANMHR1.MSK7 3
; CANMHR1.MSK6 2
; CANMHR1.MSK5 1
; CANMHR1.MSK4 0
; CANMLR1 0x0067 CAN MASK LOW REGISTER 1
; CANMLR1.MSK3 7
; CANMLR1.MSK2 6
; CANMLR1.MSK1 5
; CANMLR1.MSK0 4
; RESERVED0068 0x0068 RESERVED
; RESERVED0069 0x0069 RESERVED
; RESERVED006A 0x006A RESERVED
; RESERVED006B 0x006B RESERVED
; RESERVED006C 0x006C RESERVED
; RESERVED006D 0x006D RESERVED
; RESERVED006E 0x006E RESERVED
; RESERVED006F 0x006F RESERVED
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
RESERVED0072 0x0072 RESERVED
RESERVED0073 0x0073 RESERVED
PWM0 0x0074 PULSE BINARY WEIGHT REGISTER 0
PWM0.POL 6 Polarity Bit for channel 0
PWM0.P5 5 PWM Pulse Binary Weight for channel 0
PWM0.P4 4 PWM Pulse Binary Weight for channel 0
PWM0.P3 3 PWM Pulse Binary Weight for channel 0
PWM0.P2 2 PWM Pulse Binary Weight for channel 0
PWM0.P1 1 PWM Pulse Binary Weight for channel 0
PWM0.P0 0 PWM Pulse Binary Weight for channel 0
BRM10 0x0075 BRM REGISTER 10
BRM10.B7 7
BRM10.B6 6
BRM10.B5 5
BRM10.B4 4
BRM10.B3 3
BRM10.B2 2
BRM10.B1 1
BRM10.B0 0
PWM1 0x0076 PULSE BINARY WEIGHT REGISTER 1
PWM1.POL 6 Polarity Bit for channel 1
PWM1.P5 5 PWM Pulse Binary Weight for channel 1
PWM1.P4 4 PWM Pulse Binary Weight for channel 1
PWM1.P3 3 PWM Pulse Binary Weight for channel 1
PWM1.P2 2 PWM Pulse Binary Weight for channel 1
PWM1.P1 1 PWM Pulse Binary Weight for channel 1
PWM1.P0 0 PWM Pulse Binary Weight for channel 1
PWM2 0x0077 PULSE BINARY WEIGHT REGISTER 2
PWM2.POL 6 Polarity Bit for channel 2
PWM2.P5 5 PWM Pulse Binary Weight for channel 2
PWM2.P4 4 PWM Pulse Binary Weight for channel 2
PWM2.P3 3 PWM Pulse Binary Weight for channel 2
PWM2.P2 2 PWM Pulse Binary Weight for channel 2
PWM2.P1 1 PWM Pulse Binary Weight for channel 2
PWM2.P0 0 PWM Pulse Binary Weight for channel 2
BRM32 0x0078 BRM REGISTER 32
BRM32.B7 7
BRM32.B6 6
BRM32.B5 5
BRM32.B4 4
BRM32.B3 3
BRM32.B2 2
BRM32.B1 1
BRM32.B0 0
PWM3 0x0077 PULSE BINARY WEIGHT REGISTER 3
PWM3.POL 6 Polarity Bit for channel 3
PWM3.P5 5 PWM Pulse Binary Weight for channel 3
PWM3.P4 4 PWM Pulse Binary Weight for channel 3
PWM3.P3 3 PWM Pulse Binary Weight for channel 3
PWM3.P2 2 PWM Pulse Binary Weight for channel 3
PWM3.P1 1 PWM Pulse Binary Weight for channel 3
PWM3.P0 0 PWM Pulse Binary Weight for channel 3
.ST72561K9
; :ST72561K9
; http://us.st.com/stonline/books/pdf/docs/7212.pdf
; RAM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x0012
area BSS RESERVED 0x0012:0x0021
area DATA FSR_2 0x0021:0x0080
area DATA RAM 0x0080:0x0880
area CODE ROM 0x1000:0xFFE0 On-chip Program Memory
; Interrupt and reset vector assignments
entry __RESET 0xFFFE Reset
entry TRAP_ 0xFFFC Software Interrupt
entry TLI_ 0xFFFA External Top Level interrupt (EICR)
entry MCCRTC_ 0xFFF8 Main clock controller time base interrupt (MCCSR)
entry EIOAWUFH_ 0xFFF6 External interrupt ei0/ Auto wake-up from Halt (EICR/AWUCSR)
entry EI1AVD_ 0xFFF4 External interrupt ei1/Auxiliary Voltage Detector
entry EI2_ 0xFFF2 External interrupt ei2 (EICR)
entry EI3_ 0xFFF0 External interrupt ei3 (EICR)
entry CANRX_ 0xFFEE CAN Peripheral interrupt-RX (CIER)
entry CANTX_ 0xFFEC CAN Peripheral interrupt-TX (CIER)
entry SPI_ 0xFFEA SPI Peripheral interrupts (SPICSR)
entry TIMER_8 0xFFE8 TIMER 8 interrupt vector (T8_TCR1)
entry TIMER_16 0xFFE6 TIMER 16 interrupt vector (TCR1)
entry LINSCI2_ 0xFFE4 LINSCI2 pheripheral interrupts (SCI2CR1)
entry LINSCI1_ 0xFFE2 LINSCI1 pheripheral interrupts (SCI1CR1)
entry PWMART_ 0xFFE0 8-bit PWM ART interrupts (PWMCR)
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
PBDR 0x0003 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0004 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0005 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
PCDR 0x0006 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0007 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x0008 Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
PDDR 0x0009 Port D Data Register
PDDR.D7 7 Port D Data Register bit 7
PDDR.D6 6 Port D Data Register bit 6
PDDR.D5 5 Port D Data Register bit 5
PDDR.D4 4 Port D Data Register bit 4
PDDR.D3 3 Port D Data Register bit 3
PDDR.D2 2 Port D Data Register bit 2
PDDR.D1 1 Port D Data Register bit 1
PDDR.D0 0 Port D Data Register bit 0
PDDDR 0x000A Port D Data Direction Register
PDDDR.DD7 7 Port D Data Direction Register bit 7
PDDDR.DD6 6 Port D Data Direction Register bit 6
PDDDR.DD5 5 Port D Data Direction Register bit 5
PDDDR.DD4 4 Port D Data Direction Register bit 4
PDDDR.DD3 3 Port D Data Direction Register bit 3
PDDDR.DD2 2 Port D Data Direction Register bit 2
PDDDR.DD1 1 Port D Data Direction Register bit 1
PDDDR.DD0 0 Port D Data Direction Register bit 0
PDOR 0x000B Port D Option Register
PDOR.O7 7 Port D Option Register bit 7
PDOR.O6 6 Port D Option Register bit 6
PDOR.O5 5 Port D Option Register bit 5
PDOR.O4 4 Port D Option Register bit 4
PDOR.O3 3 Port D Option Register bit 3
PDOR.O2 2 Port D Option Register bit 2
PDOR.O1 1 Port D Option Register bit 1
PDOR.O0 0 Port D Option Register bit 0
PEDR 0x000C Port E Data Register
PEDR.D7 7 Port E Data Register bit 7
PEDR.D6 6 Port E Data Register bit 6
PEDR.D5 5 Port E Data Register bit 5
PEDR.D4 4 Port E Data Register bit 4
PEDR.D3 3 Port E Data Register bit 3
PEDR.D2 2 Port E Data Register bit 2
PEDR.D1 1 Port E Data Register bit 1
PEDR.D0 0 Port E Data Register bit 0
PEDDR 0x000D Port E Data Direction Register
PEDDR.DD7 7 Port E Data Direction Register bit 7
PEDDR.DD6 6 Port E Data Direction Register bit 6
PEDDR.DD5 5 Port E Data Direction Register bit 5
PEDDR.DD4 4 Port E Data Direction Register bit 4
PEDDR.DD3 3 Port E Data Direction Register bit 3
PEDDR.DD2 2 Port E Data Direction Register bit 2
PEDDR.DD1 1 Port E Data Direction Register bit 1
PEDDR.DD0 0 Port E Data Direction Register bit 0
PEOR 0x000E Port E Option Register
PEOR.O7 7 Port E Option Register bit 7
PEOR.O6 6 Port E Option Register bit 6
PEOR.O5 5 Port E Option Register bit 5
PEOR.O4 4 Port E Option Register bit 4
PEOR.O3 3 Port E Option Register bit 3
PEOR.O2 2 Port E Option Register bit 2
PEOR.O1 1 Port E Option Register bit 1
PEOR.O0 0 Port E Option Register bit 0
PFDR 0x000F Port F Data Register
PFDR.D7 7 Port F Data Register bit 7
PFDR.D6 6 Port F Data Register bit 6
PFDR.D5 5 Port F Data Register bit 5
PFDR.D4 4 Port F Data Register bit 4
PFDR.D3 3 Port F Data Register bit 3
PFDR.D2 2 Port F Data Register bit 2
PFDR.D1 1 Port F Data Register bit 1
PFDR.D0 0 Port F Data Register bit 0
PFDDR 0x0010 Port F Data Direction Register
PFDDR.DD7 7 Port F Data Direction Register bit 7
PFDDR.DD6 6 Port F Data Direction Register bit 6
PFDDR.DD5 5 Port F Data Direction Register bit 5
PFDDR.DD4 4 Port F Data Direction Register bit 4
PFDDR.DD3 3 Port F Data Direction Register bit 3
PFDDR.DD2 2 Port F Data Direction Register bit 2
PFDDR.DD1 1 Port F Data Direction Register bit 1
PFDDR.DD0 0 Port F Data Direction Register bit 0
PFOR 0x0011 Port F Option Register
PFOR.O7 7 Port F Option Register bit 7
PFOR.O6 6 Port F Option Register bit 6
PFOR.O5 5 Port F Option Register bit 5
PFOR.O4 4 Port F Option Register bit 4
PFOR.O3 3 Port F Option Register bit 3
PFOR.O2 2 Port F Option Register bit 2
PFOR.O1 1 Port F Option Register bit 1
PFOR.O0 0 Port F Option Register bit 0
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7 SPI Data I/O Register bit 7
SPIDR.D6 6 SPI Data I/O Register bit 6
SPIDR.D5 5 SPI Data I/O Register bit 5
SPIDR.D4 4 SPI Data I/O Register bit 4
SPIDR.D3 3 SPI Data I/O Register bit 3
SPIDR.D2 2 SPI Data I/O Register bit 2
SPIDR.D1 1 SPI Data I/O Register bit 1
SPIDR.D0 0 SPI Data I/O Register bit 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0023 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral data transfer flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
FCSR 0x0024 Flash control/Status Register
FCSR.B7 7 Flash control/Status Register Bit 7
FCSR.B6 6 Flash control/Status Register Bit 6
FCSR.B5 5 Flash control/Status Register Bit 5
FCSR.B4 4 Flash control/Status Register Bit 4
FCSR.B3 3 Flash control/Status Register Bit 3
FCSR.B2 2 Flash control/Status Register Bit 2
FCSR.B1 1 Flash control/Status Register Bit 1
FCSR.B0 0 Flash control/Status Register Bit 0
ISPR0 0x0025 Interrupt Software Priority Register 0
ISPR0.I1_3 7 Interrupt Software Priority register 0 I1_3
ISPR0.I0_3 6 Interrupt Software Priority register 0 I0_3
ISPR0.I1_2 5 Interrupt Software Priority register 0 I1_2
ISPR0.I0_2 4 Interrupt Software Priority register 0 I0_2
ISPR0.I1_1 3 Interrupt Software Priority register 0 I1_1
ISPR0.I0_1 2 Interrupt Software Priority register 0 I0_1
ISPR0.I1_0 1 Interrupt Software Priority register 0 I1_0
ISPR0.I0_0 0 Interrupt Software Priority register 0 I0_0
ISPR1 0x0026 Interrupt Software Priority Register 1
ISPR1.I1_7 7 Interrupt Software Priority register 1 I1_7
ISPR1.I0_7 6 Interrupt Software Priority register 1 I0_7
ISPR1.I1_6 5 Interrupt Software Priority register 1 I1_6
ISPR1.I0_6 4 Interrupt Software Priority register 1 I0_6
ISPR1.I1_5 3 Interrupt Software Priority register 1 I1_5
ISPR1.I0_5 2 Interrupt Software Priority register 1 I0_5
ISPR1.I1_4 1 Interrupt Software Priority register 1 I1_4
ISPR1.I0_4 0 Interrupt Software Priority register 1 I0_4
ISPR2 0x0027 Interrupt Software Priority Register 2
ISPR2.I1_11 7 Interrupt Software Priority register 2 I1_11
ISPR2.I0_11 6 Interrupt Software Priority register 2 I0_11
ISPR2.I1_10 5 Interrupt Software Priority register 2 I1_10
ISPR2.I0_10 4 Interrupt Software Priority register 2 I0_10
ISPR2.I1_9 3 Interrupt Software Priority register 2 I1_9
ISPR2.I0_9 2 Interrupt Software Priority register 2 I0_9
ISPR2.I1_8 1 Interrupt Software Priority register 2 I1_8
ISPR2.I0_8 0 Interrupt Software Priority register 2 I0_8
ISPR3 0x0028 Interrupt Software Priority Register 3
ISPR3.B7 7 Interrupt Software Priority register 3 Bit 7
ISPR3.B6 6 Interrupt Software Priority register 3 Bit 6
ISPR3.B5 5 Interrupt Software Priority register 3 Bit 5
ISPR3.B4 4 Interrupt Software Priority register 3 Bit 4
ISPR3.I1_13 3 Interrupt Software Priority register 3 I1_13
ISPR3.I0_13 2 Interrupt Software Priority register 3 I0_13
ISPR3.I1_12 1 Interrupt Software Priority register 3 I1_12
ISPR3.I0_12 0 Interrupt Software Priority register 3 I0_12
EICR0 0x0029 External Interrupt Control Registor 0
EICR0.IS31 7 EI3 Sensitivity Bit IS31
EICR0.IS30 6 EI3 Sensitivity Bit IS30
EICR0.IS21 5 EI2 Sensitivity Bit IS31
EICR0.IS20 4 EI2 Sensitivity Bit IS30
EICR0.IS11 3 EI1 Sensitivity Bit IS31
EICR0.IS10 2 EI1 Sensitivity Bit IS30
EICR0.IS01 1 EI0 Sensitivity Bit IS31
EICR0.IS00 0 EI0 Sensitivity Bit IS30
EICR1 0x002A External Interrupt Control Registor 0
EICR1.TLIS 1 Top Level Interrupt Sensitivity
EICR1.TLIE 0 Top Level Interrupt Enable
AWUCS 0x002B AWUFH Control/Status Register
AWUCS.AWUF 2 Auto Wake-Up Flag
AWUCS.AWUM 1 Auto Wake-Up Measurement
AWUCS.AWUEN 0 Auto Wake-Up From Halt Enabled
AWUPR 0x002C AWUFH Control/Status Register
AWUPR.PR7 7 Auto Wake-Up Prescaler Bit 7
AWUPR.PR6 6 Auto Wake-Up Prescaler Bit 6
AWUPR.PR5 5 Auto Wake-Up Prescaler Bit 5
AWUPR.PR4 4 Auto Wake-Up Prescaler Bit 4
AWUPR.PR3 3 Auto Wake-Up Prescaler Bit 3
AWUPR.PR2 2 Auto Wake-Up Prescaler Bit 2
AWUPR.PR1 1 Auto Wake-Up Prescaler Bit 1
AWUPR.PR0 0 Auto Wake-Up Prescaler Bit 0
SICSR 0x002D System Integrity control / Status Register
SICSR.AVDIE 6 Voltage Detector Interrupt Enable
SICSR.AVDF 5 Voltage Detector Flag
SICSR.LVDRF 4 LVD Reset Flag
SICSR.WDGRF 0 Watchdog Reset Flag
MCCSR 0x002E Main Clock Control /Status Register
MCCSR.MCO 7 Main Clock Out Selection
MCCSR.CP1 6 CPU Clock Prescaler 1
MCCSR.CP0 5 CPU Clock Prescaler 0
MCCSR.SMS 4 Slow mode Select
MCCSR.TB1 3 Time Base Control 1
MCCSR.TB0 2 Time Base Control 0
MCCSR.OIE 1 Oscillator Interrupt Enable
MCCSR.OIF 0 Main Clock Out Selection
WDGCR 0x002F Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
WDGWR 0x0030 Window wathcdog Register
WDGWR.W6 6 Window Value Bit 6
WDGWR.W5 5 Window Value Bit 5
WDGWR.W4 4 Window Value Bit 4
WDGWR.W3 3 Window Value Bit 3
WDGWR.W2 2 Window Value Bit 2
WDGWR.W1 1 Window Value Bit 1
WDGWR.W0 0 Window Value Bit 0
PWMDCR3 0x0031 PWM AR Timer Duty Cycle Register 3
PWMDCR3.DC7 7 Duty Cycle Data 7
PWMDCR3.DC6 6 Duty Cycle Data 6
PWMDCR3.DC5 5 Duty Cycle Data 5
PWMDCR3.DC4 4 Duty Cycle Data 4
PWMDCR3.DC3 3 Duty Cycle Data 3
PWMDCR3.DC2 2 Duty Cycle Data 2
PWMDCR3.DC1 1 Duty Cycle Data 1
PWMDCR3.DC0 0 Duty Cycle Data 0
PWMDCR2 0x0032 PWM AR Timer Duty Cycle Register 2
PWMDCR2.DC7 7 Duty Cycle Data 7
PWMDCR2.DC6 6 Duty Cycle Data 6
PWMDCR2.DC5 5 Duty Cycle Data 5
PWMDCR2.DC4 4 Duty Cycle Data 4
PWMDCR2.DC3 3 Duty Cycle Data 3
PWMDCR2.DC2 2 Duty Cycle Data 2
PWMDCR2.DC1 1 Duty Cycle Data 1
PWMDCR2.DC0 0 Duty Cycle Data 0
PWMDCR1 0x0033 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0034 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0035 PWM Control Register
PWMCR.OE3 7 PWM Output Enable 3
PWMCR.OE2 6 PWM Output Enable 2
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP3 3 PWM Output Polarity 3
PWMCR.OP2 2 PWM Output Polarity 2
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0036 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0037 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0038 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x0039 ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x003A ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x003B ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
T8CR2 0x003C Timer 8 bit Control Register 2
T8CR2.ICIE 7 Input Captre Interrupt Enable
T8CR2.OCIE 6 OutPut Compare Interrupt Enable
T8CR2.TOIE 5 Timer Overflow Interrupt Enable
T8CR2.FOLV2 4 Forced Output Compare 2
T8CR2.FOLV1 3 Forced Output Compare 1
T8CR2.OLVL2 2 Output Level 2
T8CR2.IEDG1 1 Input Edge 1
T8CR2.OLVL1 0 Output Level 1
T8CR1 0x003D Timer 8 bit Control Register 1
T8CR1.OC1E 7 Output Compare 1 Pin Enable
T8CR1.OC2E 6 Output Compare 2 Pin Enable
T8CR1.OPM 5 One Pulse mode
T8CR1.PWM 4 Pulse Width Modulation
T8CR1.CC1 3 Clock Control 1
T8CR1.CC0 2 Clock Control 0
T8CR1.IEDG2 1 Input Edge 2
T8CSR 0x003E Timer 8 bit Control Status Register
T8CSR.ICF1 7 Input Capture Flag 1
T8CSR.OCF1 6 Output Compare Flag 1
T8CSR.TOF 5 Timer Overflow Flag
T8CSR.ICF2 4 Input Capture Flag 2
T8CSR.OCF2 3 Output Compare Flag 2
T8CSR.TIMD 2 Timer Disable
T8IC1R 0x003F Timer 8 bit Input Capture 1 Register
T8IC1R.IC1R7 7 Input capture counter bit 7
T8IC1R.IC1R6 6 Input capture counter bit 6
T8IC1R.IC1R5 5 Input capture counter bit 5
T8IC1R.IC1R4 4 Input capture counter bit 4
T8IC1R.IC1R3 3 Input capture counter bit 3
T8IC1R.IC1R2 2 Input capture counter bit 2
T8IC1R.IC1R1 1 Input capture counter bit 1
T8IC1R.IC1R0 0 Input capture counter bit 0
T8OC1R 0x0040 Timer 8 bit Output Capture 1 Register
T8OC1R.OC1R7 7 Output capture counter bit 7
T8OC1R.OC1R6 6 Output capture counter bit 6
T8OC1R.OC1R5 5 Output capture counter bit 5
T8OC1R.OC1R4 4 Output capture counter bit 4
T8OC1R.OC1R3 3 Output capture counter bit 3
T8OC1R.OC1R2 2 Output capture counter bit 2
T8OC1R.OC1R1 1 Output capture counter bit 1
T8OC1R.OC1R0 0 Output capture counter bit 0
T8CTR 0x0041 Timer 8 bit Counter Register
T8CTR.CTR7 7 Output capture counter bit 7
T8CTR.CTR6 6 Output capture counter bit 6
T8CTR.CTR5 5 Output capture counter bit 5
T8CTR.CTR4 4 Output capture counter bit 4
T8CTR.CTR3 3 Output capture counter bit 3
T8CTR.CTR2 2 Output capture counter bit 2
T8CTR.CTR1 1 Output capture counter bit 1
T8CTR.CTR0 0 Output capture counter bit 0
T8ACTR 0x0042 Timer 8 bit Alternate Counter Register
T8ACTR.ACTR7 7 Alternate Output capture counter bit 7
T8ACTR.ACTR6 6 Alternate Output capture counter bit 6
T8ACTR.ACTR5 5 Alternate Output capture counter bit 5
T8ACTR.ACTR4 4 Alternate Output capture counter bit 4
T8ACTR.ACTR3 3 Alternate Output capture counter bit 3
T8ACTR.ACTR2 2 Alternate Output capture counter bit 2
T8ACTR.ACTR1 1 Alternate Output capture counter bit 1
T8ACTR.ACTR0 0 Alternate Output capture counter bit 0
T8IC2R 0x0043 Timer 8 bit Input Capture 2 Register
T8IC2R.IC2R7 7 Input capture counter bit 7
T8IC2R.IC2R6 6 Input capture counter bit 6
T8IC2R.IC2R5 5 Input capture counter bit 5
T8IC2R.IC2R4 4 Input capture counter bit 4
T8IC2R.IC2R3 3 Input capture counter bit 3
T8IC2R.IC2R2 2 Input capture counter bit 2
T8IC2R.IC2R1 1 Input capture counter bit 1
T8IC2R.IC2R0 0 Input capture counter bit 0
T8OC2R 0x0044 Timer 8 bit Output Capture 2 Register
T8OC2R.OC2R7 7 Output capture counter bit 7
T8OC2R.OC2R6 6 Output capture counter bit 6
T8OC2R.OC2R5 5 Output capture counter bit 5
T8OC2R.OC2R4 4 Output capture counter bit 4
T8OC2R.OC2R3 3 Output capture counter bit 3
T8OC2R.OC2R2 2 Output capture counter bit 2
T8OC2R.OC2R1 1 Output capture counter bit 1
T8OC2R.OC2R0 0 Output capture counter bit 0
ADCCSR 0x0045 ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.SLOW 4 A/D Clock Selection
ADCCSR.CH3 3 Channel Selection 3
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
ADCDRH 0x0046 A/D CONVERTER Data Register MSB
ADCDRH.D7 7 MSB Analog Converted Value 7
ADCDRH.D6 6 MSB Analog Converted Value 6
ADCDRH.D5 5 MSB Analog Converted Value 5
ADCDRH.D4 4 MSB Analog Converted Value 4
ADCDRH.D3 3 MSB Analog Converted Value 3
ADCDRH.D2 2 MSB Analog Converted Value 2
ADCDRH.D1 1 MSB Analog Converted Value 1
ADCDRH.D0 0 MSB Analog Converted Value 0
ADCDRL 0x0047 A/D CONVERTER Data Register LSB
ADCDRL.D7 7 LSB Analog Converted Value 7
ADCDRL.D6 6 LSB Analog Converted Value 6
ADCDRL.D5 5 LSB Analog Converted Value 5
ADCDRL.D4 4 LSB Analog Converted Value 4
ADCDRL.D3 3 LSB Analog Converted Value 3
ADCDRL.D2 2 LSB Analog Converted Value 2
ADCDRL.D1 1 LSB Analog Converted Value 1
ADCDRL.D0 0 LSB Analog Converted Value 0
SCISR 0x0048 LIN SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCISR.PE 0 Parity error
SCIDR 0x0049 LIN SCI Data register
SCIDR.DR7 7 LIN SCI Data register bit 7
SCIDR.DR6 6 LIN SCI Data register bit 6
SCIDR.DR5 5 LIN SCI Data register bit 5
SCIDR.DR4 4 LIN SCI Data register bit 4
SCIDR.DR3 3 LIN SCI Data register bit 3
SCIDR.DR2 2 LIN SCI Data register bit 2
SCIDR.DR1 1 LIN SCI Data register bit 1
SCIDR.DR0 0 LIN SCI Data register bit 0
SCIBRR 0x004A SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x004B SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.SCID 5 Disabled for low power consumption
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR1.PCE 2 Parity control enable
SCICR1.PS 1 Parity selection
SCICR1.PIE 0 Parity interrupt enable
SCICR2 0x004C SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
SCICR3 0x004D SCI Control Register 2
SCICR3.LINE 6 LIN Mode Enable
SCICR3.CLKEN 3 Clock Enable
SCICR3.CPOL 2 Clock Polarity
SCICR3.CPHA 1 CPHA Clock phase
SCICR3.LBCL 0 Last bit clock pulse
SCIERPR 0x004E SCI Extended Receive Prescaler register
SCIERPR.ERPR7 7 SCI Extended Receive Prescaler register bit 7
SCIERPR.ERPR6 6 SCI Extended Receive Prescaler register bit 6
SCIERPR.ERPR5 5 SCI Extended Receive Prescaler register bit 5
SCIERPR.ERPR4 4 SCI Extended Receive Prescaler register bit 4
SCIERPR.ERPR3 3 SCI Extended Receive Prescaler register bit 3
SCIERPR.ERPR2 2 SCI Extended Receive Prescaler register bit 2
SCIERPR.ERPR1 1 SCI Extended Receive Prescaler register bit 1
SCIERPR.ERPR0 0 SCI Extended Receive Prescaler register bit 0
SCIETPR 0x004F SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 SCI Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 SCI Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 SCI Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 SCI Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 SCI Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 SCI Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 SCI Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 SCI Extended Transmit Prescaler Register bit 0
RESERVED0050 0x0050 RESERVED
T16CR2 0x0051 Timer 16 Control Register 2
T16CR2.OC1E 7 Output Compare 1 Pin Enable
T16CR2.OC2E 6 Output Compare 2 Pin Enable
T16CR2.OPM 5 One Pulse mode
T16CR2.PWM 4 Pulse Width Modulation
T16CR2.CC1 3 Clock Control 1
T16CR2.CC0 2 Clock Control 0
T16CR2.IEDG2 1 Input Edge 2
T16CR2.EXEDG 0 External Clock Edge
T16CR1 0x0052 Timer A Control Register 1
T16CR1.ICIE 7 Input Capture Interrupt Enable
T16CR1.OCIE 6 Output Compare Interrupt Enable
T16CR1.TOIE 5 Timer Overflow Interrupt Enable
T16CR1.FOLV2 4 Forced Output Compare 2
T16CR1.FOLV1 3 Forced Output Compare 1
T16CR1.OLVL2 2 Output Level 2
T16CR1.IEDG1 1 Input Edge 1
T16CR1.OLVL1 0 Output Level 1
T16CSR 0x0053 Timer A Status Register
T16CSR.ICF1 7 Input Capture Flag 1
T16CSR.OCF1 6 Output Compare Flag 1
T16CSR.TOF 5 Timer Overflow Flag
T16CSR.ICF2 4 Input Capture Flag 2
T16CSR.OCF2 3 Output Compare Flag 2
T16IC1HR 0x0054 Timer A Input Capture 1 High Register
T16IC1LR 0x0055 Timer A Input Capture 1 Low Register
T16OC1HR 0x0056 Timer A Output Compare 1 High Register
T16OC1LR 0x0057 Timer A Output Compare 1 Low Register
T16CHR 0x0058 Timer A Counter High Register
T16CLR 0x0059 Timer A Counter Low Register
T16ACHR 0x005A Timer A Alternate Counter High Register
T16ACLR 0x005B Timer A Alternate Counter Low Register
T16IC2HR 0x005C Timer A Input Capture 2 High Register
T16IC2LR 0x005D Timer A Input Capture 2 Low Register
T16OC2HR 0x005E Timer A Output Compare 2 High Register
T16OC2LR 0x005F Timer A Output Compare 2 Low Register
SCI2SR 0x0060 LIN SCI Status Register (MASTER ONLY)
SCI2SR.TDRE 7 Transmit data register empty
SCI2SR.TC 6 Transmission complete
SCI2SR.RDRF 5 Received data ready flag
SCI2SR.IDLE 4 Idle line detect
SCI2SR.OR 3 Overrun error
SCI2SR.NF 2 Noise flag
SCI2SR.FE 1 Framing error
SCI2SR.PE 0 Parity error
SCI2DR 0x0061 LIN SCI Data register (MASTER ONLY)
SCI2DR.DR7 7 LIN SCI Data register bit 7
SCI2DR.DR6 6 LIN SCI Data register bit 6
SCI2DR.DR5 5 LIN SCI Data register bit 5
SCI2DR.DR4 4 LIN SCI Data register bit 4
SCI2DR.DR3 3 LIN SCI Data register bit 3
SCI2DR.DR2 2 LIN SCI Data register bit 2
SCI2DR.DR1 1 LIN SCI Data register bit 1
SCI2DR.DR0 0 LIN SCI Data register bit 0
SCI2BRR 0x0062 SCI Baud Rate Register (MASTER ONLY)
SCI2BRR.SCP1 7 First SCI Prescaler 1
SCI2BRR.SCP0 6 First SCI Prescaler 0
SCI2BRR.SCT2 5 SCI Transmitter rate divisor 2
SCI2BRR.SCT1 4 SCI Transmitter rate divisor 1
SCI2BRR.SCT0 3 SCI Transmitter rate divisor 0
SCI2BRR.SCR2 2 SCI Receiver rate divisor 2
SCI2BRR.SCR1 1 SCI Receiver rate divisor 1
SCI2BRR.SCR0 0 SCI Receiver rate divisor 0
SCI2CR1 0x0063 SCI Control Register 1 (MASTER ONLY)
SCI2CR1.R8 7 Receive data bit 8
SCI2CR1.T8 6 Transmit data bit 8
SCI2CR1.SCID 5 Disabled for low power consumption
SCI2CR1.M 4 Word length
SCI2CR1.WAKE 3 Wake-Up method
SCI2CR1.PCE 2 Parity control enable
SCI2CR1.PS 1 Parity selection
SCI2CR1.PIE 0 Parity interrupt enable
SCI2CR2 0x0064 SCI Control Register 2 (MASTER ONLY)
SCI2CR2.TIE 7 Transmitter interrupt enable
SCI2CR2.TCIE 6 Transmission complete interrupt enable
SCI2CR2.RIE 5 Receiver interrupt enable
SCI2CR2.ILIE 4 Idle line interrupt enable
SCI2CR2.TE 3 Transmitter enable
SCI2CR2.RE 2 Receiver enable
SCI2CR2.RWU 1 Receiver wake-up
SCI2CR2.SBK 0 Send break
SCI2CR3 0x0065 SCI Control Register 2 (MASTER ONLY)
SCI2CR3.LINE 6 LIN Mode Enable
SCI2CR3.CLKEN 3 Clock Enable
SCI2CR3.CPOL 2 Clock Polarity
SCI2CR3.CPHA 1 CPHA Clock phase
SCI2CR3.LBCL 0 Last bit clock pulse
SCI2ERPR 0x0066 SCI Extended Receive Prescaler register (MASTER ONLY)
SCI2ERPR.ERPR7 7 SCI Extended Receive Prescaler register bit 7
SCI2ERPR.ERPR6 6 SCI Extended Receive Prescaler register bit 6
SCI2ERPR.ERPR5 5 SCI Extended Receive Prescaler register bit 5
SCI2ERPR.ERPR4 4 SCI Extended Receive Prescaler register bit 4
SCI2ERPR.ERPR3 3 SCI Extended Receive Prescaler register bit 3
SCI2ERPR.ERPR2 2 SCI Extended Receive Prescaler register bit 2
SCI2ERPR.ERPR1 1 SCI Extended Receive Prescaler register bit 1
SCI2ERPR.ERPR0 0 SCI Extended Receive Prescaler register bit 0
SCI2ETPR 0x0067 SCI Extended Transmit Prescaler Register (MASTER ONLY)
SCI2ETPR.ETPR7 7 SCI Extended Transmit Prescaler Register bit 7
SCI2ETPR.ETPR6 6 SCI Extended Transmit Prescaler Register bit 6
SCI2ETPR.ETPR5 5 SCI Extended Transmit Prescaler Register bit 5
SCI2ETPR.ETPR4 4 SCI Extended Transmit Prescaler Register bit 4
SCI2ETPR.ETPR3 3 SCI Extended Transmit Prescaler Register bit 3
SCI2ETPR.ETPR2 2 SCI Extended Transmit Prescaler Register bit 2
SCI2ETPR.ETPR1 1 SCI Extended Transmit Prescaler Register bit 1
SCI2ETPR.ETPR0 0 SCI Extended Transmit Prescaler Register bit 0
CANCMCR 0x0068 CAN Master Control Register
CANCMCR.ABOM 6 CAN Automatic Bus-off Management
CANCMCR.AWUM 5 CAN Automatic Wake-Up Mode
CANCMCR.NART 4 CAN No Automatic Retransmission
CANCMCR.RFLM 3 CAN Receive FIF Locked Mode
CANCMCR.TXFP 2 CAN Transmit FIFO Priority
CANCMCR.SLEEP 1 CAN Sleep Mode Request
CANCMCR.INRQ 0 CAN Initialization Request
CANCMSR 0x0069 CAN Master Status Register
CANCMSR.REC 5 CAN Recieve
CANCMSR.TRAN 4 CAN Transmit
CANCMSR.WKUI 3 CAN Wake-up Interrupt
CANCMSR.ERRI 2 CAN Error Interrupt
CANCMSR.SLAK 1 CAN Sleep Acknowledge
CANCMSR.INAK 0 CAN Initialization Acknowledge
CANCTSR 0x006A CAN Transmit status Register
CANCTSR.TXOK1 5 CAN Tranmission OK for Mailbox1
CANCTSR.TXOK0 4 CAN Tranmission OK for Mailbox0
CANCTSR.RQCP1 1 CAN Request Completed for Mailbox 1
CANCTSR.RQCP0 0 CAN Request Completed for Mailbox 0
CANCTPR 0x006B CAN Transmit priority Register
CANCTPR.LOW1 6 CAN Lowest Priority Flag for Mailbox 1
CANCTPR.LOW0 5 CAN Lowest Priority Flag for Mailbox 0
CANCTPR.TME1 3 CAN Transmit Mailbox 1 Empty
CANCTPR.TME0 2 CAN Transmit Mailbox 0 Empty
CANCTPR.CODE 0 CAN Mailbox Code
CANCRFR 0x006C CAN Receive FIFO Register
CANCRFR.RFOM 5 CAN Release FIFO Output Mailbox
CANCRFR.FOVR 4 CAN FIFO Overrun
CANCRFR.FULL 3 CAN FIFO Full
CANCRFR.FMP1 1 CAN FIFO Message Pending 1
CANCRFR.FMP0 0 CAN FIFO Message Pending 0
CANCIER 0x006D CAN Interrupt Enable Register
CANCIER.WKUIE 7 CAN Wake-Up Interrupt Enable
CANCIER.FOVIE 3 CAN FIFO Overrun Interrupt Enable
CANCIER.FFIE 2 CAN FIFO Full Interrupt Enable
CANCIER.FMPIE 1 CAN FIFO Message Pending Interrupt Enable
CANCIER.TMEIE 0 CAN Transmit Mailbox Empty Interrupt Enable
CANCDGR 0x006E CAN Diagnosis Register
CANCDGR.RX 3 CAN Rx Signal
CANCDGR.SAMP 2 CAN Last Sample Point
CANCDGR.SILM 1 CAN Silent Mode
CANCDGR.LBKM 0 CAN Loop Back Mode
CANCPSR 0x006F CAN Page selection Register
CANCPSR.FPS2 2 CAN Page Select 2
CANCPSR.FPS1 1 CAN Page Select 1
CANCPSR.FPS0 0 CAN Page Select 0
; CAN PAGE 0
CANP0MCSR 0x0070 Mailbox control status register
CANP0MCSR.TERR 5 Transmission Error
CANP0MCSR.ALST 4 Arbitration Lost
CANP0MCSR.TXOK 3 Transmission OK
CANP0MCSR.RQCP 2 Request Completed
CANP0MCSR.ABRQ 1 Abort Request for Mailbox
CANP0MCSR.TXRQ 0 Transmit Mailbox Request
CANP0MDLC 0x0071 Mailbox control status register
CANP0MDLC.DLC3 3 Data Length Code3
CANP0MDLC.DLC2 2 Data Length Code2
CANP0MDLC.DLC1 1 Data Length Code1
CANP0MDLC.DLC0 0 Data Length Code0
CANP0MIDR0 0x0072 MailBox Identifier Registers 0
CANP0MIDR0.IDE 6 Extended Identifier
CANP0MIDR0.RTR 5 Remote Transmission Request
CANP0MIDR0.STID10 4 Standard Identifier 10
CANP0MIDR0.STID9 3 Standard Identifier 9
CANP0MIDR0.STID8 2 Standard Identifier 8
CANP0MIDR0.STID7 1 Standard Identifier 7
CANP0MIDR0.STID6 0 Standard Identifier 6
CANP0MIDR1 0x0073 MailBox Identifier Registers 1
CANP0MIDR1.STID5 7 Standard Identifier 5
CANP0MIDR1.STID4 6 Standard Identifier 4
CANP0MIDR1.STID3 5 Standard Identifier 3
CANP0MIDR1.STID2 4 Standard Identifier 2
CANP0MIDR1.STID1 3 Standard Identifier 1
CANP0MIDR1.STID0 2 Standard Identifier 0
CANP0MIDR1.EXID17 1 Extended Identifier 17
CANP0MIDR1.EXID16 0 Extended Identifier 16
CANP0MIDR2 0x0074 MailBox Extended Identifier Registers 2
CANP0MIDR2.EXID15 7 Extended Identifier 15
CANP0MIDR2.EXID14 6 Extended Identifier 14
CANP0MIDR2.EXID13 5 Extended Identifier 13
CANP0MIDR2.EXID12 4 Extended Identifier 12
CANP0MIDR2.EXID11 3 Extended Identifier 11
CANP0MIDR2.EXID10 2 Extended Identifier 10
CANP0MIDR2.EXID9 1 Extended Identifier 9
CANP0MIDR2.EXID8 0 Extended Identifier 8
CANP0MIDR3 0x0075 MailBox Extended Identifier Registers 3
CANP0MIDR3.EXID7 7 Extended Identifier 7
CANP0MIDR3.EXID6 6 Extended Identifier 6
CANP0MIDR3.EXID5 5 Extended Identifier 5
CANP0MIDR3.EXID4 4 Extended Identifier 4
CANP0MIDR3.EXID3 3 Extended Identifier 3
CANP0MIDR3.EXID2 2 Extended Identifier 2
CANP0MIDR3.EXID1 1 Extended Identifier 1
CANP0MIDR3.EXID0 0 Extended Identifier 0
CANP0MDAR0 0x0076 MailBox Data Registers 0
CANP0MDAR0.DATA7 7 DATA 7
CANP0MDAR0.DATA6 6 DATA 6
CANP0MDAR0.DATA5 5 DATA 5
CANP0MDAR0.DATA4 4 DATA 4
CANP0MDAR0.DATA3 3 DATA 3
CANP0MDAR0.DATA2 2 DATA 2
CANP0MDAR0.DATA1 1 DATA 1
CANP0MDAR0.DATA0 0 DATA 0
CANP0MDAR1 0x0077 MailBox Data Registers 1
CANP0MDAR1.DATA7 7 DATA 7
CANP0MDAR1.DATA6 6 DATA 6
CANP0MDAR1.DATA5 5 DATA 5
CANP0MDAR1.DATA4 4 DATA 4
CANP0MDAR1.DATA3 3 DATA 3
CANP0MDAR1.DATA2 2 DATA 2
CANP0MDAR1.DATA1 1 DATA 1
CANP0MDAR1.DATA0 0 DATA 0
CANP0MDAR2 0x0078 MailBox Data Registers 2
CANP0MDAR2.DATA7 7 DATA 7
CANP0MDAR2.DATA6 6 DATA 6
CANP0MDAR2.DATA5 5 DATA 5
CANP0MDAR2.DATA4 4 DATA 4
CANP0MDAR2.DATA3 3 DATA 3
CANP0MDAR2.DATA2 2 DATA 2
CANP0MDAR2.DATA1 1 DATA 1
CANP0MDAR2.DATA0 0 DATA 0
CANP0MDAR3 0x0079 MailBox Data Registers 3
CANP0MDAR3.DATA7 7 DATA 7
CANP0MDAR3.DATA6 6 DATA 6
CANP0MDAR3.DATA5 5 DATA 5
CANP0MDAR3.DATA4 4 DATA 4
CANP0MDAR3.DATA3 3 DATA 3
CANP0MDAR3.DATA2 2 DATA 2
CANP0MDAR3.DATA1 1 DATA 1
CANP0MDAR3.DATA0 0 DATA 0
CANP0MDAR4 0x007A MailBox Data Registers 4
CANP0MDAR4.DATA7 7 DATA 7
CANP0MDAR4.DATA6 6 DATA 6
CANP0MDAR4.DATA5 5 DATA 5
CANP0MDAR4.DATA4 4 DATA 4
CANP0MDAR4.DATA3 3 DATA 3
CANP0MDAR4.DATA2 2 DATA 2
CANP0MDAR4.DATA1 1 DATA 1
CANP0MDAR4.DATA0 0 DATA 0
CANP0MDAR5 0x007B MailBox Data Registers 5
CANP0MDAR5.DATA7 7 DATA 7
CANP0MDAR5.DATA6 6 DATA 6
CANP0MDAR5.DATA5 5 DATA 5
CANP0MDAR5.DATA4 4 DATA 4
CANP0MDAR5.DATA3 3 DATA 3
CANP0MDAR5.DATA2 2 DATA 2
CANP0MDAR5.DATA1 1 DATA 1
CANP0MDAR5.DATA0 0 DATA 0
CANP0MDAR6 0x007C MailBox Data Registers 6
CANP0MDAR6.DATA7 7 DATA 7
CANP0MDAR6.DATA6 6 DATA 6
CANP0MDAR6.DATA5 5 DATA 5
CANP0MDAR6.DATA4 4 DATA 4
CANP0MDAR6.DATA3 3 DATA 3
CANP0MDAR6.DATA2 2 DATA 2
CANP0MDAR6.DATA1 1 DATA 1
CANP0MDAR6.DATA0 0 DATA 0
CANP0MDAR7 0x007D MailBox Data Registers 7
CANP0MDAR7.DATA7 7 DATA 7
CANP0MDAR7.DATA6 6 DATA 6
CANP0MDAR7.DATA5 5 DATA 5
CANP0MDAR7.DATA4 4 DATA 4
CANP0MDAR7.DATA3 3 DATA 3
CANP0MDAR7.DATA2 2 DATA 2
CANP0MDAR7.DATA1 1 DATA 1
CANP0MDAR7.DATA0 0 DATA 0
CANP0MTSLR 0x007E Mtslow register
CANP0MTSLR.TIME7 7 TIME 7
CANP0MTSLR.TIME6 6 TIME 6
CANP0MTSLR.TIME5 5 TIME 5
CANP0MTSLR.TIME4 4 TIME 4
CANP0MTSLR.TIME3 3 TIME 3
CANP0MTSLR.TIME2 2 TIME 2
CANP0MTSLR.TIME1 1 TIME 1
CANP0MTSLR.TIME0 0 TIME 0
CANP0MTSHR 0x007F Mtslow register
CANP0MTSHR.TIME15 7 TIME 15
CANP0MTSHR.TIME14 6 TIME 14
CANP0MTSHR.TIME13 5 TIME 13
CANP0MTSHR.TIME12 4 TIME 12
CANP0MTSHR.TIME11 3 TIME 11
CANP0MTSHR.TIME10 2 TIME 10
CANP0MTSHR.TIME9 1 TIME 9
CANP0MTSHR.TIME8 0 TIME 8
.ST7261
; :ST7261 :ST72611F1 :ST72611F1B1 :ST72611F1M1 :ST72F611F1 :ST72F611F1B1 \
; :ST72P611F1
; http://us.st.com/stonline/books/pdf/docs/7212.pdf
; RAM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x000E
area BSS RESERVED 0x000E:0x0024
area DATA FSR_2 0x0024:0x0039
area BSS RESERVED 0x0039:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xF000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
RESERVED0004 0x0004 RESERVED
RESERVED0005 0x0005 RESERVED
RESERVED0006 0x0006 RESERVED
RESERVED0007 0x0007 RESERVED
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
RESERVED000A 0x000A RESERVED
RESERVED000B 0x000B RESERVED
RESERVED000C 0x000C RESERVED
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
RESERVED0032 0x0032 RESERVED
RESERVED0033 0x0033 RESERVED
RESERVED0034 0x0034 RESERVED
RESERVED0035 0x0035 RESERVED
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
.ST72621J2
; :ST72621J2 :ST72621J2M1 :ST72621J2T1 :ST72F621J2M1 :ST72F621J2T1 \
; :ST72P621J2M1 :ST72P621J2T1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=384
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x01C0
area BSS RESERVED 0x01C0:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
SPIDR 0x0011 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0012 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0013 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral Data Transfer Flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI Overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
SCIERPR 0x001D SCI Extended Receive Prescaler register
SCIERPR.ERPR7 7 SCI Extended Receive Prescaler register bit 7
SCIERPR.ERPR6 6 SCI Extended Receive Prescaler register bit 6
SCIERPR.ERPR5 5 SCI Extended Receive Prescaler register bit 5
SCIERPR.ERPR4 4 SCI Extended Receive Prescaler register bit 4
SCIERPR.ERPR3 3 SCI Extended Receive Prescaler register bit 3
SCIERPR.ERPR2 2 SCI Extended Receive Prescaler register bit 2
SCIERPR.ERPR1 1 SCI Extended Receive Prescaler register bit 1
SCIERPR.ERPR0 0 SCI Extended Receive Prescaler register bit 0
SCIETPR 0x001E SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 SCI Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 SCI Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 SCI Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 SCI Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 SCI Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 SCI Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 SCI Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 SCI Extended Transmit Prescaler Register bit 0
RESERVED001F 0x001F RESERVED
SCISR 0x0020 SCI Status register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCISR.PE 0 Parity error
SCIDR 0x0021 SCI Data register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0022 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0023 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.SCID 5 Disabled for low power consumption
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR1.PCE 2 Parity control enable
SCICR1.PS 1 Parity selection
SCICR1.PIE 0 Parity interrupt enable
SCICR2 0x0024 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72621J4
; :ST72621J4 :ST72621J4B1 :ST72621J4T1 :ST72F621J4B1 :ST72F621J4T1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=768
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x0340
area BSS RESERVED 0x0340:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
SPIDR 0x0011 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0012 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0013 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral Data Transfer Flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI Overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
SCIERPR 0x001D SCI Extended Receive Prescaler register
SCIERPR.ERPR7 7 SCI Extended Receive Prescaler register bit 7
SCIERPR.ERPR6 6 SCI Extended Receive Prescaler register bit 6
SCIERPR.ERPR5 5 SCI Extended Receive Prescaler register bit 5
SCIERPR.ERPR4 4 SCI Extended Receive Prescaler register bit 4
SCIERPR.ERPR3 3 SCI Extended Receive Prescaler register bit 3
SCIERPR.ERPR2 2 SCI Extended Receive Prescaler register bit 2
SCIERPR.ERPR1 1 SCI Extended Receive Prescaler register bit 1
SCIERPR.ERPR0 0 SCI Extended Receive Prescaler register bit 0
SCIETPR 0x001E SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 SCI Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 SCI Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 SCI Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 SCI Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 SCI Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 SCI Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 SCI Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 SCI Extended Transmit Prescaler Register bit 0
RESERVED001F 0x001F RESERVED
SCISR 0x0020 SCI Status register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCISR.PE 0 Parity error
SCIDR 0x0021 SCI Data register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0022 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0023 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.SCID 5 Disabled for low power consumption
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR1.PCE 2 Parity control enable
SCICR1.PS 1 Parity selection
SCICR1.PIE 0 Parity interrupt enable
SCICR2 0x0024 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72621K4
; :ST72621K4 :ST72621K4B1 :ST72621K4M1 :ST72F621K4B1 :ST72F621K4M1 :ST72P621K4M1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=768
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x0340
area BSS RESERVED 0x0340:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
SPIDR 0x0011 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0012 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0013 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral Data Transfer Flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI Overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
SCIERPR 0x001D SCI Extended Receive Prescaler register
SCIERPR.ERPR7 7 SCI Extended Receive Prescaler register bit 7
SCIERPR.ERPR6 6 SCI Extended Receive Prescaler register bit 6
SCIERPR.ERPR5 5 SCI Extended Receive Prescaler register bit 5
SCIERPR.ERPR4 4 SCI Extended Receive Prescaler register bit 4
SCIERPR.ERPR3 3 SCI Extended Receive Prescaler register bit 3
SCIERPR.ERPR2 2 SCI Extended Receive Prescaler register bit 2
SCIERPR.ERPR1 1 SCI Extended Receive Prescaler register bit 1
SCIERPR.ERPR0 0 SCI Extended Receive Prescaler register bit 0
SCIETPR 0x001E SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 SCI Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 SCI Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 SCI Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 SCI Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 SCI Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 SCI Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 SCI Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 SCI Extended Transmit Prescaler Register bit 0
RESERVED001F 0x001F RESERVED
SCISR 0x0020 SCI Status register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCISR.PE 0 Parity error
SCIDR 0x0021 SCI Data register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0022 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0023 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.SCID 5 Disabled for low power consumption
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR1.PCE 2 Parity control enable
SCICR1.PS 1 Parity selection
SCICR1.PIE 0 Parity interrupt enable
SCICR2 0x0024 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72621L4
; :ST72621L4 :ST72621L4B1 :ST72621L4M1 :ST72F621L4B1 :ST72F621L4M1 :ST72P621L4B1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=768
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x0340
area BSS RESERVED 0x0340:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
SPIDR 0x0011 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0012 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0013 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral Data Transfer Flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI Overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
SCIERPR 0x001D SCI Extended Receive Prescaler register
SCIERPR.ERPR7 7 SCI Extended Receive Prescaler register bit 7
SCIERPR.ERPR6 6 SCI Extended Receive Prescaler register bit 6
SCIERPR.ERPR5 5 SCI Extended Receive Prescaler register bit 5
SCIERPR.ERPR4 4 SCI Extended Receive Prescaler register bit 4
SCIERPR.ERPR3 3 SCI Extended Receive Prescaler register bit 3
SCIERPR.ERPR2 2 SCI Extended Receive Prescaler register bit 2
SCIERPR.ERPR1 1 SCI Extended Receive Prescaler register bit 1
SCIERPR.ERPR0 0 SCI Extended Receive Prescaler register bit 0
SCIETPR 0x001E SCI Extended Transmit Prescaler Register
SCIETPR.ETPR7 7 SCI Extended Transmit Prescaler Register bit 7
SCIETPR.ETPR6 6 SCI Extended Transmit Prescaler Register bit 6
SCIETPR.ETPR5 5 SCI Extended Transmit Prescaler Register bit 5
SCIETPR.ETPR4 4 SCI Extended Transmit Prescaler Register bit 4
SCIETPR.ETPR3 3 SCI Extended Transmit Prescaler Register bit 3
SCIETPR.ETPR2 2 SCI Extended Transmit Prescaler Register bit 2
SCIETPR.ETPR1 1 SCI Extended Transmit Prescaler Register bit 1
SCIETPR.ETPR0 0 SCI Extended Transmit Prescaler Register bit 0
RESERVED001F 0x001F RESERVED
SCISR 0x0020 SCI Status register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCISR.PE 0 Parity error
SCIDR 0x0021 SCI Data register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0022 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0023 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.SCID 5 Disabled for low power consumption
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR1.PCE 2 Parity control enable
SCICR1.PS 1 Parity selection
SCICR1.PIE 0 Parity interrupt enable
SCICR2 0x0024 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72622K2
; :ST72622K2 :ST72622K2M1 :ST72F622K2M1 :ST72P622K2M1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=384
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x01C0
area BSS RESERVED 0x01C0:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
SPIDR 0x0011 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0012 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0013 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral Data Transfer Flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI Overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
RESERVED0020 0x0020 RESERVED
RESERVED0021 0x0021 RESERVED
RESERVED0022 0x0022 RESERVED
RESERVED0023 0x0023 RESERVED
RESERVED0024 0x0024 RESERVED
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72622L2
; :ST72622L2 :ST72622L2B1 :ST72F622L2B1 :ST72P622L2B1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=384
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x01C0
area BSS RESERVED 0x01C0:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
SPIDR 0x0011 Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0012 Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPICSR 0x0013 SPI Control Status Register
SPICSR.SPIF 7 Serial Peripheral Data Transfer Flag
SPICSR.WCOL 6 Write Collision status
SPICSR.OVR 5 SPI Overrun error
SPICSR.MODF 4 Mode Fault flag
SPICSR.SOD 2 SPI Output Disable
SPICSR.SSM 1 SS Management
SPICSR.SSI 0 SS Internal Mode
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
RESERVED0020 0x0020 RESERVED
RESERVED0021 0x0021 RESERVED
RESERVED0022 0x0022 RESERVED
RESERVED0023 0x0023 RESERVED
RESERVED0024 0x0024 RESERVED
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72623F2
; :ST72623F2 :ST72623F2B1 :ST72623F2M1 :ST72623F2T1 :ST72F623F2B1 \
; :ST72F623F2M1 :ST72F623F2T1 :ST72P623F2B1 :ST72P623F2M1 :ST72P623F2T1
; http://us.st.com/stonline/books/pdf/docs/6996.pdf
; RAM=384
; MEMORY MAP
area DATA FSR_1 0x0000:0x003A
area BSS RESERVED 0x003A:0x0040
area DATA RAM_ 0x0040:0x01C0
area BSS RESERVED 0x01C0:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP software interrupt vector
interrupt FLASH_ 0xFFFA FLASH Start programming NMI interrupt vector
interrupt USB_ES 0xFFF8 USB End Suspend interrupt vector
interrupt Port_A 0xFFF6 Port A external interrupts IT[3:1]
interrupt Port_B 0xFFF4 Port B external interrupts IT[8:5]
interrupt Port_C 0xFFF2 Port C external interrupts IT[12:9]
interrupt TBU_ 0xFFF0 Timebase Unit interrupt vector
interrupt ART_PWM 0xFFEE ART/PWM Timer interrupt
interrupt SPI_ 0xFFEC SPI interrupt vector
interrupt SCI_ 0xFFEA SCI interrupt vector
interrupt USB_ 0xFFE8 USB interrupt vector
interrupt ADC_ 0xFFE6 A/D End of conversion interrupt
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PDDR 0x0006 Port D Data Register
PDDR.D7 7 Port C Data Register bit 7
PDDR.D6 6 Port C Data Register bit 6
PDDR.D5 5 Port C Data Register bit 5
PDDR.D4 4 Port C Data Register bit 4
PDDR.D3 3 Port C Data Register bit 3
PDDR.D2 2 Port C Data Register bit 2
PDDR.D1 1 Port C Data Register bit 1
PDDR.D0 0 Port C Data Register bit 0
PDDDR 0x0007 Port D Data Direction Register
PDDDR.DD7 7 Port C Data Direction Register bit 7
PDDDR.DD6 6 Port C Data Direction Register bit 6
PDDDR.DD5 5 Port C Data Direction Register bit 5
PDDDR.DD4 4 Port C Data Direction Register bit 4
PDDDR.DD3 3 Port C Data Direction Register bit 3
PDDDR.DD2 2 Port C Data Direction Register bit 2
PDDDR.DD1 1 Port C Data Direction Register bit 1
PDDDR.DD0 0 Port C Data Direction Register bit 0
ITRFRE1 0x0008 Interrupt Register 1
ITRFRE1.IT8E 7 Interrupt Enable 8
ITRFRE1.IT7E 6 Interrupt Enable 7
ITRFRE1.IT6E 5 Interrupt Enable 6
ITRFRE1.IT5E 4 Interrupt Enable 5
ITRFRE1.IT3E 2 Interrupt Enable 3
ITRFRE1.IT2E 1 Interrupt Enable 2
ITRFRE1.IT1E 0 Interrupt Enable 1
MISC 0x0009 Miscellaneous Register
MISC.SMS1 3 Slow Mode Selection 1
MISC.SMS0 2 Slow Mode Selection 0
MISC.USBOE 1 USB Output Enable
MISC.MCO 0 Main Clock Out
ADCDRMSB 0x000A ADC Data Register (bit 9:2)
ADCDRMSB.D9 7 MSB of Analog Converted Value 7
ADCDRMSB.D8 6 MSB of Analog Converted Value 6
ADCDRMSB.D7 5 MSB of Analog Converted Value 5
ADCDRMSB.D6 4 MSB of Analog Converted Value 4
ADCDRMSB.D5 3 MSB of Analog Converted Value 3
ADCDRMSB.D4 2 MSB of Analog Converted Value 2
ADCDRMSB.D3 1 MSB of Analog Converted Value 1
ADCDRMSB.D2 0 MSB of Analog Converted Value 0
ADCDRLSB 0x000B ADC Data Register (bit 1:0)
ADCDRLSB.D1 1 LSB of Analog Converted Value 1
ADCDRLSB.D0 0 LSB of Analog Converted Value 0
ADCCSR 0x000C ADC Control Status Register
ADCCSR.EOC 7 End of Conversion
ADCCSR.SPEED 6 ADC clock selection
ADCCSR.ADON 5 A/D Converter on
ADCCSR.ITE 4 Interrupt Enable
ADCCSR.ONESHOT 3 One Shot Conversion Selection
ADCCSR.CS2 2 Channel Selection 2
ADCCSR.CS1 1 Channel Selection 1
ADCCSR.CS0 0 Channel Selection 0
WDGCR 0x000D Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
RESERVED0011 0x0011 RESERVED
RESERVED0012 0x0012 RESERVED
RESERVED0013 0x0013 RESERVED
PWMDCR1 0x0014 PWM AR Timer Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0015 PWM AR Timer Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0016 PWM AR Timer Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0017 Auto-Reload Timer Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0018 Auto-Reload Timer Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0019 Auto-Reload Timer Auto-Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x001A ART Input Capture Control/Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x001B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
ARTICR2 0x001C ART Input Capture Register 2
ARTICR2.IC7 7 Input Capture Data 7
ARTICR2.IC6 6 Input Capture Data 6
ARTICR2.IC5 5 Input Capture Data 5
ARTICR2.IC4 4 Input Capture Data 4
ARTICR2.IC3 3 Input Capture Data 3
ARTICR2.IC2 2 Input Capture Data 2
ARTICR2.IC1 1 Input Capture Data 1
ARTICR2.IC0 0 Input Capture Data 0
RESERVED001D 0x001D RESERVED
RESERVED001E 0x001E RESERVED
RESERVED001F 0x001F RESERVED
RESERVED0020 0x0020 RESERVED
RESERVED0021 0x0021 RESERVED
RESERVED0022 0x0022 RESERVED
RESERVED0023 0x0023 RESERVED
RESERVED0024 0x0024 RESERVED
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.CTRL 7 Control
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP0RB.EA3 3 Endpoint addres 3
USBEP0RB.EA2 2 Endpoint addres 2
USBEP0RB.EA1 1 Endpoint addres 1
USBEP0RB.EA0 0 Endpoint addres 0
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
; RESERVED0032 0x0032 RESERVED
; RESERVED0033 0x0033 RESERVED
; RESERVED0034 0x0034 RESERVED
; RESERVED0035 0x0035 RESERVED
ITSPR0 0x0032 Interrupt Software Priority Register 0
ITSPR0.I1_3 7
ITSPR0.I0_3 6
ITSPR0.I1_2 5
ITSPR0.I0_2 4
ITSPR0.I1_1 3
ITSPR0.I0_1 2
ITSPR0.I1_0 1
ITSPR0.I0_0 0
ITSPR1 0x0033 Interrupt Software Priority Register 1
ITSPR1.I1_7 7
ITSPR1.I0_7 6
ITSPR1.I1_6 5
ITSPR1.I0_6 4
ITSPR1.I1_5 3
ITSPR1.I0_5 2
ITSPR1.I1_4 1
ITSPR1.I0_4 0
ITSPR2 0x0034 Interrupt Software Priority Register 2
ITSPR2.I1_11 7
ITSPR2.I0_11 6
ITSPR2.I1_10 5
ITSPR2.I0_10 4
ITSPR2.I1_9 3
ITSPR2.I0_9 2
ITSPR2.I1_8 1
ITSPR2.I0_8 0
ITSPR3 0x0035 Interrupt Software Priority Register 3
ITSPR3.I1_13 3
ITSPR3.I0_13 2
ITSPR3.I1_12 1
ITSPR3.I0_12 0
TBUCV 0x0036 TBU Counter Value Register
TBUCV.CV7 7 Counter Value 7
TBUCV.CV6 6 Counter Value 6
TBUCV.CV5 5 Counter Value 5
TBUCV.CV4 4 Counter Value 4
TBUCV.CV3 3 Counter Value 3
TBUCV.CV2 2 Counter Value 2
TBUCV.CV1 1 Counter Value 1
TBUCV.CV0 0 Counter Value 0
TBUCSR 0x0037 TBU Control/Status Register
TBUCSR.CAS 6 Cascading Enable
TBUCSR.OVF 5 Overflow Flag
TBUCSR.ITE 4 Interrupt enabled
TBUCSR.TCEN 3 TBU Enable
TBUCSR.PR2 2 Prescaler Selection 2
TBUCSR.PR1 1 Prescaler Selection 1
TBUCSR.PR0 0 Prescaler Selection 0
FCSR 0x0038 Flash Control Status Register
ITRFRE2 0x0039 Interrupt Register 2
ITRFRE2.CTL3 7 IT[12] Interrupt Sensitivity
ITRFRE2.CTL2 6 IT[11] Interrupt Sensitivity
ITRFRE2.CTL1 5 IT[10] Interrupt Sensitivity
ITRFRE2.CTL0 4 IT[9] Interrupt Sensitivity
ITRFRE2.IT12E 3 Interrupt 12 Enable
ITRFRE2.IT11E 2 Interrupt 11 Enable
ITRFRE2.IT10E 1 Interrupt 10 Enable
ITRFRE2.IT9E 0 Interrupt 9 Enable
.ST72631
; :ST72631K4 :ST72631K4B1 :ST72631K4M1 :ST72E631K4D0 :ST72T631K4B1 :ST72T631K4M1
; http://us.st.com/stonline/books/pdf/docs/6341.pdf
; RAM=512
; ROM_OTP=16K
; MEMORY MAP
area DATA FSR_1 0x0000:0x0040
area DATA RAM_ 0x0040:0x0240
area BSS RESERVED 0x0240:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt USB_ESM 0xFFFA USB End Suspend Mode Interrupt Vector
interrupt IT1_IT8 0xFFF8 IT1 to IT8 Interrupt Vector
interrupt TIMER_ 0xFFF6 TIMER Interrupt Vector
interrupt I2C_ 0xFFF4 I2C Interrupt Vector
interrupt SCI_ 0xFFF2 SCI Interrupt Vector
interrupt USB_ 0xFFF0 USB Interrupt Vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
RESERVED0006 0x0006 RESERVED
RESERVED0007 0x0007 RESERVED
ITIFRE 0x0008 Interrupt Register
ITIFRE.IT8E 7 Interrupt Enable Control Bit 7
ITIFRE.IT7E 6 Interrupt Enable Control Bit 6
ITIFRE.IT6E 5 Interrupt Enable Control Bit 5
ITIFRE.IT5E 4 Interrupt Enable Control Bit 4
ITIFRE.IT4E 3 Interrupt Enable Control Bit 3
ITIFRE.IT3E 2 Interrupt Enable Control Bit 2
ITIFRE.IT2E 1 Interrupt Enable Control Bit 1
ITIFRE.IT1E 0 Interrupt Enable Control Bit 0
MISCR 0x0009 Miscellaneous Register
MISCR.LVD 3 Low Voltage Detector
MISCR.CLKDIV 2 Clock Divider
MISCR.USBOE 1 USB enable
MISCR.MCO 0 Main Clock Out selection
ADCDR 0x000A A/D Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x000B A/D Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
WDGCR 0x000C Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000D 0x000D RESERVED
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
TIMCR2 0x0011 Timer Control Register 2
TIMCR2.OC1E 7 Output Compare 1 Pin Enable
TIMCR2.OC2E 6 Output Compare 2 Pin Enable
TIMCR2.OPM 5 One Pulse mode
TIMCR2.PWM 4 Pulse Width Modulation
TIMCR2.CC1 3 Clock Control 1
TIMCR2.CC0 2 Clock Control 0
TIMCR2.IEDG2 1 Input Edge 2
TIMCR2.EXEDG 0 External Clock Edge
TIMCR1 0x0012 Timer Control Register 1
TIMCR1.ICIE 7 Input Capture Interrupt Enable
TIMCR1.OCIE 6 Output Compare Interrupt Enable
TIMCR1.TOIE 5 Timer Overflow Interrupt Enable
TIMCR1.FOLV2 4 Forced Output Compare 2
TIMCR1.FOLV1 3 Forced Output Compare 1
TIMCR1.OLVL2 2 Output Level 2
TIMCR1.IEDG1 1 Input Edge 1
TIMCR1.OLVL1 0 Output Level 1
TIMSR 0x0013 Timer Status Register
TIMSR.ICF1 7 Input Capture Flag 1
TIMSR.OCF1 6 Output Compare Flag 1
TIMSR.TOF 5 Timer Overflow Flag
TIMSR.ICF2 4 Input Capture Flag 2
TIMSR.OCF2 3 Output Compare Flag 2
TIMIC1HR 0x0014 Timer Input Capture 1 High Register
TIMIC1LR 0x0015 Timer Input Capture 1 Low Register
TIMOC1HR 0x0016 Timer Output Compare 1 High Register
TIMOC1LR 0x0017 Timer Output Compare 1 Low Register
TIMCHR 0x0018 Timer Counter High Register
TIMCLR 0x0019 Timer Counter Low Register
TIMACHR 0x001A Timer Alternate Counter High Register
TIMACLR 0x001B Timer Alternate Counter Low Register
TIMIC2HR 0x001C Timer Input Capture 2 High Register
TIMIC2LR 0x001D Timer Input Capture 2 Low Register
TIMOC2HR 0x001E Timer Output Compare 2 High Register
TIMOC2LR 0x001F Timer Output Compare 2 Low Register
SCISR 0x0020 SCI Status register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0021 SCI Data register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0022 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0023 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0024 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
RESERVED0032 0x0032 RESERVED
RESERVED0033 0x0033 RESERVED
RESERVED0034 0x0034 RESERVED
RESERVED0035 0x0035 RESERVED
RESERVED0036 0x0036 RESERVED
RESERVED0037 0x0037 RESERVED
RESERVED0038 0x0038 RESERVED
I2CDR 0x0039 I2C Data Register
I2CDR.D7 7 I2C Data Register bit 7
I2CDR.D6 6 I2C Data Register bit 6
I2CDR.D5 5 I2C Data Register bit 5
I2CDR.D4 4 I2C Data Register bit 4
I2CDR.D3 3 I2C Data Register bit 3
I2CDR.D2 2 I2C Data Register bit 2
I2CDR.D1 1 I2C Data Register bit 1
I2CDR.D0 0 I2C Data Register bit 0
RESERVED003A 0x003A RESERVED
I2COAR 0x003B I2C (7 Bits) Slave Address Register
I2COAR.ADD7 7 Interface addres 7
I2COAR.ADD6 6 Interface addres 6
I2COAR.ADD5 5 Interface addres 5
I2COAR.ADD4 4 Interface addres 4
I2COAR.ADD3 3 Interface addres 3
I2COAR.ADD2 2 Interface addres 2
I2COAR.ADD1 1 Interface addres 1
I2COAR.ADD0 0 Address direction bit
I2CCCR 0x003C I2C Clock Control Register
I2CCCR.FM_SM 7 Fast/Standard I2C mode
I2CCCR.CC6 6 clock divider bit 6
I2CCCR.CC5 5 clock divider bit 5
I2CCCR.CC4 4 clock divider bit 4
I2CCCR.CC3 3 clock divider bit 3
I2CCCR.CC2 2 clock divider bit 2
I2CCCR.CC1 1 clock divider bit 1
I2CCCR.CC0 0 clock divider bit 0
I2CSR2 0x003D I2C 2nd Status Register
I2CSR2.AF 4 Acknowledge failure
I2CSR2.STOPF 3 Stop detection (Slave mode)
I2CSR2.ARLO 2 Arbitration lost
I2CSR2.BERR 1 Bus error
I2CSR2.GCAL 0 General Call (Slave mode)
I2CSR1 0x003E I2C 1st Status Register
I2CSR1.EVF 7 Event flag
I2CSR1.TRA 5 Transmitter/Receiver
I2CSR1.BUSY 4 Bus busy
I2CSR1.BTF 3 Byte transfer finished
I2CSR1.ADSL 2 Address matched (Slave mode)
I2CSR1.M_SL 1 Master/Slave
I2CSR1.SB 0 Start bit (Master mode)
I2CCR 0x003F I2C Control Register
I2CCR.PE 5 Peripheral enable
I2CCR.ENGC 4 Enable General Call
I2CCR.START 3 Generation of a Start condition
I2CCR.ACK 2 Acknowledge enable
I2CCR.STOP 1 Generation of a Stop condition
I2CCR.ITE 0 Interrupt enable
.ST72632
; :ST72632K2 :ST72632K2B1 :ST72632K2M1 :ST72T632K2B1 :ST72T632K2M1
; http://us.st.com/stonline/books/pdf/docs/6341.pdf
; RAM=256
; ROM_OTP=8K
; MEMORY MAP
area DATA FSR_1 0x0000:0x0040
area DATA RAM_ 0x0040:0x0140
area BSS RESERVED 0x0140:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt USB_ESM 0xFFFA USB End Suspend Mode Interrupt Vector
interrupt IT1_IT8 0xFFF8 IT1 to IT8 Interrupt Vector
interrupt TIMER_ 0xFFF6 TIMER Interrupt Vector
interrupt SCI_ 0xFFF2 SCI Interrupt Vector
interrupt USB_ 0xFFF0 USB Interrupt Vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
RESERVED0006 0x0006 RESERVED
RESERVED0007 0x0007 RESERVED
ITIFRE 0x0008 Interrupt Register
ITIFRE.IT8E 7 Interrupt Enable Control Bit 7
ITIFRE.IT7E 6 Interrupt Enable Control Bit 6
ITIFRE.IT6E 5 Interrupt Enable Control Bit 5
ITIFRE.IT5E 4 Interrupt Enable Control Bit 4
ITIFRE.IT4E 3 Interrupt Enable Control Bit 3
ITIFRE.IT3E 2 Interrupt Enable Control Bit 2
ITIFRE.IT2E 1 Interrupt Enable Control Bit 1
ITIFRE.IT1E 0 Interrupt Enable Control Bit 0
MISCR 0x0009 Miscellaneous Register
MISCR.LVD 3 Low Voltage Detector
MISCR.CLKDIV 2 Clock Divider
MISCR.USBOE 1 USB enable
MISCR.MCO 0 Main Clock Out selection
ADCDR 0x000A A/D Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x000B A/D Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
WDGCR 0x000C Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000D 0x000D RESERVED
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
TIMCR2 0x0011 Timer Control Register 2
TIMCR2.OC1E 7 Output Compare 1 Pin Enable
TIMCR2.OC2E 6 Output Compare 2 Pin Enable
TIMCR2.OPM 5 One Pulse mode
TIMCR2.PWM 4 Pulse Width Modulation
TIMCR2.CC1 3 Clock Control 1
TIMCR2.CC0 2 Clock Control 0
TIMCR2.IEDG2 1 Input Edge 2
TIMCR2.EXEDG 0 External Clock Edge
TIMCR1 0x0012 Timer Control Register 1
TIMCR1.ICIE 7 Input Capture Interrupt Enable
TIMCR1.OCIE 6 Output Compare Interrupt Enable
TIMCR1.TOIE 5 Timer Overflow Interrupt Enable
TIMCR1.FOLV2 4 Forced Output Compare 2
TIMCR1.FOLV1 3 Forced Output Compare 1
TIMCR1.OLVL2 2 Output Level 2
TIMCR1.IEDG1 1 Input Edge 1
TIMCR1.OLVL1 0 Output Level 1
TIMSR 0x0013 Timer Status Register
TIMSR.ICF1 7 Input Capture Flag 1
TIMSR.OCF1 6 Output Compare Flag 1
TIMSR.TOF 5 Timer Overflow Flag
TIMSR.ICF2 4 Input Capture Flag 2
TIMSR.OCF2 3 Output Compare Flag 2
TIMIC1HR 0x0014 Timer Input Capture 1 High Register
TIMIC1LR 0x0015 Timer Input Capture 1 Low Register
TIMOC1HR 0x0016 Timer Output Compare 1 High Register
TIMOC1LR 0x0017 Timer Output Compare 1 Low Register
TIMCHR 0x0018 Timer Counter High Register
TIMCLR 0x0019 Timer Counter Low Register
TIMACHR 0x001A Timer Alternate Counter High Register
TIMACLR 0x001B Timer Alternate Counter Low Register
TIMIC2HR 0x001C Timer Input Capture 2 High Register
TIMIC2LR 0x001D Timer Input Capture 2 Low Register
TIMOC2HR 0x001E Timer Output Compare 2 High Register
TIMOC2LR 0x001F Timer Output Compare 2 Low Register
SCISR 0x0020 SCI Status register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0021 SCI Data register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0022 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0023 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0024 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
RESERVED0032 0x0032 RESERVED
RESERVED0033 0x0033 RESERVED
RESERVED0034 0x0034 RESERVED
RESERVED0035 0x0035 RESERVED
RESERVED0036 0x0036 RESERVED
RESERVED0037 0x0037 RESERVED
RESERVED0038 0x0038 RESERVED
RESERVED0039 0x0039 RESERVED
RESERVED003A 0x003A RESERVED
RESERVED003B 0x003B RESERVED
RESERVED003C 0x003C RESERVED
RESERVED003D 0x003D RESERVED
RESERVED003E 0x003E RESERVED
RESERVED003F 0x003F RESERVED
.ST72633
; :ST72633 :ST72633K1 :ST72633K1B1 :ST72633K1M1 :ST72T633K1B1 :ST72T633K1M1
; http://us.st.com/stonline/books/pdf/docs/6341.pdf
; RAM=256
; ROM_OTP=4K
; MEMORY MAP
area DATA FSR_1 0x0000:0x0040
area DATA RAM_ 0x0040:0x0140
area BSS RESERVED 0x0140:0xC000
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC TRAP (software) Interrupt Vector
interrupt USB_ESM 0xFFFA USB End Suspend Mode Interrupt Vector
interrupt IT1_IT8 0xFFF8 IT1 to IT8 Interrupt Vector
interrupt TIMER_ 0xFFF6 TIMER Interrupt Vector
interrupt USB_ 0xFFF0 USB Interrupt Vector
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PBDR 0x0002 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0003 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PCDR 0x0004 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0005 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
RESERVED0006 0x0006 RESERVED
RESERVED0007 0x0007 RESERVED
ITIFRE 0x0008 Interrupt Register
ITIFRE.IT8E 7 Interrupt Enable Control Bit 7
ITIFRE.IT7E 6 Interrupt Enable Control Bit 6
ITIFRE.IT6E 5 Interrupt Enable Control Bit 5
ITIFRE.IT5E 4 Interrupt Enable Control Bit 4
ITIFRE.IT4E 3 Interrupt Enable Control Bit 3
ITIFRE.IT3E 2 Interrupt Enable Control Bit 2
ITIFRE.IT2E 1 Interrupt Enable Control Bit 1
ITIFRE.IT1E 0 Interrupt Enable Control Bit 0
MISCR 0x0009 Miscellaneous Register
MISCR.LVD 3 Low Voltage Detector
MISCR.CLKDIV 2 Clock Divider
MISCR.USBOE 1 USB enable
MISCR.MCO 0 Main Clock Out selection
ADCDR 0x000A A/D Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x000B A/D Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
WDGCR 0x000C Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
RESERVED000D 0x000D RESERVED
RESERVED000E 0x000E RESERVED
RESERVED000F 0x000F RESERVED
RESERVED0010 0x0010 RESERVED
TIMCR2 0x0011 Timer Control Register 2
TIMCR2.OC1E 7 Output Compare 1 Pin Enable
TIMCR2.OC2E 6 Output Compare 2 Pin Enable
TIMCR2.OPM 5 One Pulse mode
TIMCR2.PWM 4 Pulse Width Modulation
TIMCR2.CC1 3 Clock Control 1
TIMCR2.CC0 2 Clock Control 0
TIMCR2.IEDG2 1 Input Edge 2
TIMCR2.EXEDG 0 External Clock Edge
TIMCR1 0x0012 Timer Control Register 1
TIMCR1.ICIE 7 Input Capture Interrupt Enable
TIMCR1.OCIE 6 Output Compare Interrupt Enable
TIMCR1.TOIE 5 Timer Overflow Interrupt Enable
TIMCR1.FOLV2 4 Forced Output Compare 2
TIMCR1.FOLV1 3 Forced Output Compare 1
TIMCR1.OLVL2 2 Output Level 2
TIMCR1.IEDG1 1 Input Edge 1
TIMCR1.OLVL1 0 Output Level 1
TIMSR 0x0013 Timer Status Register
TIMSR.ICF1 7 Input Capture Flag 1
TIMSR.OCF1 6 Output Compare Flag 1
TIMSR.TOF 5 Timer Overflow Flag
TIMSR.ICF2 4 Input Capture Flag 2
TIMSR.OCF2 3 Output Compare Flag 2
TIMIC1HR 0x0014 Timer Input Capture 1 High Register
TIMIC1LR 0x0015 Timer Input Capture 1 Low Register
TIMOC1HR 0x0016 Timer Output Compare 1 High Register
TIMOC1LR 0x0017 Timer Output Compare 1 Low Register
TIMCHR 0x0018 Timer Counter High Register
TIMCLR 0x0019 Timer Counter Low Register
TIMACHR 0x001A Timer Alternate Counter High Register
TIMACLR 0x001B Timer Alternate Counter Low Register
TIMIC2HR 0x001C Timer Input Capture 2 High Register
TIMIC2LR 0x001D Timer Input Capture 2 Low Register
TIMOC2HR 0x001E Timer Output Compare 2 High Register
TIMOC2LR 0x001F Timer Output Compare 2 Low Register
RESERVED0020 0x0020 RESERVED
RESERVED0021 0x0021 RESERVED
RESERVED0022 0x0022 RESERVED
RESERVED0023 0x0023 RESERVED
RESERVED0024 0x0024 RESERVED
USBPIDR 0x0025 USB PID Register
USBPIDR.TP3 7 Token PID bit 3
USBPIDR.TP2 6 Token PID bit 2
USBPIDR.RX_SEZ 2 Received single-ended zero
USBPIDR.RXD 1 Received data
USBDMAR 0x0026 USB DMA Address register
USBDMAR.DA15 7 DMA address bit 15
USBDMAR.DA14 6 DMA address bit 14
USBDMAR.DA13 5 DMA address bit 13
USBDMAR.DA12 4 DMA address bit 12
USBDMAR.DA11 3 DMA address bit 11
USBDMAR.DA10 2 DMA address bit 10
USBDMAR.DA9 1 DMA address bit 9
USBDMAR.DA8 0 DMA address bit 8
USBIDR 0x0027 USB Interrupt/DMA Register
USBIDR.DA7 7 DMA address bit 7
USBIDR.DA6 6 DMA address bit 6
USBIDR.EP1 5 Endpoint number 1
USBIDR.EP0 4 Endpoint number 0
USBIDR.CNT3 3 Byte count 3
USBIDR.CNT2 2 Byte count 2
USBIDR.CNT1 1 Byte count 1
USBIDR.CNT0 0 Byte count 0
USBISTR 0x0028 USB Interrupt Status Register
USBISTR.SUSP 7 Suspend mode request
USBISTR.DOVR 6 DMA over/underrun
USBISTR.CTR 5 Correct Transfer
USBISTR.ERR 4 Error
USBISTR.IOVR 3 Interrupt overrun
USBISTR.ESUSP 2 End suspend mode
USBISTR.RESET 1 USB reset
USBISTR.SOF 0 Start of frame
USBIMR 0x0029 USB Interrupt Mask Register
USBIMR.SUSPM 7
USBIMR.DOVRM 6
USBIMR.CTRM 5
USBIMR.ERRM 4
USBIMR.IOVRM 3
USBIMR.ESUSPM 2
USBIMR.RESETM 1
USBIMR.SOFM 0
USBCTLR 0x002A USB Control Register
USBCTLR.RESUME 3 Resume
USBCTLR.PDWN 2 Power down
USBCTLR.FSUSP 1 Force suspend mode
USBCTLR.FRES 0 Force reset
USBDADDR 0x002B USB Device Address Register
USBDADDR.ADD6 6 Device addres 6
USBDADDR.ADD5 5 Device addres 5
USBDADDR.ADD4 4 Device addres 4
USBDADDR.ADD3 3 Device addres 3
USBDADDR.ADD2 2 Device addres 2
USBDADDR.ADD1 1 Device addres 1
USBDADDR.ADD0 0 Device addres 0
USBEP0RA 0x002C USB Endpoint 0 Register A
USBEP0RA.ST_OUT 7 Status out
USBEP0RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP0RA.STAT_TX1 5 Status bit 1, for transmission transfers
USBEP0RA.STAT_TX0 4 Status bit 0, for transmission transfers
USBEP0RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP0RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP0RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP0RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP0RB 0x002D USB Endpoint 0 Register B
USBEP0RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP0RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP0RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RA 0x002E USB Endpoint 1 Register A
USBEP1RA.ST_OUT 7 Status out
USBEP1RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP1RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP1RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP1RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP1RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP1RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP1RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP1RB 0x002F USB Endpoint 1 Register B
USBEP1RB.CTRL 7 Control
USBEP1RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP1RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP1RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP1RB.EA3 3 Endpoint addres 3
USBEP1RB.EA2 2 Endpoint addres 2
USBEP1RB.EA1 1 Endpoint addres 1
USBEP1RB.EA0 0 Endpoint addres 0
USBEP2RA 0x0030 USB Endpoint 2 Register A
USBEP2RA.ST_OUT 7 Status out
USBEP2RA.DTOG_TX 6 Data Toggle, for transmission transfers
USBEP2RA.STAT_TX1 5 Status bits, for transmission transfer 1
USBEP2RA.STAT_TX0 4 Status bits, for transmission transfer 0
USBEP2RA.TBC3 3 Transmit byte count for Endpoint 3
USBEP2RA.TBC2 2 Transmit byte count for Endpoint 2
USBEP2RA.TBC1 1 Transmit byte count for Endpoint 1
USBEP2RA.TBC0 0 Transmit byte count for Endpoint 0
USBEP2RB 0x0031 USB Endpoint 2 Register B
USBEP2RB.CTRL 7 Control
USBEP2RB.DTOG_RX 6 Data toggle, for reception transfers
USBEP2RB.STAT_RX1 5 Status bit 1, for reception transfers
USBEP2RB.STAT_RX0 4 Status bit 0, for reception transfers
USBEP2RB.EA3 3 Endpoint addres 3
USBEP2RB.EA2 2 Endpoint addres 2
USBEP2RB.EA1 1 Endpoint addres 1
USBEP2RB.EA0 0 Endpoint addres 0
RESERVED0032 0x0032 RESERVED
RESERVED0033 0x0033 RESERVED
RESERVED0034 0x0034 RESERVED
RESERVED0035 0x0035 RESERVED
RESERVED0036 0x0036 RESERVED
RESERVED0037 0x0037 RESERVED
RESERVED0038 0x0038 RESERVED
RESERVED0039 0x0039 RESERVED
RESERVED003A 0x003A RESERVED
RESERVED003B 0x003B RESERVED
RESERVED003C 0x003C RESERVED
RESERVED003D 0x003D RESERVED
RESERVED003E 0x003E RESERVED
RESERVED003F 0x003F RESERVED
.ST7263BK1
; :ST7263BK1 :ST7263BK1B1 :ST7263BK1M1 :ST72F63BK1 :ST72F63BK1B1 :ST72F63BK1M1
; http://us.st.com/stonline/books/pdf/docs/7516.pdf
; RAM=512
; ROM_OTP=16K
; MEMORY MAP
; Interrupt and reset vector assignments
; INPUT/OUTPUT PORTS
.ST7263BK2
; :ST7263BK2 :ST7263BK2B1 :ST7263BK2M1 :ST72F63BK2 :ST72F63BK2B1 :ST72F63BK2M1 \
; :ST72F63BK4 :ST72F63BK4B1 :ST72F63BK4M1
; http://us.st.com/stonline/books/pdf/docs/7516.pdf
.ST72651
; :ST72651 :ST72651R4 :ST72651R6 :ST72651R6T1 :ST72F651 :ST72F651AR6T1 \
; :ST72F651R6T1
; http://us.st.com/stonline/books/pdf/docs/7215.pdf
; RAM=5K
; ROM=32K
; MEMORY MAP
; Interrupt and reset vector assignments
; INPUT/OUTPUT PORTS
.ST72652
; :ST72652 :ST72652R4T1 :ST72F651 :ST72F652 :ST72F652R4T1
; http://us.st.com/stonline/books/pdf/docs/7215.pdf
.ST72C171K2B
; :ST72C171K2B :ST72C171K2B6
; http://us.st.com/stonline/books/pdf/docs/6813.pdf
; RAM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x0020
area DATA FSR_2 0x0020:0x0055
area BSS RESERVED 0x0055:0x0070
area DATA FSR_2 0x0070:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
area DATA FLASH_ 0xE000:0xFFE0
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software
interrupt ei0_ 0xFFFA Ext. Interrupt ei0
interrupt ei1_ 0xFFF8 Ext. Interrupt ei1
interrupt CSS_ 0xFFF6 Clock Filter Interrupt
interrupt SPI_ 0xFFF4 Transfer Complete/Mode Fault
interrupt TIMER_16 0xFFF2 TIMER 16
interrupt ART_PWM 0xFFEE Input Capture 1/Timer Overflow
interrupt OA1_ 0xFFEC OA1 Interrupt
interrupt OA2_ 0xFFEA OA2 Interrupt
interrupt SCI_ 0xFFE4 SCI Peripheral Interrupts
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PCDR 0x0008 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0009 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x000A Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.PEI3 7 Polarity Options of External Interrupt ei1 (Port B) 3
MISCR1.PEI2 6 Polarity Options of External Interrupt ei1 (Port B) 2
MISCR1.MCO 5 Main clock out selection
MISCR1.PEI1 4 Polarity Options of External Interrupt ei0 (Port A) 1
MISCR1.PEI0 3 Polarity Options of External Interrupt ei0 (Port A) 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow Mode Select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.SPIOD 4 SPI output disable
MISCR2.P1OS 3 PWM1 output select
MISCR2.P0OS 2 PWM0 output select
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
RESERVED0040 0x0040 RESERVED
RESERVED0041 0x0041 RESERVED
RESERVED0042 0x0042 RESERVED
RESERVED0043 0x0043 RESERVED
RESERVED0044 0x0044 RESERVED
RESERVED0045 0x0045 RESERVED
RESERVED0046 0x0046 RESERVED
RESERVED0047 0x0047 RESERVED
RESERVED0048 0x0048 RESERVED
RESERVED0049 0x0049 RESERVED
RESERVED004A 0x004A RESERVED
RESERVED004B 0x004B RESERVED
RESERVED004C 0x004C RESERVED
RESERVED004D 0x004D RESERVED
RESERVED004E 0x004E RESERVED
RESERVED004F 0x004F RESERVED
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
RESERVED0072 0x0072 RESERVED
RESERVED0073 0x0073 RESERVED
PWMDCR1 0x0074 PWM Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x007A ART Input Capture Control Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x007B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST72C171K2M
; :ST72C171K2M :ST72C171K2M6
; http://us.st.com/stonline/books/pdf/docs/6813.pdf
; RAM=256
; MEMORY MAP
area DATA FSR_1 0x0000:0x000B
area BSS RESERVED 0x000B:0x001B
area DATA FSR_2 0x001B:0x0055
area BSS RESERVED 0x0055:0x0070
area DATA FSR_2 0x0070:0x0080
area DATA RAM_ 0x0080:0x0180
area BSS RESERVED 0x0180:0xE000
area DATA FLASH_ 0xE000:0xFFE0
; Interrupt and reset vector assignments
interrupt __RESET 0xFFFE Reset
interrupt TRAP_ 0xFFFC Software
interrupt ei0_ 0xFFFA Ext. Interrupt ei0
interrupt ei1_ 0xFFF8 Ext. Interrupt ei1
interrupt CSS_ 0xFFF6 Clock Filter Interrupt
interrupt SPI_ 0xFFF4 Transfer Complete/Mode Fault
interrupt TIMER_16 0xFFF2 TIMER 16
interrupt ART_PWM 0xFFEE Input Capture 1/Timer Overflow
interrupt OA1_ 0xFFEC OA1 Interrupt
interrupt OA2_ 0xFFEA OA2 Interrupt
interrupt SCI_ 0xFFE4 SCI Peripheral Interrupts
; INPUT/OUTPUT PORTS
PADR 0x0000 Port A Data Register
PADR.D7 7 Port A Data Register bit 7
PADR.D6 6 Port A Data Register bit 6
PADR.D5 5 Port A Data Register bit 5
PADR.D4 4 Port A Data Register bit 4
PADR.D3 3 Port A Data Register bit 3
PADR.D2 2 Port A Data Register bit 2
PADR.D1 1 Port A Data Register bit 1
PADR.D0 0 Port A Data Register bit 0
PADDR 0x0001 Port A Data Direction Register
PADDR.DD7 7 Port A Data Direction Register bit 7
PADDR.DD6 6 Port A Data Direction Register bit 6
PADDR.DD5 5 Port A Data Direction Register bit 5
PADDR.DD4 4 Port A Data Direction Register bit 4
PADDR.DD3 3 Port A Data Direction Register bit 3
PADDR.DD2 2 Port A Data Direction Register bit 2
PADDR.DD1 1 Port A Data Direction Register bit 1
PADDR.DD0 0 Port A Data Direction Register bit 0
PAOR 0x0002 Port A Option Register
PAOR.O7 7 Port A Option Register bit 7
PAOR.O6 6 Port A Option Register bit 6
PAOR.O5 5 Port A Option Register bit 5
PAOR.O4 4 Port A Option Register bit 4
PAOR.O3 3 Port A Option Register bit 3
PAOR.O2 2 Port A Option Register bit 2
PAOR.O1 1 Port A Option Register bit 1
PAOR.O0 0 Port A Option Register bit 0
RESERVED0003 0x0003 RESERVED
PBDR 0x0004 Port B Data Register
PBDR.D7 7 Port B Data Register bit 7
PBDR.D6 6 Port B Data Register bit 6
PBDR.D5 5 Port B Data Register bit 5
PBDR.D4 4 Port B Data Register bit 4
PBDR.D3 3 Port B Data Register bit 3
PBDR.D2 2 Port B Data Register bit 2
PBDR.D1 1 Port B Data Register bit 1
PBDR.D0 0 Port B Data Register bit 0
PBDDR 0x0005 Port B Data Direction Register
PBDDR.DD7 7 Port B Data Direction Register bit 7
PBDDR.DD6 6 Port B Data Direction Register bit 6
PBDDR.DD5 5 Port B Data Direction Register bit 5
PBDDR.DD4 4 Port B Data Direction Register bit 4
PBDDR.DD3 3 Port B Data Direction Register bit 3
PBDDR.DD2 2 Port B Data Direction Register bit 2
PBDDR.DD1 1 Port B Data Direction Register bit 1
PBDDR.DD0 0 Port B Data Direction Register bit 0
PBOR 0x0006 Port B Option Register
PBOR.O7 7 Port B Option Register bit 7
PBOR.O6 6 Port B Option Register bit 6
PBOR.O5 5 Port B Option Register bit 5
PBOR.O4 4 Port B Option Register bit 4
PBOR.O3 3 Port B Option Register bit 3
PBOR.O2 2 Port B Option Register bit 2
PBOR.O1 1 Port B Option Register bit 1
PBOR.O0 0 Port B Option Register bit 0
RESERVED0007 0x0007 RESERVED
PCDR 0x0008 Port C Data Register
PCDR.D7 7 Port C Data Register bit 7
PCDR.D6 6 Port C Data Register bit 6
PCDR.D5 5 Port C Data Register bit 5
PCDR.D4 4 Port C Data Register bit 4
PCDR.D3 3 Port C Data Register bit 3
PCDR.D2 2 Port C Data Register bit 2
PCDR.D1 1 Port C Data Register bit 1
PCDR.D0 0 Port C Data Register bit 0
PCDDR 0x0009 Port C Data Direction Register
PCDDR.DD7 7 Port C Data Direction Register bit 7
PCDDR.DD6 6 Port C Data Direction Register bit 6
PCDDR.DD5 5 Port C Data Direction Register bit 5
PCDDR.DD4 4 Port C Data Direction Register bit 4
PCDDR.DD3 3 Port C Data Direction Register bit 3
PCDDR.DD2 2 Port C Data Direction Register bit 2
PCDDR.DD1 1 Port C Data Direction Register bit 1
PCDDR.DD0 0 Port C Data Direction Register bit 0
PCOR 0x000A Port C Option Register
PCOR.O7 7 Port C Option Register bit 7
PCOR.O6 6 Port C Option Register bit 6
PCOR.O5 5 Port C Option Register bit 5
PCOR.O4 4 Port C Option Register bit 4
PCOR.O3 3 Port C Option Register bit 3
PCOR.O2 2 Port C Option Register bit 2
PCOR.O1 1 Port C Option Register bit 1
PCOR.O0 0 Port C Option Register bit 0
OA1CR 0x001B OA1 Control Register
OA1CR.AZ1 7 OA1 Autozero Mode.
OA1CR.G12 6 Gain Control 2
OA1CR.G11 5 Gain Control 1
OA1CR.G10 4 Gain Control 0
OA1CR.PS11 3 Positive Input Select / Gain adjust 1
OA1CR.PS10 2 Positive Input Select / Gain adjust 0
OA1CR.NS11 1 Negative Input Select 1
OA1CR.NS10 0 Negative Input Select 0
OA2CR 0x001C OA2 Control Register
OA2CR.AZ2 7 OA2 Autozero Mode
OA2CR.G22 6 Gain Control 2
OA2CR.G21 5 Gain Control 1
OA2CR.G20 4 Gain Control 0
OA2CR.PS21 3 Positive Input Select / Gain adjust 1
OA2CR.PS20 2 Positive Input Select / Gain adjust 0
OA2CR.NS21 1 Negative Input Select 1
OA2CR.NS20 0 Negative Input Select 0
OA3CR 0x001D OA3 Control Register
OA3CR.OA3ON 7 OA3 on/off (low power)
OAIRR 0x001E OA Interrupt & Readout Register
OAIRR.OA1IE 7 OA1 interrupt enable
OAIRR.OA1P 6 OA1 interrupt polarity select
OAIRR.OA1V 5 OA1 output value (read only)
OAIRR.OA1ON 4 OA1 on/off (low power)
OAIRR.OA2IE 3 OA2 interrupt enable
OAIRR.OA2P 2 OA2 interrupt polarity select
OAIRR.OA2V 1 OA2 output value (read only)
OAIRR.OA2ON 0 OA2 on/off (low power)
OAVRCR 0x001F OA Voltage Reference Control Register
OAVRCR.VR2E 7 VR2 Enable
OAVRCR.VR22 6 Voltage selection for channel 2 2
OAVRCR.VR21 5 Voltage selection for channel 2 1
OAVRCR.VR20 4 Voltage selection for channel 2 0
OAVRCR.VR1E 3 VR1 Enable
OAVRCR.VR12 2 Voltage selection for channel 1 2
OAVRCR.VR11 1 Voltage selection for channel 1 1
OAVRCR.VR10 0 Voltage selection for channel 1 0
MISCR1 0x0020 Miscellaneous Register 1
MISCR1.PEI3 7 Polarity Options of External Interrupt ei1 (Port B) 3
MISCR1.PEI2 6 Polarity Options of External Interrupt ei1 (Port B) 2
MISCR1.MCO 5 Main clock out selection
MISCR1.PEI1 4 Polarity Options of External Interrupt ei0 (Port A) 1
MISCR1.PEI0 3 Polarity Options of External Interrupt ei0 (Port A) 0
MISCR1.CP1 2 CPU clock prescaler 1
MISCR1.CP0 1 CPU clock prescaler 0
MISCR1.SMS 0 Slow Mode Select
SPIDR 0x0021 SPI Data I/O Register
SPIDR.D7 7
SPIDR.D6 6
SPIDR.D5 5
SPIDR.D4 4
SPIDR.D3 3
SPIDR.D2 2
SPIDR.D1 1
SPIDR.D0 0
SPICR 0x0022 SPI Control Register
SPICR.SPIE 7 Serial peripheral interrupt enable
SPICR.SPE 6 Serial peripheral output enable
SPICR.SPR2 5 Divider Enable
SPICR.MSTR 4 Master
SPICR.CPOL 3 Clock polarity
SPICR.CPHA 2 Clock phase
SPICR.SPR1 1 Serial peripheral rate 1
SPICR.SPR0 0 Serial peripheral rate 0
SPISR 0x0023 SPI Status Register
SPISR.SPIF 7 Serial Peripheral data transfer flag
SPISR.WCOL 6 Write Collision status
SPISR.MODF 4 Mode Fault flag
WDGCR 0x0024 Watchdog Control Register
WDGCR.WDGA 7 Activation bit
WDGCR.T6 6 timer bit 6
WDGCR.T5 5 timer bit 5
WDGCR.T4 4 timer bit 4
WDGCR.T3 3 timer bit 3
WDGCR.T2 2 timer bit 2
WDGCR.T1 1 timer bit 1
WDGCR.T0 0 timer bit 0
CRSR 0x0025 Clock, Reset, Supply Control / Status Register
CRSR.LVDRF 4 LVD reset flag
CRSR.CSSIE 2 Clock security syst. interrupt enable
CRSR.CSSD 1 Clock security system detection
CRSR.WDGRF 0 Watchdog reset flag
RESERVED0026 0x0026 RESERVED
RESERVED0027 0x0027 RESERVED
RESERVED0028 0x0028 RESERVED
RESERVED0029 0x0029 RESERVED
RESERVED002A 0x002A RESERVED
RESERVED002B 0x002B RESERVED
RESERVED002C 0x002C RESERVED
RESERVED002D 0x002D RESERVED
RESERVED002E 0x002E RESERVED
RESERVED002F 0x002F RESERVED
RESERVED0030 0x0030 RESERVED
TACR2 0x0031 Timer A Control Register 2
TACR2.OC1E 7 Output Compare 1 Pin Enable
TACR2.OC2E 6 Output Compare 2 Pin Enable
TACR2.OPM 5 One Pulse mode
TACR2.PWM 4 Pulse Width Modulation
TACR2.CC1 3 Clock Control 1
TACR2.CC0 2 Clock Control 0
TACR2.IEDG2 1 Input Edge 2
TACR2.EXEDG 0 External Clock Edge
TACR1 0x0032 Timer A Control Register 1
TACR1.ICIE 7 Input Capture Interrupt Enable
TACR1.OCIE 6 Output Compare Interrupt Enable
TACR1.TOIE 5 Timer Overflow Interrupt Enable
TACR1.FOLV2 4 Forced Output Compare 2
TACR1.FOLV1 3 Forced Output Compare 1
TACR1.OLVL2 2 Output Level 2
TACR1.IEDG1 1 Input Edge 1
TACR1.OLVL1 0 Output Level 1
TASR 0x0033 Timer A Status Register
TASR.ICF1 7 Input Capture Flag 1
TASR.OCF1 6 Output Compare Flag 1
TASR.TOF 5 Timer Overflow Flag
TASR.ICF2 4 Input Capture Flag 2
TASR.OCF2 3 Output Compare Flag 2
TAIC1HR 0x0034 Timer A Input Capture 1 High Register
TAIC1LR 0x0035 Timer A Input Capture 1 Low Register
TAOC1HR 0x0036 Timer A Output Compare 1 High Register
TAOC1LR 0x0037 Timer A Output Compare 1 Low Register
TACHR 0x0038 Timer A Counter High Register
TACLR 0x0039 Timer A Counter Low Register
TAACHR 0x003A Timer A Alternate Counter High Register
TAACLR 0x003B Timer A Alternate Counter Low Register
TAIC2HR 0x003C Timer A Input Capture 2 High Register
TAIC2LR 0x003D Timer A Input Capture 2 Low Register
TAOC2HR 0x003E Timer A Output Compare 2 High Register
TAOC2LR 0x003F Timer A Output Compare 2 Low Register
MISCR2 0x0040 Miscellaneous Register 2
MISCR2.SPIOD 4 SPI output disable
MISCR2.P1OS 3 PWM1 output select
MISCR2.P0OS 2 PWM0 output select
MISCR2.SSM 1 SS mode selection
MISCR2.SSI 0 SS internal mode
RESERVED0040 0x0040 RESERVED
RESERVED0041 0x0041 RESERVED
RESERVED0042 0x0042 RESERVED
RESERVED0043 0x0043 RESERVED
RESERVED0044 0x0044 RESERVED
RESERVED0045 0x0045 RESERVED
RESERVED0046 0x0046 RESERVED
RESERVED0047 0x0047 RESERVED
RESERVED0048 0x0048 RESERVED
RESERVED0049 0x0049 RESERVED
RESERVED004A 0x004A RESERVED
RESERVED004B 0x004B RESERVED
RESERVED004C 0x004C RESERVED
RESERVED004D 0x004D RESERVED
RESERVED004E 0x004E RESERVED
RESERVED004F 0x004F RESERVED
SCISR 0x0050 SCI Status Register
SCISR.TDRE 7 Transmit data register empty
SCISR.TC 6 Transmission complete
SCISR.RDRF 5 Received data ready flag
SCISR.IDLE 4 Idle line detect
SCISR.OR 3 Overrun error
SCISR.NF 2 Noise flag
SCISR.FE 1 Framing error
SCIDR 0x0051 SCI Data Register
SCIDR.DR7 7
SCIDR.DR6 6
SCIDR.DR5 5
SCIDR.DR4 4
SCIDR.DR3 3
SCIDR.DR2 2
SCIDR.DR1 1
SCIDR.DR0 0
SCIBRR 0x0052 SCI Baud Rate Register
SCIBRR.SCP1 7 First SCI Prescaler 1
SCIBRR.SCP0 6 First SCI Prescaler 0
SCIBRR.SCT2 5 SCI Transmitter rate divisor 2
SCIBRR.SCT1 4 SCI Transmitter rate divisor 1
SCIBRR.SCT0 3 SCI Transmitter rate divisor 0
SCIBRR.SCR2 2 SCI Receiver rate divisor 2
SCIBRR.SCR1 1 SCI Receiver rate divisor 1
SCIBRR.SCR0 0 SCI Receiver rate divisor 0
SCICR1 0x0053 SCI Control Register 1
SCICR1.R8 7 Receive data bit 8
SCICR1.T8 6 Transmit data bit 8
SCICR1.M 4 Word length
SCICR1.WAKE 3 Wake-Up method
SCICR2 0x0054 SCI Control Register 2
SCICR2.TIE 7 Transmitter interrupt enable
SCICR2.TCIE 6 Transmission complete interrupt enable
SCICR2.RIE 5 Receiver interrupt enable
SCICR2.ILIE 4 Idle line interrupt enable
SCICR2.TE 3 Transmitter enable
SCICR2.RE 2 Receiver enable
SCICR2.RWU 1 Receiver wake-up
SCICR2.SBK 0 Send break
ADCDR 0x0070 A/D CONVERTER Data Register
ADCDR.D7 7 Analog Converted Value 7
ADCDR.D6 6 Analog Converted Value 6
ADCDR.D5 5 Analog Converted Value 5
ADCDR.D4 4 Analog Converted Value 4
ADCDR.D3 3 Analog Converted Value 3
ADCDR.D2 2 Analog Converted Value 2
ADCDR.D1 1 Analog Converted Value 1
ADCDR.D0 0 Analog Converted Value 0
ADCCSR 0x0071 A/D CONVERTER Control/Status Register
ADCCSR.COCO 7 Conversion Complete
ADCCSR.ADON 5 A/D converter On
ADCCSR.CH2 2 Channel Selection 2
ADCCSR.CH1 1 Channel Selection 1
ADCCSR.CH0 0 Channel Selection 0
RESERVED0072 0x0072 RESERVED
RESERVED0073 0x0073 RESERVED
PWMDCR1 0x0074 PWM Duty Cycle Register 1
PWMDCR1.DC7 7 Duty Cycle Data 7
PWMDCR1.DC6 6 Duty Cycle Data 6
PWMDCR1.DC5 5 Duty Cycle Data 5
PWMDCR1.DC4 4 Duty Cycle Data 4
PWMDCR1.DC3 3 Duty Cycle Data 3
PWMDCR1.DC2 2 Duty Cycle Data 2
PWMDCR1.DC1 1 Duty Cycle Data 1
PWMDCR1.DC0 0 Duty Cycle Data 0
PWMDCR0 0x0075 PWM Duty Cycle Register 0
PWMDCR0.DC7 7 Duty Cycle Data 7
PWMDCR0.DC6 6 Duty Cycle Data 6
PWMDCR0.DC5 5 Duty Cycle Data 5
PWMDCR0.DC4 4 Duty Cycle Data 4
PWMDCR0.DC3 3 Duty Cycle Data 3
PWMDCR0.DC2 2 Duty Cycle Data 2
PWMDCR0.DC1 1 Duty Cycle Data 1
PWMDCR0.DC0 0 Duty Cycle Data 0
PWMCR 0x0076 PWM Control Register
PWMCR.OE1 5 PWM Output Enable 1
PWMCR.OE0 4 PWM Output Enable 0
PWMCR.OP1 1 PWM Output Polarity 1
PWMCR.OP0 0 PWM Output Polarity 0
ARTCSR 0x0077 ART Control/Status Register
ARTCSR.EXCL 7 External Clock
ARTCSR.CC2 6 Counter Clock Control 2
ARTCSR.CC1 5 Counter Clock Control 1
ARTCSR.CC0 4 Counter Clock Control 0
ARTCSR.TCE 3 Timer Counter Enable
ARTCSR.FCRL 2 Force Counter Re-Load
ARTCSR.OIE 1 Overflow Interrupt Enable
ARTCSR.OVF 0 Overflow Flag
ARTCAR 0x0078 ART Counter Access Register
ARTCAR.CA7 7 Counter Access Data 7
ARTCAR.CA6 6 Counter Access Data 6
ARTCAR.CA5 5 Counter Access Data 5
ARTCAR.CA4 4 Counter Access Data 4
ARTCAR.CA3 3 Counter Access Data 3
ARTCAR.CA2 2 Counter Access Data 2
ARTCAR.CA1 1 Counter Access Data 1
ARTCAR.CA0 0 Counter Access Data 0
ARTARR 0x0079 ART Auto Reload Register
ARTARR.AR7 7 Counter Auto-Reload Data 7
ARTARR.AR6 6 Counter Auto-Reload Data 6
ARTARR.AR5 5 Counter Auto-Reload Data 5
ARTARR.AR4 4 Counter Auto-Reload Data 4
ARTARR.AR3 3 Counter Auto-Reload Data 3
ARTARR.AR2 2 Counter Auto-Reload Data 2
ARTARR.AR1 1 Counter Auto-Reload Data 1
ARTARR.AR0 0 Counter Auto-Reload Data 0
ARTICCSR 0x007A ART Input Capture Control Status Register
ARTICCSR.CS2 5 Capture Sensitivity 2
ARTICCSR.CS1 4 Capture Sensitivity 1
ARTICCSR.CIE2 3 Capture Interrupt Enable 2
ARTICCSR.CIE1 2 Capture Interrupt Enable 1
ARTICCSR.CF2 1 Capture Flag 2
ARTICCSR.CF1 0 Capture Flag 1
ARTICR1 0x007B ART Input Capture Register 1
ARTICR1.IC7 7 Input Capture Data 7
ARTICR1.IC6 6 Input Capture Data 6
ARTICR1.IC5 5 Input Capture Data 5
ARTICR1.IC4 4 Input Capture Data 4
ARTICR1.IC3 3 Input Capture Data 3
ARTICR1.IC2 2 Input Capture Data 2
ARTICR1.IC1 1 Input Capture Data 1
ARTICR1.IC0 0 Input Capture Data 0
RESERVED007C 0x007C RESERVED
RESERVED007D 0x007D RESERVED
RESERVED007E 0x007E RESERVED
RESERVED007F 0x007F RESERVED
.ST7FDALI
; :ST7FDALI :ST7FDALIF2B6 :ST7FDALIF2M6
; http://us.st.com/stonline/books/pdf/docs/8349.pdf
.ST7FLITE05
; :ST7FLITE05 :ST7FLITE05Y0B6 :ST7FLITE05Y0M6
; http://us.st.com/stonline/books/pdf/docs/8348.pdf
.ST7FLITE09
; :ST7FLITE09 :ST7FLITE09Y0B6 :ST7FLITE09Y0M6
; http://us.st.com/stonline/books/pdf/docs/8348.pdf
.ST7FLITE2
; :ST7FLITE2 :ST7FLITE20 :ST7FLITE20F2B6 :ST7FLITE20F2M6 :ST7FLITE25 \
; :ST7FLITE25F2B6 :ST7FLITE25F2M6 :ST7FLITE29 :ST7FLITE29F2B6 :ST7FLITE29F2M6
; http://us.st.com/stonline/books/pdf/docs/8349.pdf
.ST7FSCR1E4
; :ST7FSCR1E4 :ST7FSCR1R4 :ST7FSCRDIE :ST7SCR :ST7SCR1E4 :ST7SCR1R4 :ST7SCRDIE
; http://us.st.com/stonline/books/pdf/docs/8951.pdf
.ST7HUB
; :ST7HUB
; http://us.st.com/stonline/books/pdf/docs/8375.pdf